KR20010090379A - 반도체패키지 - Google Patents
반도체패키지 Download PDFInfo
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- KR20010090379A KR20010090379A KR1020000015305A KR20000015305A KR20010090379A KR 20010090379 A KR20010090379 A KR 20010090379A KR 1020000015305 A KR1020000015305 A KR 1020000015305A KR 20000015305 A KR20000015305 A KR 20000015305A KR 20010090379 A KR20010090379 A KR 20010090379A
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- semiconductor chip
- semiconductor
- package
- conductive
- lead
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Abstract
Description
Claims (14)
- 상면에 다수의 입출력패드가 형성된 제1반도체칩과;상기 제1반도체칩의 상면에 더 큰 크기로 위치되며, 하면에 다수의 입출력패드가 형성된 제2반도체칩과;상기 제1반도체칩의 외주연과 제2반도체칩의 하면 영역에 형성된 다수의 리드와;상기 제1반도체칩의 입출력패드와 상기 제2반도체칩의 특정 입출력패드를 상호 접속시키고, 또한 상기 제2반도체칩의 다른 입출력패드와 상기 리드를 상호 접속시키는 다수의 도전성 접속수단과;상기 제1반도체칩, 제2반도체칩, 도전성 접속수단 및 리드를 봉지재로 봉지하되, 상기 리드의 하면은 외부로 노출되도록 형성된 패키지몸체를 포함하여 이루어진 반도체패키지.
- 제1항에 있어서, 상기 제1반도체칩의 하면과 제2반도체칩의 상면중 적어도 한 면 또는 양면은 패키지몸체 외측으로 노출된 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서, 상기 도전성 접속수단은 솔더볼, 골드볼 또는 이방성도전필름중 선택된 어느 하나인 것을 특징으로 하는 반도체패키지.
- 제3항에 있어서, 상기 도전성 접속수단으로서 솔더볼 또는 골드볼이 이용되었을 경우, 상기 제2반도체칩의 입출력패드와 리드를 접속시키는 영역의 외주연에는 일정두께의 절연층이 형성된 것을 특징으로 하는 반도체패키지.
- 상면에 다수의 입출력패드가 형성된 제1반도체칩과;상기 제1반도체칩의 상면에 더 작은 위치로 위치되며, 상기 제1반도체칩을 향하여 다수의 입출력패드가 형성된 제2반도체칩과;상기 제1반도체칩의 하면에 접착제에 의해 접착된 칩탑재판과;상기 칩탑재판의 외주연에 일정거리 이격되어 형성된 다수의 리드와;상기 제1반도체칩의 특정 입출력패드와 상기 리드를 상호 접속시키는 다수의 도전성와이어와;상기 제1반도체칩의 다른 입출력패드와 상기 제2반도체칩의 입출력패드를 상호 접속시키는 다수의 도전성 접속수단과;상기 제1반도체칩, 제2반도체칩, 칩탑재판, 리드, 도전성와이어 및 도전성 접속수단을 봉지재로 봉지하되, 상기 칩탑재판 및 리드의 하면은 외부로 노출되도록 형성된 패키지몸체를 포함하여 이루어진 반도체패키지.
- 제5항에 있어서, 상기 제2반도체칩은 상면이 패키지몸체 외측으로 노출된 것을 특징으로 하는 반도체패키지.
- 제5항에 있어서, 상기 제1반도체칩은 리드 상면까지 연장되고, 하면은 접착제로 리드 상면에 접착된 것을 특징으로 하는 반도체패키지.
- 제1항 또는 제5항중 어느 한 항에 있어서, 상기 리드는 칩탑재판을 향하는 단부 하면에 일정 깊이의 부분에칭부가 형성되어 패키지몸체 내측에 결합되어 있고, 상기 부분에칭부의 외주연에는 랜드가 형성되어 패키지몸체 외측으로 노출된 것을 특징으로 하는 반도체패키지.
- 제1항 또는 제5항중 어느 한항에 있어서, 상기 리드는 하면에 적어도 하나 이상의 부분에칭부가 형성되어 패키지몸체에 결합되어 있고, 상기 부분에칭부의 외주연에는 랜드가 형성되어 패키지몸체 외측으로 노출되어 있되, 상기 랜드는 패키지몸체의 하면에 행과 열을 이루며 어레이되어 있는 것을 특징으로 하는 반도체패키지.
- 제8항에 있어서, 상기 랜드에는 도전성볼이 융착된 것을 특징으로 하는 반도체패키지.
- 제9항에 있어서, 상기 랜드에는 도전성볼이 융착된 것을 특징으로 하는 반도체패키지.
- 제2항에 있어서, 상기 패키지몸체 하면으로 노출된 제1반도체칩의 하면에는 도전성페이스트가 더 융착되어 차후 마더보드에 실장 가능하게 된 것을 특징으로 하는 반도체패키지.
- 제5항에 있어서, 상기 칩탑재판의 하면에는 도전성페이스트가 더 융착되어 차후 마더보드에 실장 가능하게 된 것을 특징으로 하는 반도체패키지.
- 제5항에 있어서, 상기 도전성 접속수단은 솔더볼, 골드볼 또는 이방성도전필름중 선택된 어느 하나인 것을 특징으로 하는 반도체패키지.
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JP2000380927A JP2001284523A (ja) | 2000-03-25 | 2000-12-14 | 半導体パッケージ |
US09/816,599 US6759737B2 (en) | 2000-03-25 | 2001-03-23 | Semiconductor package including stacked chips with aligned input/output pads |
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-
2000
- 2000-03-25 KR KR1020000015305A patent/KR100559664B1/ko active IP Right Grant
- 2000-12-14 JP JP2000380927A patent/JP2001284523A/ja active Pending
-
2001
- 2001-03-23 SG SG200101838A patent/SG89386A1/en unknown
- 2001-03-23 US US09/816,599 patent/US6759737B2/en not_active Expired - Lifetime
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KR100576889B1 (ko) * | 2000-12-29 | 2006-05-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
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SG89386A1 (en) | 2002-06-18 |
KR100559664B1 (ko) | 2006-03-10 |
US6759737B2 (en) | 2004-07-06 |
JP2001284523A (ja) | 2001-10-12 |
US20030001252A1 (en) | 2003-01-02 |
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