JPS5773940A - Levelling method of insulation layer - Google Patents

Levelling method of insulation layer

Info

Publication number
JPS5773940A
JPS5773940A JP15017980A JP15017980A JPS5773940A JP S5773940 A JPS5773940 A JP S5773940A JP 15017980 A JP15017980 A JP 15017980A JP 15017980 A JP15017980 A JP 15017980A JP S5773940 A JPS5773940 A JP S5773940A
Authority
JP
Japan
Prior art keywords
film
substrate
films
etching
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15017980A
Other languages
Japanese (ja)
Inventor
Riyouichi Hazuki
Takahiko Moriya
Masahiro Kashiwagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15017980A priority Critical patent/JPS5773940A/en
Priority to DE8181107369T priority patent/DE3164742D1/en
Priority to EP81107369A priority patent/EP0049400B1/en
Priority to US06/304,677 priority patent/US4377438A/en
Publication of JPS5773940A publication Critical patent/JPS5773940A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To decrease unevenness of the surface and permit buried construction of an insulation layer by arranging two layers of insulation films, a film of Si nitride as a principal component for the upper layer, on the uneven surface of the substrate. CONSTITUTION:A thermally oxidized film 2 is formed on a substrate 1, and for example, Al wiring of 1mum thickness is applied on the film 2, and an SiO2 film 41 and an Si nitride film 42 of each thickness of 1mum are attached at low temperature. Then the raised part of the film 41 is etched by 0.5mum by the process of reactive ion etching using a gas mixture of H2 (27%) and CF4. In this etching method, the surface can be leveled because the raised part of the film 42 is etched faster than the recessed part, and etching speed is the same for the films 41 and 42. Also by etching treatment with two layers, the films 41 and 42, arranged as above on the substrate 1 with ditches at the separating region, a constitution of SiO2 film 41 buried in the ditch can be formed evenly without widening or forming birdbeaks.
JP15017980A 1980-09-22 1980-10-28 Levelling method of insulation layer Pending JPS5773940A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP15017980A JPS5773940A (en) 1980-10-28 1980-10-28 Levelling method of insulation layer
DE8181107369T DE3164742D1 (en) 1980-09-22 1981-09-17 Method of smoothing an insulating layer formed on a semiconductor body
EP81107369A EP0049400B1 (en) 1980-09-22 1981-09-17 Method of smoothing an insulating layer formed on a semiconductor body
US06/304,677 US4377438A (en) 1980-09-22 1981-09-22 Method for producing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15017980A JPS5773940A (en) 1980-10-28 1980-10-28 Levelling method of insulation layer

Publications (1)

Publication Number Publication Date
JPS5773940A true JPS5773940A (en) 1982-05-08

Family

ID=15491225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15017980A Pending JPS5773940A (en) 1980-09-22 1980-10-28 Levelling method of insulation layer

Country Status (1)

Country Link
JP (1) JPS5773940A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191354A (en) * 1983-04-14 1984-10-30 Nec Corp Manufacture of semiconductor device
JPS6110240A (en) * 1984-06-20 1986-01-17 Yokogawa Hewlett Packard Ltd Manufacture of semiconductor element
US4587549A (en) * 1982-06-04 1986-05-06 Tokyo Shibaura Denki Kabushiki Kaisha Multilayer interconnection structure for semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587549A (en) * 1982-06-04 1986-05-06 Tokyo Shibaura Denki Kabushiki Kaisha Multilayer interconnection structure for semiconductor device
JPS59191354A (en) * 1983-04-14 1984-10-30 Nec Corp Manufacture of semiconductor device
JPH0226783B2 (en) * 1983-04-14 1990-06-12 Nippon Electric Co
JPS6110240A (en) * 1984-06-20 1986-01-17 Yokogawa Hewlett Packard Ltd Manufacture of semiconductor element

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