JPS5591181A - Field effect semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE: To eliminate adverse effect of erroneous mask size to a gate interval in a field effect semiconductor device by disposing gate regions to partly superimpose each other into upper and lower layers and defining the gate interval by the interval between the superimposed portions.

CONSTITUTION: A p⁺-type buried layer 14 for the first gate is formed in an n^--epitaxial layer 12 on an n⁺-type silicon substrate 10, and an n⁺-type layer 18 interposed between p⁺-type layers 16, 16 for second gate and the layers 16 partly superimposed with the layer 14 are formed on the surface of the layer 12. The portions 12a, 12b interposed between the layers 14 are so controlled as not to close the layer 14 by a depletion layer DP₁ at zero bias time. Channels CH₁∼CH₄ between the layers 16 and 14 are closed (according to specification) by the respective depletion layers DP₁, DP₂ substantially at zero bias time of the layers 14, 16. The channel length L depends upon the superimposition of the layers 14, 16. The channel thickness d depends upon the interval between the layers 14 and 16. Accprding to this configuration the thickness d can be defined accurately by diffusing the layer 16 to thereby equalize the characteristics. Particularly, the erroneous size of the mask for selectively diffusing the layer 16 is regardless of the diffusing depth with no adverse effect to the irregularity of the thickness d.

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