JPS55153369A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS55153369A JPS55153369A JP6201279A JP6201279A JPS55153369A JP S55153369 A JPS55153369 A JP S55153369A JP 6201279 A JP6201279 A JP 6201279A JP 6201279 A JP6201279 A JP 6201279A JP S55153369 A JPS55153369 A JP S55153369A
- Authority
- JP
- Japan
- Prior art keywords
- film
- emitter
- electrode
- layer
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000005530 etching Methods 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 238000005121 nitriding Methods 0.000 abstract 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical group C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract 2
- 238000005546 reactive sputtering Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To form an electrode pattern of an excellent superposing accuracy by forming an emitter size with reactive sputtering etching and by isolating an emitter electrode and a base electrode with an inverted pedestal structure of a nitriding film and an oxidized film. CONSTITUTION:An oxidized film 9 and a nitriding film 10 are formed on the surface of the semiconductor substrate 1 having a base layer 2. Then, the films 9 and 10 are etched with the same etching speed with hydrogen and Freon using a reactive sputtering device, and a window 11 is opened. Next, a polycrystalline Si film 6 containing the impurities to be used for the emitter region formation, is formed on the emitter contact window only, the impurities are pushed in by heat diffusion and an emitter layer 3 is formed. Next, the oxidized film on the surface of the layer 6 is removed, the film 9 under the film 10 is etched at the same time and an inverted pedestal structure is formed. Then, the emitter electrode 7 and the base electrode 8 are formed separately by sputtering an electrode metal on the substrate 1 from the vertical direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201279A JPS55153369A (en) | 1979-05-18 | 1979-05-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201279A JPS55153369A (en) | 1979-05-18 | 1979-05-18 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55153369A true JPS55153369A (en) | 1980-11-29 |
Family
ID=13187807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6201279A Pending JPS55153369A (en) | 1979-05-18 | 1979-05-18 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55153369A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5144408A (en) * | 1985-03-07 | 1992-09-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device and method of manufacturing the same |
-
1979
- 1979-05-18 JP JP6201279A patent/JPS55153369A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5144408A (en) * | 1985-03-07 | 1992-09-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device and method of manufacturing the same |
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