JPS55107243A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55107243A
JPS55107243A JP1374179A JP1374179A JPS55107243A JP S55107243 A JPS55107243 A JP S55107243A JP 1374179 A JP1374179 A JP 1374179A JP 1374179 A JP1374179 A JP 1374179A JP S55107243 A JPS55107243 A JP S55107243A
Authority
JP
Japan
Prior art keywords
film
layer
sio
psg
oxidized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1374179A
Other languages
Japanese (ja)
Inventor
Atsuhiko Menju
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1374179A priority Critical patent/JPS55107243A/en
Publication of JPS55107243A publication Critical patent/JPS55107243A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: To prevent the induction of a disconnection by etching and relieving the difference in level of an oxidized film between the surfaces of an element region and an isolating region in a semiconductor substrate.
CONSTITUTION: An n+ buried layer 12 followed by an n epitaxial layer 13 are piled on a p- Si substrate 11, and the layers are covered by a SiO2 film 14. Masks 16a, 16b of Si3N4 film are applied to the layer above so as to eatch the film 14 and n layer 13 successively and form a concave portion 17. Next if a separated oxidized layer 18 is made through wet oxidization at 1000°C, 9 air pressure and for 60min., thin oxidized films 20a, 20b are produced on the rugged portion 19 and the masks. Excepting the Si3N4 film 16a and the SiO2 layer 14 under that 16a, the remaining one is exposed to a POCl3 gas at a high temperature in order to form a PSG layer on the film 18, then an n+ layer 21, using the diffusion of P. The film 20b is changed into PSG at the same time. Next the film 20b is etched to the extent beyond its thickness so that the PSG on the isolated layer 18 as well as the rugged portion are removed. The films 16b and 14 are removed, thence after SiO2 film 20c, p+ and n+ layers are formed, Al wiring 24W26 is completed. This constitution prevent the occurrence of a disconnection considerably.
COPYRIGHT: (C)1980,JPO&Japio
JP1374179A 1979-02-08 1979-02-08 Manufacture of semiconductor device Pending JPS55107243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1374179A JPS55107243A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1374179A JPS55107243A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55107243A true JPS55107243A (en) 1980-08-16

Family

ID=11841682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1374179A Pending JPS55107243A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55107243A (en)

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