JPH0226783B2 - - Google Patents
Info
- Publication number
- JPH0226783B2 JPH0226783B2 JP58065820A JP6582083A JPH0226783B2 JP H0226783 B2 JPH0226783 B2 JP H0226783B2 JP 58065820 A JP58065820 A JP 58065820A JP 6582083 A JP6582083 A JP 6582083A JP H0226783 B2 JPH0226783 B2 JP H0226783B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- psg
- etching
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特に
ポリシリ段部でのAl配線の断線を防止する有効
な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that is effective in preventing disconnection of Al wiring at a polysilicon step.
半導体素子は拡散、酸化気相成長、フオトリソ
グラフイー、エツチングなどのくり返しで作製さ
れるが、そのために一般に活性領域上にはこれら
の絶縁膜や導電膜が多層に重なりあつて段差が非
常に大きくなつてしまう欠点がある。 Semiconductor devices are fabricated by repeated processes such as diffusion, oxidation vapor phase growth, photolithography, and etching, but as a result, these insulating and conductive films are generally stacked in multiple layers over the active region, resulting in very large steps. It has the disadvantage of getting used to it.
このため配線としてアルミニウム（Al）を用
いて配線を行うと、段差の大きな部分でAl断線
を起こすという欠点が発生しやすく、特にポリシ
リ段部ではこの傾向が顕著であり、ポリシリと
Alの間の層間膜の形状によつてはAlの段切れが
非常に起こりやすい。 For this reason, when aluminum (Al) is used for wiring, it tends to have the disadvantage of causing Al disconnection in areas with large steps, and this tendency is particularly noticeable in polysilicon steps, and
Depending on the shape of the interlayer film between Al layers, breakage of the Al layer is very likely to occur.
このため歩留り上、及び信頼性上の両面から、
ポリシリコンとAl間の層間膜の形状をAl段切れ
のしにくいように平担にすることが望まれてい
る。 Therefore, from both yield and reliability perspectives,
It is desired that the shape of the interlayer film between polysilicon and Al be flat so that the Al layer is less likely to break.
次にどのような場合にAl断線が起こりやすい
かを例示して説明する。 Next, examples of cases in which Al disconnection is likely to occur will be explained.
第１図ａ〜ｂを参照すると、通常のシリコン・
ゲート構造のMOS型LSIで、絶縁膜１２上にゲ
ートポリシリコン１１のフオトリソグラフイ及び
ソース、ドレイン領域１３が半導体基板１４に形
成した状態を第１図ａに示す。 Referring to Figures 1a-b, typical silicon
FIG. 1a shows a MOS type LSI having a gate structure, in which a gate polysilicon 11 is photolithographically formed on an insulating film 12, and source and drain regions 13 are formed on a semiconductor substrate 14.
次いで、気相成長リンガラス膜（以下PSGと
略す）１５を0.5〜1.5μｍの厚さに形成し、1000
℃N2中で10分ほど熱処理して、該リンガラス膜
１５を稠密化する（第１図ｂ）。 Next, a vapor phase grown phosphorus glass film (hereinafter abbreviated as PSG) 15 was formed to a thickness of 0.5 to 1.5 μm, and
The phosphorus glass film 15 is densified by heat treatment in ℃ N2 for about 10 minutes (FIG. 1b).
このときのポリシリ段部付近のPSGの形状を
SEMで観察すると、ポリシリコンとポリシリコ
ンの間隔が狭いところ１６では、PSGが逆テー
パーぎみになつており、この上に、Al配線を行
なつた場合、Alの断切れ、又はAlのシヨートの
発生する確率が非常に高くなつてしまう。 The shape of the PSG near the polysilicon step at this time is
Observation with SEM shows that in areas 16 where the distance between polysilicon and polysilicon is narrow, the PSG is almost inversely tapered. The probability of this occurring becomes extremely high.
これに対する従来の方法は、該PSGの熱処理
を高温の酸化性雰囲気で行なつて該PSGのだら
しを十分に行なう方法があつた。しかし高温で長
時間の熱処理をほどこすとSDの接合が深くなる
こと、及び該ポリシリ１１が酸化されて薄くなつ
てしまうことなどの欠点があり、特に素子の微細
化が進んだ場合には、熱処理はできるだけ少ない
方が望ましい。 A conventional method for this purpose was to heat-treat the PSG in a high-temperature oxidizing atmosphere to sufficiently loosen the PSG. However, if heat treatment is performed at high temperature for a long time, the SD bond will become deep and the polysilicon 11 will be oxidized and become thinner. It is desirable to minimize heat treatment.
又、他の従来方法としては、該PSG上に酸化
シリコン系被膜形成用塗布液（以上、シリカ・フ
イルムと称す）を塗布して、段部の形状を緩和す
る方法がある。 Another conventional method is to apply a coating liquid for forming a silicon oxide film (hereinafter referred to as silica film) on the PSG to soften the shape of the stepped portion.
しかし、この方法では、該シリカ・フイルムの
硬化が不十分な場合、フツ酸系の溶液に対するエ
ツチレートが異常に早いため、次のコンタクトの
穴あけ工程で、ポリシリコン段部に沿つて、バツ
フアードフツ酸がしみ込んで段部のシリカ・フイ
ルムがエツチングされてなくなつてしまう現象
が、特に目合わせズレを起こしたときに発生しや
すいことが判つた。この現象をさけるには、950
℃のスチーム雰囲気で10分程度の熱処理を行なう
必要があり、先に述べたと同様、素子が微細化し
た場合には熱処理を極力少くしたいので問題があ
る。 However, with this method, if the silica film is insufficiently cured, the etching rate for hydrofluoric acid solution is abnormally fast, so buffered hydrofluoric acid is applied along the polysilicon steps in the next contact hole-drilling process. It has been found that the phenomenon in which the silica film in the step part is etched and disappears due to penetration is particularly likely to occur when misalignment occurs. To avoid this phenomenon, 950
It is necessary to perform heat treatment for about 10 minutes in a steam atmosphere at ℃, which is a problem because, as mentioned above, when devices are miniaturized, it is desirable to minimize heat treatment.
従つて、本発明は、上記欠点を解決する方法を
提供するものである。 Therefore, the present invention provides a method to overcome the above-mentioned drawbacks.
本発明の構成はポリシリコンのパターンを形成
し、PSGを成長させたのち、シリカ・フイルム
を塗布し、800℃以下の熱処理を加える工程と、
たとえば、リアクテイブ・イオン・エツチの異方
性エツチングにより、該シリカ・フイルムと
PSGの大部分をエツチングで除去する工程と、
再度、PSG又はSiO2を気相成長法等により、デ
ポジシヨンさせる工程とから成る。 The structure of the present invention includes the steps of forming a polysilicon pattern, growing PSG, applying a silica film, and applying heat treatment at 800°C or less.
For example, by anisotropic etching using reactive ion etching, the silica film can be
A step of removing most of the PSG by etching,
This process again includes a step of depositing PSG or SiO 2 by vapor phase growth or the like.
以下、実施例をもとに説明する。 The following is a description based on examples.
第２図を参照すると、第２図ａは通常のシリコ
ンゲート構造のMOS型LSIで、半導体基板２４
内にソース、ドレイン領域２３が形成され、絶縁
膜２２上のゲートポリシリコン２１が形状形成さ
れている。ここにPSG２５を0.5〜1.5μの厚さに
形成し、更に、シリカフイルム２６を塗布し、
300℃N2中で30分と700℃N2中で60分の熱処理を
行つたものである。 Referring to FIG. 2, FIG. 2a shows a MOS type LSI with a normal silicon gate structure.
Source and drain regions 23 are formed therein, and a gate polysilicon 21 on an insulating film 22 is formed. Here, PSG25 is formed to a thickness of 0.5 to 1.5μ, and a silica film 26 is further applied.
Heat treatment was performed at 300°C N 2 for 30 minutes and at 700°C N 2 for 60 minutes.
次いで、第２図ｂに示すように、リアクテイ
ブ・エツチヤーで該シリカ・フイルムと、PSG
の異方性エツチングを行ない、ポリシリコン上の
PSGがわずかに残つている状態でこのエツチン
グを終了させる。このときのエツチング条件は、
CF4ガス30SCCM、H2ガス10SCCMの流量で、パワー
を300W、圧力が５パスカルであつた。また、上
記条件に於て、該PSGのエツチング−レートは、
380Å／minであり、該シリカ・フイルムは、490
Å／minであつた。 Next, as shown in FIG. 2b, the silica film and PSG are coated using a reactive etcher.
Anisotropic etching is performed on polysilicon.
Finish this etching with a small amount of PSG remaining. The etching conditions at this time are
The flow rate was 30 SCCM of CF 4 gas and 10 SCCM of H 2 gas, the power was 300 W , and the pressure was 5 Pascals. Furthermore, under the above conditions, the etching rate of the PSG is
380 Å/min, and the silica film is 490 Å/min.
The temperature was Å/min.
この状態では、エツチングは素子基板に対し垂
直方向にのみ進み、エツチング前にシリカ・フイ
ルムで平滑化された表面２７がほぼ平行シフトさ
れたなだらかな表面になる。また、シリカ・フイ
ルムは、エツチングで除去されてなくなつてい
る。 In this state, the etching proceeds only in the direction perpendicular to the device substrate, and the surface 27, which was smoothed with a silica film before etching, becomes a smooth surface that is shifted approximately parallel. Also, the silica film has been removed by etching and is no longer present.
次いで、第２図ｃに示すように気相成長法又
は、スパツタリング等でPSG２８を0.5〜1.0μ成
長させると、平担で均一な層間膜ができ上るた
め、Al配線のポリシリ段での断線又はシヨート
を防止することができる。 Next, as shown in Fig. 2c, when PSG28 is grown by 0.5 to 1.0μ by vapor phase epitaxy or sputtering, a flat and uniform interlayer film is created, which prevents disconnection or breakage at the polysilicon stage of the Al wiring. Shoots can be prevented.
また、PSGを熱処理でだらす必要がないので、
該PSG中のリン濃度は濃くする必要がなく、こ
のため、耐湿性には、非常に秀れた素子が出来
る。 In addition, there is no need to heat-treat PSG, so
There is no need to increase the phosphorus concentration in the PSG, and therefore an element with excellent moisture resistance can be produced.
本発明は、リアクテイブ・イオンエツチに対す
るシリカ・フイルムのエツチング速度が、800℃
以下の低温で熱処理した場合でも、極端に早くは
ないこと、特に、PSGとのエツチング速度差が
あまり大きくないこと、という２つの発見に基づ
いている。 In the present invention, the etching rate of silica film for reactive ion etching is 800°C.
This is based on two discoveries: even when heat treated at a low temperature below, the etching rate is not extremely fast, and in particular, the difference in etching rate with PSG is not very large.
シリカ・フイルム及びPSGのエツチング速度
と、熱処理温度との関係を第３図に示す。Ａはシ
リカ・フイルム、ＢはPSGであり、それぞれの
リン含有量は同一で、この場合は、４モル重量パ
ーセントでの値を示している。エツチングの条件
は、実施例で示したのと同じく、ガス流量が
CF430SCCM、H210SCCM、パワー300W、圧力５パス
カルである。又、熱処理は、窒素雰囲気で行つた
ものである。 FIG. 3 shows the relationship between the etching rate of silica film and PSG and the heat treatment temperature. A is a silica film and B is PSG, and the phosphorus content of each is the same, and in this case, the value is expressed as 4 molar weight percent. The etching conditions are the same as shown in the example, with a gas flow rate of
CF 4 30 SCCM , H 2 10 SCCM , power 300 W , pressure 5 Pascal. Further, the heat treatment was performed in a nitrogen atmosphere.
第１図は従来技術を示す断面図、第２図は本発
明の実施例を示す断面図、第３図はシリカ・フイ
ルム及びPSGのエツチング速度と熱処理温度と
の関係を示す図である。
尚、図において、１４，２４……半導体基板、
１３，２３……ソース、ドレイン領域、１２，２
２……絶縁膜、１１，２１……ポリシリコンゲー
ト電極、１５，２５……リンガラス膜、１６……
間隔が狭いところ、２６……シリカ・フイルム、
２７……エツチング前のシリカフイルムの表面、
２８……リンガラス膜である。
FIG. 1 is a sectional view showing the prior art, FIG. 2 is a sectional view showing an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between etching rate and heat treatment temperature of silica film and PSG. In addition, in the figure, 14, 24...semiconductor substrate,
13,23...source, drain region, 12,2
2... Insulating film, 11, 21... Polysilicon gate electrode, 15, 25... Phosphorous glass film, 16...
Where the spacing is narrow, 26...Silica film,
27...Surface of silica film before etching,
28... Phosphorous glass film.
Claims (1)
る段部を含む所定領域上に、第１の絶縁膜を形成
する工程と、前記第１の絶縁膜上に、酸化シリコ
ン系被膜形成用塗布液を塗布する工程と、熱処理
を加えて前記第１の絶縁膜と、該塗布液によるシ
リカ・フイルムを稠密化させる工程と、異方性エ
ツチングにより、該シリカ・フイルムの大部分を
除去するとともに該第１の絶縁膜の表面を平坦化
する工程と、この平坦化された第１の絶縁膜上に
第２の絶縁膜を形成する工程とを含むことを特徴
とする半導体装置の製造方法。1. A step of forming a first insulating film on a predetermined area including a stepped portion of a conductor pattern formed on a semiconductor substrate, and applying a coating liquid for forming a silicon oxide film on the first insulating film. a step of applying heat treatment to densify the first insulating film and the silica film formed by the coating solution; and removing most of the silica film by anisotropic etching and removing the first insulating film. 1. A method for manufacturing a semiconductor device, comprising the steps of: planarizing the surface of an insulating film; and forming a second insulating film on the planarized first insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6582083A JPS59191354A (en) | 1983-04-14 | 1983-04-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6582083A JPS59191354A (en) | 1983-04-14 | 1983-04-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59191354A JPS59191354A (en) | 1984-10-30 |
| JPH0226783B2 true JPH0226783B2 (en) | 1990-06-12 |
Family
ID=13298043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6582083A Granted JPS59191354A (en) | 1983-04-14 | 1983-04-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59191354A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60239042A (en) * | 1984-05-11 | 1985-11-27 | Sony Corp | Manufacture of semiconductor device |
| JPH0669038B2 (en) * | 1984-12-19 | 1994-08-31 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPS61196555A (en) * | 1985-02-26 | 1986-08-30 | Nec Corp | Formation for multilayer interconnection |
| JPS6324625A (en) * | 1986-07-16 | 1988-02-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773940A (en) * | 1980-10-28 | 1982-05-08 | Toshiba Corp | Levelling method of insulation layer |
-
1983
- 1983-04-14 JP JP6582083A patent/JPS59191354A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773940A (en) * | 1980-10-28 | 1982-05-08 | Toshiba Corp | Levelling method of insulation layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59191354A (en) | 1984-10-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5442223A (en) | Semiconductor device with stress relief | |
| JPS63234548A (en) | Manufacture of semiconductor element | |
| JPH0226783B2 (en) | ||
| JP3071268B2 (en) | Method for manufacturing semiconductor device | |
| JP2606315B2 (en) | Method for manufacturing semiconductor device | |
| JPS5812340A (en) | Manufacture of semiconductor device | |
| JPS59148350A (en) | Manufacture of semiconductor device | |
| JPS63302537A (en) | Manufacture of integrated circuit | |
| JPS63260050A (en) | Manufacture of semiconductor device | |
| JPS599937A (en) | Manufacture of semiconductor device | |
| JP3296270B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS63228732A (en) | Manufacture of semiconductor device | |
| JPS61166031A (en) | Etching method of insulation film | |
| JPH035656B2 (en) | ||
| JPH0642510B2 (en) | Method of forming a semiconductor structure | |
| JP2720179B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3158486B2 (en) | Method for manufacturing semiconductor device | |
| JPS5928358A (en) | Manufacture of semiconductor device | |
| JPH04275430A (en) | Manufacture of semiconductor device | |
| JPH04144231A (en) | Manufacture of semiconductor device | |
| JPH0416019B2 (en) | ||
| JPH05308068A (en) | Manufacture of semiconductor device | |
| JPH04369854A (en) | Semiconductor device and manufacture thereof | |
| JPH0148652B2 (en) | ||
| JPH01295427A (en) | Manufacture of semiconductor device |