JPH02106728U - - Google Patents
Info
- Publication number
- JPH02106728U JPH02106728U JP1499589U JP1499589U JPH02106728U JP H02106728 U JPH02106728 U JP H02106728U JP 1499589 U JP1499589 U JP 1499589U JP 1499589 U JP1499589 U JP 1499589U JP H02106728 U JPH02106728 U JP H02106728U
- Authority
- JP
- Japan
- Prior art keywords
- selector
- memory
- delay line
- programmable delay
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
第1図はこの考案による実施例の構成図、第2
図は従来技術によるスキユー補正回路の構成図、
第3図はセレクタの説明図、第4図はスキユーの
発生した波形説明図、第5図はメモリ8の状態説
明図である。
1……セレクタ、2……プログラマブル遅延線
、3……波形整形回路、4……セレクタ、5A,
5B……ドライバ、6……バス、7……レジスタ
、8……メモリ、9……セレクト信号、10……
レジスタ。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figure shows a configuration diagram of a skew correction circuit according to conventional technology.
3 is an explanatory diagram of the selector, FIG. 4 is an explanatory diagram of waveforms where skew occurs, and FIG. 5 is an explanatory diagram of the state of the memory 8. 1... Selector, 2... Programmable delay line, 3... Waveform shaping circuit, 4... Selector, 5A,
5B...Driver, 6...Bus, 7...Register, 8...Memory, 9...Select signal, 10...
register.
Claims (1)
するセレクタ1と、 セレクタ1の出力に遅延を与えるプログラマブ
ル遅延線2と、 セレクタ1の位置とセレクタ1内の遅延時間の
関係データを書き込んだメモリ8とを備え、 セレクタ1の位置により、プログラマブル遅延
線2の遅延量をメモリ8のデータで指定すること
を特徴とするスキユー補正データ転送回路。[Claims for Utility Model Registration] A selector 1 for selecting an arbitrary clock from among a plurality of clocks; a programmable delay line 2 for delaying the output of the selector 1; A skew correction data transfer circuit comprising: a memory 8 in which related data is written; and a delay amount of a programmable delay line 2 is specified by the data of the memory 8 according to the position of the selector 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1499589U JPH02106728U (en) | 1989-02-10 | 1989-02-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1499589U JPH02106728U (en) | 1989-02-10 | 1989-02-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02106728U true JPH02106728U (en) | 1990-08-24 |
Family
ID=31226663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1499589U Pending JPH02106728U (en) | 1989-02-10 | 1989-02-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02106728U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225082A (en) * | 1984-03-30 | 1985-11-09 | ハネウエル・インコーポレーテッド | Pulse synchronizer |
-
1989
- 1989-02-10 JP JP1499589U patent/JPH02106728U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60225082A (en) * | 1984-03-30 | 1985-11-09 | ハネウエル・インコーポレーテッド | Pulse synchronizer |
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