JPH0176626U - - Google Patents

Info

Publication number
JPH0176626U
JPH0176626U JP1987170358U JP17035887U JPH0176626U JP H0176626 U JPH0176626 U JP H0176626U JP 1987170358 U JP1987170358 U JP 1987170358U JP 17035887 U JP17035887 U JP 17035887U JP H0176626 U JPH0176626 U JP H0176626U
Authority
JP
Japan
Prior art keywords
circuit
transmission control
shift register
clock transmission
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987170358U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987170358U priority Critical patent/JPH0176626U/ja
Publication of JPH0176626U publication Critical patent/JPH0176626U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図a,b,c,dおよびeは、前記実施例におけ
る各部の信号波形図、第3図は、従来のクロツク
送出制御回路のブロツク図、第4図a,b,c,
dおよびeは、前記従来例における各部の信号波
形図である。 図において、1……クロツク発生回路、2……
パルス発生回路、3……シフトレジスタ回路、4
……NAND回路、5……NOR回路、6……カ
ウンタ回路、7……クロツク送出制御パルス発生
回路。
Fig. 1 is a block diagram of an embodiment of the present invention;
Figures a, b, c, d and e are signal waveform diagrams of each part in the above embodiment, Figure 3 is a block diagram of a conventional clock transmission control circuit, and Figure 4 a, b, c,
d and e are signal waveform diagrams of each part in the conventional example. In the figure, 1... clock generation circuit, 2...
Pulse generation circuit, 3...Shift register circuit, 4
... NAND circuit, 5 ... NOR circuit, 6 ... counter circuit, 7 ... clock transmission control pulse generation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シリアルデータの送出回路において、所定のク
ロツクの送出数を制御する手段として、シフトレ
ジスタ回路を備えることを特徴とするクロツク送
出制御回路。
1. A clock transmission control circuit for serial data, comprising a shift register circuit as means for controlling the number of clocks to be transmitted.
JP1987170358U 1987-11-06 1987-11-06 Pending JPH0176626U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987170358U JPH0176626U (en) 1987-11-06 1987-11-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987170358U JPH0176626U (en) 1987-11-06 1987-11-06

Publications (1)

Publication Number Publication Date
JPH0176626U true JPH0176626U (en) 1989-05-24

Family

ID=31461226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987170358U Pending JPH0176626U (en) 1987-11-06 1987-11-06

Country Status (1)

Country Link
JP (1) JPH0176626U (en)

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