JPH0210633U - - Google Patents

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例による信号遅延回
路のブロツク図、第２図はこの考案の他の実施例
を示す信号遅延回路のブロツク図、第３図は従来
の信号遅延回路のブロツク図である。 図において、１は入力信号、２は基準クロツク
、１０は遅延信号、１１は遅延量設定回路、１２
は遅延量設定信号、１３は計数回路、１４はアド
レス信号、１５は記憶回路、１６は読み出し信号
、１７はラツチ回路を示す。なお、図中、同一符
号は同一、又は相当部分を示す。 Fig. 1 is a block diagram of a signal delay circuit according to one embodiment of this invention, Fig. 2 is a block diagram of a signal delay circuit showing another embodiment of this invention, and Fig. 3 is a block diagram of a conventional signal delay circuit. It is. In the figure, 1 is an input signal, 2 is a reference clock, 10 is a delay signal, 11 is a delay amount setting circuit, 12
13 is a delay amount setting signal, 13 is a counting circuit, 14 is an address signal, 15 is a storage circuit, 16 is a read signal, and 17 is a latch circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号遅延回路の計数回路で遅延量を設定すると
共に、記憶回路とラツチ回路を用い一定時間後に
再生させるようにしたことを特徴とする信号遅延
回路。 A signal delay circuit characterized in that a delay amount is set by a counting circuit of the signal delay circuit, and the signal is reproduced after a certain period of time using a memory circuit and a latch circuit.