JPS6251600U - - Google Patents
Info
- Publication number
- JPS6251600U JPS6251600U JP13529686U JP13529686U JPS6251600U JP S6251600 U JPS6251600 U JP S6251600U JP 13529686 U JP13529686 U JP 13529686U JP 13529686 U JP13529686 U JP 13529686U JP S6251600 U JPS6251600 U JP S6251600U
- Authority
- JP
- Japan
- Prior art keywords
- data
- random access
- access memory
- address
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Shift Register Type Memory (AREA)
- Pulse Circuits (AREA)
Description
第1図は本考案の一実施例構成、第2図はその
動作説明図である。
図中、1はRAM、2はレジスタ、3はアドレ
ス・カウンタ、4は設定レジスタ、5は第1遅延
回路、6は第2遅延回路をそれぞれ示す。
FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. In the figure, 1 is a RAM, 2 is a register, 3 is an address counter, 4 is a setting register, 5 is a first delay circuit, and 6 is a second delay circuit.
Claims (1)
れるランダム・アクセス・メモリと、 該ランダム・アクセス・メモリの出力データが
セツトされる出力データ保持手段と、 データを遅延するクロツク数を任意に設定する
設定手段と、 入力される該データのクロツクをカウントし、
該設定手段に設定されたクロツク数だけカウント
したときにカウント値をリセツトし、上記ランダ
ム・アクセス・メモリにアドレスを発生するアド
レス・カウンタと、 上記クロツクを所定時間遅延させて上記出力デ
ータ保持手段のデータを取込むタイミングとする
とともに、更に所定時間遅延させて上記ランダム
・アクセス・メモリのデータを書込むタイミング
とする遅延手段を設け、 上記アドレス・カウンタから伝達されるアドレ
スに記入されている領域からデータを読出して保
持した後にそのアドレスに新しいデータを記入し
、入力データを前記周期だけ遅延させて出力する
ようにしたことを特徴とするシフトレジスタ装置
。[Claims for Utility Model Registration] Random access memory into which data is written or read based on addresses, output data holding means into which output data of the random access memory is set, and the number of clocks for delaying the data. a setting means for arbitrarily setting
an address counter that resets the count value when the number of clocks set in the setting means is counted and generates an address in the random access memory; A delay means is provided to set the timing to take in the data and further delay the data by a predetermined time to set the timing to write the data in the random access memory, from the area written in the address transmitted from the address counter. A shift register device characterized in that after reading and holding data, new data is written at the address, and the input data is output after being delayed by the period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13529686U JPS6251600U (en) | 1986-09-03 | 1986-09-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13529686U JPS6251600U (en) | 1986-09-03 | 1986-09-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6251600U true JPS6251600U (en) | 1987-03-31 |
Family
ID=31037347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13529686U Pending JPS6251600U (en) | 1986-09-03 | 1986-09-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6251600U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03102694A (en) * | 1989-09-14 | 1991-04-30 | Mitsubishi Electric Corp | Memory controller |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5515682B2 (en) * | 1972-11-25 | 1980-04-25 |
-
1986
- 1986-09-03 JP JP13529686U patent/JPS6251600U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5515682B2 (en) * | 1972-11-25 | 1980-04-25 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03102694A (en) * | 1989-09-14 | 1991-04-30 | Mitsubishi Electric Corp | Memory controller |
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