JPH03107749U - - Google Patents
Info
- Publication number
- JPH03107749U JPH03107749U JP1429590U JP1429590U JPH03107749U JP H03107749 U JPH03107749 U JP H03107749U JP 1429590 U JP1429590 U JP 1429590U JP 1429590 U JP1429590 U JP 1429590U JP H03107749 U JPH03107749 U JP H03107749U
- Authority
- JP
- Japan
- Prior art keywords
- data signal
- storage device
- processing unit
- central processing
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
Description
第１図はこの考案の１実施例を示すブロツク図
、第２図は１実施例のタイミングチヤート、第３
図は従来例を示すブロツク図、第４図は従来例の
タイミングチヤートである。図において、１……
ライト信号、２……アドレス信号、３……データ
信号、４……中央処理装置、５……記憶装置、６
……アドレスラツチ回路、７……デイレー回路、
８……クロツク、９……遅延データ信号である。
なお、各図中、同一符号は同一または相当部分を
示す。
FIG. 1 is a block diagram showing one embodiment of this invention, FIG. 2 is a timing chart of one embodiment, and FIG.
The figure is a block diagram showing a conventional example, and FIG. 4 is a timing chart of the conventional example. In the figure, 1...
Write signal, 2...Address signal, 3...Data signal, 4...Central processing unit, 5...Storage device, 6
...Address latch circuit, 7...Delay circuit,
8...Clock, 9...Delayed data signal.
In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
、ライト信号の停止と同時にデータ信号を停止す
る中央処理装置と、中央処理装置から送られてき
たデータ信号を受け取る記憶装置と、中央処理装
置から出力されたデータ信号が記憶装置に到達す
るのを所定時間遅らせるデイレー回路を備え、前
記記憶装置へのライト信号の停止時に前記中央処
理装置から出力されるデータ信号を前記記憶装置
が記憶するようにしたことを特徴とする計算機。 A central processing unit that outputs a data signal at the same time as the write signal is output and stops the data signal at the same time as the write signal stops; a storage device that receives the data signal sent from the central processing unit; A delay circuit is provided to delay the arrival of the data signal to the storage device for a predetermined period of time, and the storage device stores the data signal output from the central processing unit when the write signal to the storage device is stopped. A calculator featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1429590U JPH03107749U (en) | 1990-02-16 | 1990-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1429590U JPH03107749U (en) | 1990-02-16 | 1990-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03107749U true JPH03107749U (en) | 1991-11-06 |
Family
ID=31517664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1429590U Pending JPH03107749U (en) | 1990-02-16 | 1990-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03107749U (en) |
-
1990
- 1990-02-16 JP JP1429590U patent/JPH03107749U/ja active Pending
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