JP5802515B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 110
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 90
- 238000005530 etching Methods 0.000 claims description 53
- 238000002955 isolation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 234
- 239000002184 metal Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
実施形態は、BSV方式のTSVを形成する技術に関する。
図1は、実施形態に係わる半導体装置を示している。
尚、以下の説明において、図1と同じ要素には同じ符号を付すことによりその詳細な説明を省略する。
図3は、図2のIII−III線に沿う断面図である。
図5は、図4のV−V線に沿う断面図である。
図7は、図6のVII−VII線に沿う断面図である。
図9は、図8のIX−IX線に沿う断面図である。
図11は、図10のXI−XI線に沿う断面図である。
図13は、図12のXIII−XIII線に沿う断面図である。
図15は、図14のXV−XV線に沿う断面図である。
図17は、図16のXVII−XVII線に沿う断面図である。
次に、半導体装置の製造方法について説明する。
実施形態によれば、高信頼性のBSV方式のTSVを実現できる。
Claims (6)
- 互いに対向する第1と第2の主面を有する半導体基板の前記第1の主面に接するように、開口部を有する絶縁層を埋め込み形成する工程と、
前記第1の主面上にLSIを形成する工程と、
前記絶縁層の前記開口部上に前記LSIに接続される導電層を形成する工程と、
前記半導体基板の前記第2の主面から前記半導体基板を選択的にエッチングすることにより、前記第2の主面から前記半導体基板と前記絶縁層の界面までの範囲内において前記開口部のサイズよりも大きいサイズを有し、前記開口部内において自己整合的に前記開口部のサイズに等しく、前記開口部を介して前記導電層に達するホールを形成する工程と、
前記ホール内にビアを形成する工程と
を具備する半導体装置の製造方法。 - 互いに対向する第1と第2の主面を有し、前記第1の主面にLSIが形成される半導体基板と、
前記第1の主面において前記半導体基板に接して、開口部を有するように埋め込まれた第1の絶縁層と、
前記第1の主面において前記開口部上に形成され、前記LSIに接続される導電層と、
前記第2の主面から前記開口部を介して前記導電層に接続され、前記第2の主面から前記半導体基板と前記第1の絶縁層の第1の界面までの範囲において前記開口部のサイズよりも大きいサイズを有し、前記開口部内において前記開口部のサイズに等しいビアと、
前記第1の主面において、前記第1の絶縁層上に形成され、前記導電層を覆う第2の絶縁層を具備し、
前記導電層のサイズは、前記開口部のサイズより小さい半導体装置。 - 前記第1の絶縁層は、前記LSIを構成する素子を分離する素子分離層の一部である請求項2に記載の半導体装置。
- 互いに対向する第1と第2の主面を有し、前記第1の主面にLSIが形成される半導体基板と、
前記第1の主面において前記半導体基板に接して、開口部を有するように埋め込まれた第1の絶縁層と、
前記第1の主面において前記開口部上に形成され、前記LSIに接続される導電層と、
前記第2の主面から前記開口部を介して前記導電層に接続され、前記第2の主面から前記半導体基板と前記第1の絶縁層の第1の界面までの範囲において前記開口部のサイズよりも大きいサイズを有し、前記開口部内において前記開口部のサイズに等しいビアと、
を具備し、
前記第1の絶縁層及び前記導電層は、それぞれアイランド状である半導体装置。 - 互いに対向する第1と第2の主面を有し、前記第1の主面にLSIが形成される半導体基板と、
前記第1の主面において前記半導体基板に接して、開口部を有するように埋め込まれた第1の絶縁層と、
前記第1の主面において前記開口部上に形成され、前記LSIに接続される導電層と、
前記第2の主面から前記開口部を介して前記導電層に接続され、前記第2の主面から前記半導体基板と前記第1の絶縁層の第1の界面までの範囲において前記開口部のサイズよりも大きいサイズを有し、前記開口部内において前記開口部のサイズに等しいビアと、
前記第1の主面において、前記第1の絶縁層上に形成され、前記導電層を覆う第2の絶縁層を具備し、
前記導電層のサイズは、前記開口部のサイズより小さく、
前記ビアのサイズは、前記第1の及び第2の絶縁層の第2の界面から前記導電層までの範囲において前記導電層のサイズに等しい半導体装置。 - 前記第1の主面において、前記第1の絶縁層上に前記導電層を覆う第2の絶縁層を形成する工程をさらに具備し、
前記導電層を形成する工程は、前記導電層のサイズを前記開口部のサイズより小さく形成する請求項1に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2011230008A JP5802515B2 (ja) | 2011-10-19 | 2011-10-19 | 半導体装置及びその製造方法 |
US13/593,980 US20130099349A1 (en) | 2011-10-19 | 2012-08-24 | Semiconductor device and method of manufacturing the same |
US14/615,400 US9520339B2 (en) | 2011-10-19 | 2015-02-05 | Semiconductor device and method of manufacturing the same |
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JP2011230008A JP5802515B2 (ja) | 2011-10-19 | 2011-10-19 | 半導体装置及びその製造方法 |
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JP2013089816A JP2013089816A (ja) | 2013-05-13 |
JP5802515B2 true JP5802515B2 (ja) | 2015-10-28 |
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JP (1) | JP5802515B2 (ja) |
Families Citing this family (15)
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US20150021773A1 (en) * | 2013-07-22 | 2015-01-22 | Conversant Intellectual Property Management Inc. | Through Semiconductor via Structure with Reduced Stress Proximity Effect |
JP2015041691A (ja) * | 2013-08-21 | 2015-03-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP6499400B2 (ja) * | 2014-04-04 | 2019-04-10 | キヤノン株式会社 | 半導体装置の製造方法 |
JP6479579B2 (ja) * | 2015-05-29 | 2019-03-06 | 東芝メモリ株式会社 | 半導体装置 |
JP6489942B2 (ja) | 2015-05-29 | 2019-03-27 | 東芝メモリ株式会社 | 半導体デバイスの製造方法 |
JP2017050340A (ja) * | 2015-08-31 | 2017-03-09 | 株式会社ソシオネクスト | 半導体装置、及び半導体装置の製造方法 |
JP2017050497A (ja) * | 2015-09-04 | 2017-03-09 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR102652854B1 (ko) * | 2016-08-17 | 2024-04-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
JP2019054199A (ja) * | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | 半導体装置 |
US11355421B2 (en) | 2017-11-14 | 2022-06-07 | Sony Semiconductor Solutions Corporation | Semiconductor device, manufacturing method for semiconductor, and imaging unit |
EP3564994A1 (en) * | 2018-05-03 | 2019-11-06 | ams AG | Semiconductor device with through-substrate via |
JP2019204894A (ja) * | 2018-05-24 | 2019-11-28 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
DE102018215793A1 (de) * | 2018-09-18 | 2020-03-19 | Robert Bosch Gmbh | Verfahren zur Herstellung einer Halbleitervorrichtung sowie Halbleitervorrichtung |
CN111554647B (zh) * | 2020-05-19 | 2022-04-19 | 上海先方半导体有限公司 | 一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法 |
WO2024062796A1 (en) * | 2022-09-22 | 2024-03-28 | Sony Semiconductor Solutions Corporation | Semiconductor apparatus and method of manufacturing semiconductor apparatus |
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JP4433663B2 (ja) | 2001-09-06 | 2010-03-17 | コニカミノルタホールディングス株式会社 | 塗布材塗布方法、被塗布基材、及び被塗布基材を含む塗布材塗布装置 |
JP2004130458A (ja) * | 2002-10-11 | 2004-04-30 | Rohm Co Ltd | 半導体デバイスとその製造方法 |
JP4799542B2 (ja) * | 2007-12-27 | 2011-10-26 | 株式会社東芝 | 半導体パッケージ |
JP5537016B2 (ja) * | 2008-10-27 | 2014-07-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP2011009645A (ja) * | 2009-06-29 | 2011-01-13 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5101575B2 (ja) | 2009-07-28 | 2012-12-19 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2011108690A (ja) * | 2009-11-12 | 2011-06-02 | Panasonic Corp | 半導体装置及びその製造方法 |
US8796135B2 (en) * | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
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2011
- 2011-10-19 JP JP2011230008A patent/JP5802515B2/ja not_active Expired - Fee Related
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2012
- 2012-08-24 US US13/593,980 patent/US20130099349A1/en not_active Abandoned
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2015
- 2015-02-05 US US14/615,400 patent/US9520339B2/en active Active
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US20150155223A1 (en) | 2015-06-04 |
US20130099349A1 (en) | 2013-04-25 |
JP2013089816A (ja) | 2013-05-13 |
US9520339B2 (en) | 2016-12-13 |
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