TWI731694B - 半導體元件結構及其形成方法 - Google Patents

半導體元件結構及其形成方法 Download PDF

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TWI731694B
TWI731694B TW109117094A TW109117094A TWI731694B TW I731694 B TWI731694 B TW I731694B TW 109117094 A TW109117094 A TW 109117094A TW 109117094 A TW109117094 A TW 109117094A TW I731694 B TWI731694 B TW I731694B
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Taiwan
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bonding pad
buffer layer
layer
bump structure
bump
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TW109117094A
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TW202115850A (zh
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朱景升
徐晨祐
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台灣積體電路製造股份有限公司
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Abstract

本揭露的各種實施例涉及一種半導體元件結構，所述半 導體元件結構包括上覆在結合墊上的凸塊結構。結合墊設置在半導體基底之上。蝕刻停止層上覆在結合墊上。緩衝層設置在結合墊之上且將蝕刻停止層與結合墊隔開。凸塊結構包括基部部分及上部部分，基部部分接觸結合墊的上表面，上部部分延伸穿過蝕刻停止層及緩衝層。凸塊結構的基部部分具有第一寬度或直徑且凸塊結構的上部部分具有第二寬度或直徑。第一寬度或直徑大於第二寬度或直徑。

Description

半導體元件結構及其形成方法
本發明實施例是有關於一種半導體元件結構及其形成方法。
半導體晶片用於各種各樣的電子元件及其他元件中且是眾所周知的。如今這種晶片的廣泛使用以及消費者對更強大及更緊密(compact)的元件的需求要求晶片製造商持續減小這些晶片的實體大小及持續增加這些晶片的功能。這種按比例縮小製程(scaling-down process)通常通過提高生產效率及降低相關成本來提供有益效果。然而，由於特徵大小持續減小，因此製作製程持續變得更加難以執行。因此，形成大小越來越小的可靠的半導體元件是一項挑戰。
在本揭露實施例提供一種半導體元件結構。所述半導體元件結構包括：結合墊，設置在半導體基底之上；蝕刻停止層， 上覆在所述結合墊上；緩衝層，設置在所述結合墊之上且將所述蝕刻停止層與所述結合墊隔開；以及凸塊結構，包括基部部分及上部部分，所述基部部分接觸所述結合墊的上表面，所述上部部分延伸穿過所述蝕刻停止層及所述緩衝層，其中所述凸塊結構的所述基部部分具有第一寬度或直徑且所述凸塊結構的所述上部部分具有第二寬度或直徑，所述第一寬度或直徑大於所述第二寬度或直徑。
在本揭露實施例另提供一種半導體元件結構。所述半導體元件結構包括：內連結構，上覆在基底上，所述內連結構包括最頂部導電配線；鈍化結構，上覆在所述內連結構上；結合墊，上覆在所述最頂部導電配線上，其中所述結合墊延伸穿過所述鈍化結構且直接接觸所述最頂部導電配線的頂表面，其中所述結合墊具有在垂直方向上位於所述結合墊的頂表面下方的上表面，且其中所述結合墊的所述上表面在垂直方向上位於所述鈍化結構的頂表面下方；蝕刻停止層，上覆在所述結合墊及所述鈍化結構上；緩衝層，設置在所述蝕刻停止層與所述結合墊之間，其中所述結合墊沿著所述緩衝層的下側連續地延伸並以杯狀包圍所述緩衝層的所述下側；以及凸塊結構，包括基部部分及上部部分，所述基部部分接觸所述結合墊的所述上表面且設置在所述緩衝層內，所述上部部分從所述基部部分向上延伸且延伸穿過所述蝕刻停止層及所述緩衝層，其中所述基部部分具有在所述緩衝層內界定的第一寬度，且所述上部部分具有在所述緩衝層的頂表面上方界定的 第二寬度，且其中所述第一寬度大於所述第二寬度。
在本揭露實施例提供一種形成半導體元件結構的方法。所述形成半導體元件結構的方法包括：在導電配線之上形成鈍化結構；在所述導電配線之上形成結合墊，其中所述結合墊懸在所述鈍化結構上；在所述結合墊之上沉積緩衝層；在所述緩衝層及所述鈍化結構之上沉積蝕刻停止層；在所述蝕刻停止層之上沉積上部介電結構；對所述緩衝層、所述蝕刻停止層及所述上部介電結構執行乾式蝕刻製程，所述乾式蝕刻製程界定上覆在所述結合墊的上表面上的凸塊結構開口，其中在所述乾式蝕刻製程之後，所述緩衝層的一部分上覆在所述結合墊的所述上表面上；對所述緩衝層執行濕式蝕刻製程，所述濕式蝕刻製程移除所述緩衝層的上覆在所述結合墊的所述上表面上的所述一部分，其中所述濕式蝕刻製程使所述凸塊結構開口擴大且暴露出所述結合墊的所述上表面；以及在所述凸塊結構開口中形成凸塊結構。
100、600:互補金屬氧化物半導體(CMOS)晶片
102:基底
103、624:源極/汲極區
104:半導體元件
105:閘極電介質
106:內連結構
107:內連介電結構
108、644b、644c、644d:導通孔
109、622:側壁間隔件
110:導電配線
110a:最頂部導電配線
111:閘極電極
112:鈍化結構
114:結合墊
114a:上部結合墊層
114b:下部結合墊層
114c:中心區
114p:外圍區
114us、116us、302u:上表面
116:緩衝層
118:蝕刻停止層
118ls:下表面
120:凸塊結構
120a:上部導電結構
120b:下部導電結構
120bp:基部部分
120cs:彎曲外側壁/彎曲側壁
120cs1:第一彎曲側壁
120cs2:第二彎曲側壁
120s1、120s2:側壁
120ss1:第一傾斜側壁
120ss2:第二傾斜側壁
120ss3:第三傾斜側壁
120u:上部部分
120vs:垂直外側壁/垂直側壁
200:立體圖
300、400、500a、500b、700、800、900、1000、1100、1200、1300、1400、1500、1600、1700、1800:剖視圖
302:下部介電層
304:上部介電層
306:介電結構
402:第一水平線
404:第二水平線
602:第一半導體元件區
604:第二半導體元件區
608:淺溝渠隔離(STI)區
610、611、612:電晶體
614:閘極電極
618:閘極介電層
626a、626b、626c、626d:金屬間介電(IMD)層
626e:金屬間介電(IMD)層/最頂部IMD層
638a:導電配線層/底部導電配線層
638b、638c:導電配線層
638d:導電配線層/最上部導電配線層
640:介電保護層
644a:導通孔/底部導通孔
650:深溝渠隔離結構
660:導電結合結構
702、906、1102、1404:掩蔽層
802:結合墊開口
902:導電層
904:金屬保護層
1202:深溝渠隔離結構開口
1402:上部介電結構
1502:凸塊結構開口
1900:方法
1902、1904、1906、1908、1910、1912、1914、1916:動作
α:第一角度
β:第二角度
Φ:第三角度
d1:橫向距離
h1:第一高度
h2:第二高度
h3:第三高度
hbs:高度
tbl、tbl’、tbp、tel:厚度
w1:第一寬度
w2:第二寬度
v1:非零垂直距離
結合附圖閱讀以下詳細說明，會最好地理解本揭露的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1示出具有上覆在結合墊(bond pad)上的凸塊結構的互補金屬氧化物半導體(complementary metal-oxide semiconductor， CMOS)晶片的一些實施例的剖視圖，其中結合墊上覆在與半導體元件電耦合的內連結構上。
圖2示出上覆在結合墊上的凸塊結構的一些實施例的立體圖。
圖3示出圖1的凸塊結構的一些替代實施例的剖視圖。
圖4示出圖3的凸塊結構的一段的放大視圖(close-up view)的一些實施例的剖視圖。
圖5A及圖5B示出圖1的凸塊結構的一些替代實施例的剖視圖。
圖6示出具有設置在基底之上的多個半導體元件、上覆在基底上的內連結構以及上覆在內連結構上的凸塊結構的互補金屬氧化物半導體(CMOS)晶片的一些實施例的剖視圖。
圖7到圖18示出形成上覆在結合墊上的凸塊結構的方法的一些實施例的剖視圖。
圖19以流程圖的形式示出一種方法，其示出形成上覆在結合墊上的凸塊結構的方法的一些實施例。
以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述組件及布置的具體實例以簡化本揭露。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵之上或第二特徵上可包括其中第 一特徵與第二特徵被形成為直接接觸的實施例，且也還包括其中第一特徵與第二特徵之間可形成有附加特徵從而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「在...之下(beneath)」、「在...下方(below)」、「下部的(lower)」、「在...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個構件或特徵與另一(其他)構件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括元件在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向)，且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
典型的互補金屬氧化物半導體(CMOS)晶粒包括上覆在基底上的內連結構。一個或多個半導體元件(例如，電晶體、變容器(varactor)、電阻器、電容器)布置在基底中、基底上或基底之上且通過內連結構電耦合到一個或多個結合墊。凸塊結構直接上覆在每一結合墊上且被配置成有利於通過例如金屬結合製程電耦合到印刷電路板(printed circuit board，PCB)或另一CMOS晶粒。
一種形成凸塊結構的方法包括直接在內連結構中在最頂 部導電層之上形成結合墊。在結合墊之上形成蝕刻停止層，且在蝕刻停止層之上形成氧化物層。根據掩蔽層(masking layer)執行第一蝕刻(例如，電漿蝕刻)以移除蝕刻停止層的一部分及氧化物層的一部分，從而界定暴露出結合墊的上表面的凸塊結構開口。為了確保第一蝕刻從結合墊的上表面清除蝕刻停止層，第一蝕刻會輕微地蝕刻到結合墊中。遺憾的是，如在本揭露的一些方面中所理解，當通過第一蝕刻移除此結合墊材料(例如，鋁)時，結合墊材料及/或其副產物可再沉積到凸塊結構開口中的蝕刻停止層的側壁上及氧化物層的側壁上。此外，在一些情況下，此第一蝕刻可包含氟自由基(fluorine free radical)。當氟自由基與結合墊的材料接觸時，氟與結合墊材料可發生反應而在結合墊的上表面上形成副產物。這些副產物可隨後與周圍環境中的濕氣發生反應而產生氫氟酸(hydrofluoric acid，HF)，氫氟酸將腐蝕結合墊的上表面，從而使得結合墊的上表面被損壞且變得粗糙。可執行氬轟擊製程(argon bombardment process)來移除這種腐蝕，但是這會增加製造製程的時間及成本。
然後在結合墊的上表面上形成例如凸塊結構(例如焊料凸塊)。在形成凸塊結構之後，通過第二蝕刻(例如，包括蝕刻劑(例如，氫氟酸)的蒸汽蝕刻(vapor etch))來移除剩餘的氧化物層。在第二蝕刻期間，凸塊結構的側壁上的再沉積材料(例如，鋁)可能從凸塊結構掉落或剝落(peel off)到相鄰的結構上。由於再沉積材料是導電的，因此這些材料可將相鄰的導電結構及/或 相鄰的凸塊結構電短路在一起，從而使得CMOS晶粒上的元件不可操作。此外，即使再沉積材料留在適當的位置，結合墊的被損壞的/粗糙的上表面也會導致長期的可靠性問題，例如由於黏著問題及/或焊料凸塊與結合墊之間的電阻增加而導致長期的可靠性問題。
在本揭露的一些實施例中，為了消除材料從結合墊再沉積到凸塊結構的側壁上且為了在結合墊與焊料凸塊之間提供良好的界面，可在形成蝕刻停止層之前在結合墊之上形成緩衝層。因此，在形成緩衝層之後，可在緩衝層之上形成蝕刻停止層，且可在蝕刻停止層之上形成氧化物層。執行第一蝕刻(例如，包含氟自由基的電漿蝕刻)以移除氧化物層的一部分及蝕刻停止層的一部分，從而界定暴露出緩衝層的上表面的凸塊結構開口。由於第一蝕刻在緩衝層上停止，因此第一蝕刻不會與結合墊接觸且將不會導致結合墊材料再沉積到凸塊結構開口的側壁上。然後執行第二蝕刻(例如，濕式蝕刻)以通過移除緩衝層的暴露部分來使凸塊結構開口延伸從而暴露出結合墊的上表面。由於此第二蝕刻是濕式蝕刻，因此其可對蝕刻停止層進行底切(undercut)且留下具有乾淨側壁的延伸的凸塊結構開口(即，沿著凸塊結構開口的側壁不存在來自結合墊的再沉積材料)。另外，憑藉濕式蝕刻製程，上部結合墊表面是光滑的且為凸塊結構提供良好的接觸界面。因此，當隨後在結合墊之上形成凸塊結構且執行第三蝕刻製程(例如，包含蝕刻劑(例如氫氟酸))以移除剩餘的氧化物層時，結果 會在結合墊與凸塊結構之間實現良好的實體接觸及電接觸。
參照圖1，提供互補金屬氧化物半導體(CMOS)晶片100的一些實施例的剖視圖，所述互補金屬氧化物半導體晶片100具有上覆在結合墊114上的凸塊結構120。
CMOS晶片100包括基底102、內連結構106及通過結合墊114電耦合到內連結構106的凸塊結構120。在基底102上設置有半導體元件104。半導體元件104可例如為電晶體。在前述實例中，半導體元件104可包括：源極/汲極區103，設置在基底102中；閘極電介質105，設置在源極/汲極區103之間；閘極電極111，上覆在閘極電介質105上；以及側壁間隔件109，設置在閘極電極111的側壁及閘極電介質105的側壁周圍。半導體元件104通過內連結構106電耦合到上覆的金屬層、上覆的電子元件(例如，記憶胞、金屬-絕緣體-金屬電容器、電阻器等)、及/或另一CMOS晶粒。
內連結構106包括多個導通孔(conductive via)108、多個導電配線110及內連介電結構107。導通孔108及導電配線110設置在內連介電結構107內且被配置成將半導體元件104電耦合到上覆的導電結構。最頂部導電配線110a直接位於結合墊114之下。
在內連結構106上上覆有鈍化結構112。結合墊114從鈍化結構112的頂表面延伸到最頂部導電配線110a。在結合墊114的上表面114us上上覆有緩衝層116。蝕刻停止層118在鈍化結構 112、結合墊114及緩衝層116之上連續地延伸。在結合墊114上直接上覆有凸塊結構120。凸塊結構120被配置成將結合墊114電耦合到另一CMOS晶粒(未示出)。在一些實施例中，結合墊114的上表面114us包括外圍區114p及中心區114c；且結合墊114的外圍區114p的上部部分懸在鈍化結構112上。外圍區114p的上表面具有從基底102的上表面測量的第一高度h1，且中心區114c的上表面具有從基底102的上表面測量的第二高度h2。第一高度h1大於第二高度h2。
凸塊結構120包括基部部分120bp及上部部分120u，基部部分120b與結合墊114的上表面114us直接接觸，上部部分120u向上延伸穿過蝕刻停止層118。在一些情形中，凸塊結構120的基部部分120bp在第三高度h3處與凸塊結構120的上部部分120u交會，所述第三高度h3小於第一高度h1且大於第二高度h2。基部部分120bp界定在彎曲外側壁(也稱為彎曲側壁)120cs之間；且上部部分120u界定在垂直外側壁(也稱為垂直側壁)120vs之間。彎曲側壁120cs設置在緩衝層116內。垂直側壁120vs從緩衝層116的頂表面延伸到與凸塊結構120的頂表面對應的點。在一些實施例中，凸塊結構120的相對的側壁120s1、120s2是根據剖視圖界定。舉例來說，如果當從上方觀察時凸塊結構120是圓形的/橢圓形的，則當從上方觀察時，相對的側壁120s1、120s2是單個連續側壁，因此當在剖視圖中繪示時，相對的「側壁」120s1、120s2指的是此單個連續側壁自然會呈現出的兩個側壁。另外，如果當 從上方觀察時，凸塊結構120是圓形的或橢圓形的，則與包括凸塊結構120的結構及/或層的剖視圖相關聯的任何長度及/或寬度分別與圓的直徑或在橢圓主軸上的兩個頂點之間界定的長度對應。
通過在緩衝層116中設置彎曲側壁120cs，在製作CMOS晶片100期間，導電材料從結合墊114到凸塊結構120的相對的側壁120s1、120s2的再沉積得到減輕。通過減輕來自結合墊114的導電材料的再沉積，凸塊結構120與相鄰的導電結構電隔離，且因此會提高CMOS晶片100的良率。此外，通過在蝕刻停止層118與結合墊114之間設置緩衝層116，用於製作CMOS晶片100的處理步驟的數目得到減少及/或消除。這在某種程度上減少與製作CMOS晶片100相關聯的良率損失、時間及成本。
參照圖2，提供圖1的凸塊結構120的一些實施例的立體圖200。如圖2中所示，凸塊結構120具有圓柱形狀。因此，凸塊結構120的基部部分(圖1：基部部分120bp)及凸塊結構120的上部部分(圖1：上部部分120u)二者為圓柱形，其中基部部分(圖1：基部部分120bp)的寬度或直徑大於上部部分(圖1：上部部分120u)的寬度或直徑。儘管在圖2中不可見，但是結合墊(圖1：結合墊114)具有矩形/正方形形狀，使得凸塊結構120布置在結合墊(圖1：結合墊114)的內側壁之間。凸塊結構120的頂表面在垂直方向上位於結合墊(圖1：結合墊114)的頂表面上方。
參照圖3，提供圖1的凸塊結構120的一些實施例的剖視圖300。
在蝕刻停止層118及凸塊結構120之上設置有介電結構306。在一些實施例中，介電結構306可例如為或包含氧化物(例如，二氧化矽、氧化金、另一種合適的氧化物等)。在又一些實施例中，介電結構306被省略。結合墊114的下部部分設置在鈍化結構112內。鈍化結構112包括上部介電層304及下部介電層302。上部介電層304可例如為或包含二氧化矽、矽玻璃、未經摻雜的矽玻璃等，及/或可具有介於約5,500埃到6,500埃的範圍內的厚度。下部介電層302可例如為或包含碳化矽、氮化矽等，及/或可具有介於約1,000埃到1,500埃的範圍內的厚度。在鈍化結構112上上覆有蝕刻停止層118。在一些實施例中，蝕刻停止層118可例如為或包含氧化鋁、另一種合適的氧化物等。蝕刻停止層118具有厚度tel，厚度tel可例如介於約100埃到1,000埃的範圍內。
在一些實施例中，結合墊114可例如為或包含鋁、銅、鋁銅、氮化鉭等。在一些實施例中，結合墊114可具有在下部介電層302的底表面與凸塊結構120的底表面之間界定的厚度tbp。厚度tbp可例如介於約1,000埃到8,000埃的範圍內。在又一些實施例中，結合墊114可例如包括包含第一材料(例如，鋁銅)的第一導電層以及包含與第一材料不同的第二材料(例如，氮化鉭)的第二導電層。第一導電層直接上覆在第二導電層上，例如，參見圖5B的上部結合墊層114a及下部結合墊層114b。
在蝕刻停止層118與結合墊114的上表面114us之間設置有緩衝層116。在一些實施例中，緩衝層116可例如為或包含氮化物(例如，氮化鈦、氮化鉭、氮化矽或氮氧化矽)、或氧化物(例如，氧化鈦、二氧化矽或氮氧化矽)、鈦等，及/或可具有介於約100埃到1,000埃的範圍內的厚度tbl。在一些實施例中，如果厚度tbl為100埃或大於100埃，則可在凸塊結構120的製作期間利用濕式蝕刻製程來暴露出結合墊114的上表面114us。在再一些實施例中，如果厚度tbl為1,000埃或小於約1,000埃，則可在執行電漿蝕刻(在凸塊結構120的製作期間)以移除蝕刻停止層118的一部分的同時保護結合墊114的上表面114us。在一些實施例中，如果厚度tbl大於1,000埃，則在沉積製程期間緩衝層116可能易於由於顆粒缺陷而損壞。這可繼而導致緩衝層116與相鄰的層之間的分層(delamination)。憑藉緩衝層116的厚度tbl及材料，在凸塊結構120的製作期間，從結合墊114到凸塊結構120的相對的側壁120s1、120s2的導電材料的再沉積得到減輕。此外，在電漿蝕刻製程期間對結合墊114的上表面114us進行保護的緩衝層116會減輕及/或消除結合墊114的上表面114us的腐蝕(例如，結合墊缺陷問題)。這會減輕及/或省略結合墊114的上表面114us上的處理製程(例如，氬轟擊製程)的利用，從而減少與製作結合墊114及/或凸塊結構120相關聯的良率損失、時間及成本。在一些實施例中，相對的側壁120s1、120s2的彎曲側壁的高度等於厚度tbl。
在一些實施例中，凸塊結構120可例如為或包含鎳、金等，及/或可具有介於約3,000埃到10,000埃的範圍內的高度hbs。凸塊結構120具有在相對的側壁120s1、120s2的垂直側壁之間界定的第一寬度w1。在一些實施例中，第一寬度w1介於約1微米到5微米的範圍內。凸塊結構具有在相對的側壁120s1、120s2的彎曲側壁之間界定的第二寬度w2。在一些實施例中，第二寬度w2介於約1.01微米到5.06微米的範圍內。在又一些實施例中，第二寬度w2大於第一寬度w1。
在一些實施例中，凸塊結構120具有在相對的側壁120s1、120s2的垂直側壁與相對的側壁120s1、120s2的彎曲側壁的外側點之間界定的橫向距離d1。在一些實施例中，橫向距離d1介於約50埃到300埃的範圍內。在又一些實施例中，橫向距離d1的值與緩衝層116的厚度tbl相關。舉例來說，如果厚度tbl為相對薄的(例如，近似100埃)，則橫向距離d1可為相對小的(例如，近似50埃)。在另一實例中，如果厚度tbl為相對厚的(例如，近似1,000埃)，則橫向距離d1可為相對大的(例如，近似300埃)。
參照圖4，提供圖3的凸塊結構120的一段(如圖3中的虛線框所示)的放大視圖的一些實施例的剖視圖400。
如圖4中所示，凸塊結構120與緩衝層116的底切輪廓及蝕刻停止層118的底切輪廓共形。凸塊結構120的側壁120s2包括第一傾斜側壁120ss1、第二傾斜側壁120ss2、第一彎曲側壁120cs1、第二彎曲側壁120cs2及第三傾斜側壁120ss3。第一傾斜 側壁120ss1具有在結合墊114的上表面114us與凸塊結構120之間界定的第一角度α。在一些實施例中，第一角度α介於近似10度到60度的範圍內。第二傾斜側壁120ss2具有在凸塊結構120與第一水平線402之間界定的第二角度β。在一些實施例中，第二角度β介於近似10度到80度的範圍內。在又一些實施例中，第一角度α小於第二角度β。第一彎曲側壁120cs1與緩衝層116的彎曲底切部分直接接觸。第二彎曲側壁120cs2直接上覆在第一彎曲側壁120cs1上且與蝕刻停止層118的底切部分直接接觸。第三傾斜側壁120ss3具有在凸塊結構120與第二水平線404之間界定的第三角度Φ。在一些實施例中，第三角度Φ介於近似10度到90度的範圍內。凸塊結構120的側壁120s2的前述側壁可由在凸塊結構120的製作期間利用的一種或多種蝕刻製程來界定。
參照圖5A，提供圖3的凸塊結構120的替代實施例的剖視圖500a。
凸塊結構120包括上部導電結構120a及下部導電結構120b。在一些實施例中，上部導電結構120a包含第一材料且下部導電結構120b包含與第一材料不同的第二材料。舉例來說，上部導電結構120a的第一材料可為或包含金且下部導電結構120b的第二材料可為或包含鎳。上部導電結構120a的相對的側壁分別包括連續的、直的垂直側壁。下部導電結構120b的相對的側壁分別包括直接上覆在彎曲側壁上的連續的、直的垂直側壁。
參照圖5B，提供圖3的凸塊結構120的替代實施例的剖 視圖500b。
結合墊114包括上部結合墊層114a及位於上部結合墊層114a之下的下部結合墊層114b。上部結合墊層114a包含第一結合墊材料且下部結合墊層114b包含與第一結合墊材料不同的第二結合墊材料。在一些實施例中，第一結合墊材料可例如為或包含鋁、銅、鋁銅等。在一些實施例中，第二結合墊材料可例如為或包含鉭、氮化物、氮化鉭等。上部結合墊層114a直接接觸緩衝層116及凸塊結構120。
參照圖6，提供互補金屬氧化物半導體(CMOS)晶片600的剖視圖，所述互補金屬氧化物半導體晶片600包括上覆在內連結構106上的多個凸塊結構120。
CMOS晶片600包括基底102。基底102可例如為塊狀基底(例如，塊狀矽基底)或絕緣體上矽(silicon-on-insulator，SOI)基底。所示實施例繪示出可在基底102內包括電介質填充溝渠的一個或多個淺溝渠隔離(shallow trench isolation，STI)區608。
在第一半導體元件區602中在STI區608之間設置有電晶體610、611。在第二半導體元件區604中相鄰於STI區608設置有電晶體612。在一些實施例中，第一半導體元件區602可為記憶體陣列區(包括設置在內連結構106中的記憶胞)且第二半導體元件區604可為邏輯區。在又一些實施例中，第一半導體元件區602通過深溝渠隔離結構650而與第二半導體元件區604隔開。電晶體610、611、612分別包括閘極電極614、閘極介電層618、 側壁間隔件622及源極/汲極區624。源極/汲極區624在基底102內設置於每一閘極電極614的任一側上，且被摻雜成具有與每一閘極介電層618下面的通道區的第二導電類型(例如，p型)相反的第一導電類型(例如，n型)。閘極電極614可例如分別為經摻雜的多晶矽或金屬(例如鎢)、矽化物、或其組合。閘極介電層618可例如各自為或包含氧化物(例如，二氧化矽)、或高介電常數介電材料。如本文中所用，高介電常數介電材料是介電常數大於3.9的介電材料。側壁間隔件622可例如由氮化矽製成。
內連結構106布置在基底102之上且包括多個金屬間介電(inter-metal dielectric，IMD)層626a到626e、多個導電配線層638a到638d及多個導通孔644a到644d。IMD層626a到626e可例如分別由低介電常數介電材料(例如，未經摻雜的矽酸鹽玻璃)或氧化物(例如，二氧化矽)製成。如本文中所用，低介電常數介電材料是介電常數小於3.9的介電材料。導電配線層638a到638d形成在溝渠內且可由金屬(例如銅、鋁等)製成。導通孔(也稱為底部導通孔)644a從導電配線層(也稱為底部導電配線層)638a延伸到源極/汲極區624及/或閘極電極614；且導通孔644b到644d在導電配線層638b到638d之間延伸。導通孔644a到644d延伸穿過介電保護層640(其可由介電材料製成及/或可在製造期間充當蝕刻停止層)。介電保護層640可例如由氮化物(例如，氮化矽)、碳化物(例如，碳化矽)、氧化物(例如，氮氧化矽)等製成。導通孔644a到644d可例如各自由金屬(例如銅、鎢等) 製成。
在IMD層(也稱為最頂部IMD層)626e上上覆有鈍化結構112。結合墊114從鈍化結構112的頂表面延伸到導電配線層(也稱為最上部導電配線層)638d。在每一結合墊114上上覆有緩衝層116且在緩衝層116上上覆有蝕刻停止層118。蝕刻停止層118從鈍化結構112連續地延伸到基底102的頂表面下方。蝕刻停止層118以杯狀包圍深溝渠隔離結構650的下側。在每一結合墊114上上覆有凸塊結構120，使得凸塊結構120通過內連結構106電耦合到電晶體610、611、612的源極/汲極區624。在一些實施例中，凸塊結構120各自被配置成圖5A的凸塊結構120，其中每一凸塊結構120具有上部導電結構120a及下部導電結構120b。凸塊結構120被配置成有利於將電晶體610、611、612耦合到另一集成晶片(未示出)。在相鄰的凸塊結構120之間在橫向上設置有導電結合結構660。導電結合結構660被配置成有利於將凸塊結構120結合到另一集成晶片(未示出)。在一些實施例中，導電結合結構660可例如為或包含與結合墊114相同的材料。
圖7到圖18示出形成上覆在結合墊上的凸塊結構的方法的一些實施例的剖視圖700到剖視圖1800。儘管參照方法來闡述圖7到圖18中所示的剖視圖700到剖視圖1800，然而應理解，圖7到圖18中所示的結構並不僅限於所述方法，而是可單獨地獨立於所述方法。此外，儘管圖7到圖18被闡述為一系列動作，然而應理解，這些動作並不是限制性的，這是因為在其他實施例中可 改變所述動作的次序，且所公開的方法也可適用於其他結構。在其他實施例中，可全部或部分地省略所示出及/或所闡述的一些動作。
如圖7的剖視圖700中所示，提供上覆在基底102上的內連介電結構107。在內連介電結構107內設置最頂部導電配線110a且最頂部導電配線110a上覆在基底102上。在最頂部導電配線110a之上形成鈍化結構112。在一些實施例中，鈍化結構112包括上部介電層304及下部介電層302。在上部介電層304之上形成掩蔽層702，以使得上部介電層304的一部分暴露出來。上部介電層304可例如為或包含二氧化矽、矽玻璃、未經摻雜的矽玻璃等且被形成為介於約5,500埃到6,500埃的範圍內的厚度。下部介電層302可例如為或包含碳化矽、氮化矽等且被形成為介於約1,000到1,500埃的範圍內的厚度。上部介電層304及/或下部介電層302可例如通過化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、熱氧化、或另一種合適的沉積製程形成。掩蔽層702可例如為或包括硬罩幕層、光阻等。
如圖8的剖視圖800中所示，根據掩蔽層(圖7的掩蔽層702)將鈍化結構112圖案化，從而界定結合墊開口802且暴露出最頂部導電配線110a的上表面。在一些實施例中，圖案化製程包括將上部介電層304及下部介電層302的未被掩蔽的區暴露到一種或多種蝕刻劑。在再一些實施例中，在形成結合墊開口802 之後，執行移除製程以移除掩蔽層(圖7的掩蔽層702)。
在一些實施例中，圖案化製程包括選擇性蝕刻製程，所述選擇性蝕刻製程包括對上部介電層304執行第一蝕刻(例如，乾式蝕刻)直到暴露出下部介電層302的上表面302u。在一些實施例中，第一蝕刻可對下部介電層302的一部分進行過蝕刻(over etch)且移除下部介電層302的所述一部分，以使得下部介電層302的上表面302u設置在上部介電層304的底表面下方。此外，在執行第一蝕刻之後，對下部介電層302執行第二蝕刻(例如，濕式蝕刻)直到暴露出最頂部導電配線110a的上表面。
如圖9的剖視圖900中所示，在鈍化結構112及最頂部導電配線110a之上形成導電層902及金屬保護層904。導電層902及金屬保護層904填充結合墊開口(圖8的結合墊開口802)。在金屬保護層904之上形成掩蔽層906。在一些實施例中，掩蔽層906可例如為光阻、硬罩幕層等。導電層902可例如為或包含鋁、銅、鋁銅、氮化鉭等且被形成為介於約1,000埃到8,000埃的範圍內的厚度。在又一些實施例中，導電層902可例如包括包含第一材料(例如鋁銅)的第一導電層及包含與第一材料(未示出)不同的第二材料(例如氮化鉭)的第二導電層。在一些實施例中，金屬保護層904可例如為或包含氮氧化矽、碳化矽、氮化矽等且被形成為介於約250埃到350埃的範圍內的厚度。
如圖10的剖視圖1000中所示，根據掩蔽層(圖9的掩蔽層906)將導電層(圖9的導電層902)及金屬保護層904圖案 化，從而界定結合墊114及導電結合結構660。導電結合結構660與結合墊114在橫向上偏置開非零距離。在一些實施例中，在形成結合墊114及導電結合結構660之後，執行移除製程以移除掩蔽層(圖9的掩蔽層906)。
如圖11的剖視圖1100中所示，在鈍化結構112及結合墊114之上形成掩蔽層1102。掩蔽層1102可例如為光阻、硬罩幕等。
如圖12的剖視圖1200中所示，根據掩蔽層(圖11的掩蔽層1102)將鈍化結構112、內連介電結構107及基底102圖案化，從而界定深溝渠隔離結構開口1202。在一些實施例中，圖案化製程包括例如執行高功率電漿蝕刻製程，以移除位於上部介電層304的未被掩蔽的區下面以及設置在鈍化結構112與基底102之間的介電材料。在一些實施例中，深溝渠隔離結構開口1202界定在集成晶片(未示出)的記憶體陣列區與邏輯區之間。在一些實施例中，在執行圖案化製程之後，執行移除製程以移除掩蔽層(圖11的掩蔽層1102)。
如圖13的剖視圖1300中所示，移除金屬保護層(圖12的金屬保護層904)，從而暴露出結合墊114的上表面及導電結合結構660的上表面。
如圖14的剖視圖1400中所示，在結合墊114的上表面之上形成緩衝層116。在一些實施例中，緩衝層116可例如為或包含氮化物(例如，氮化鈦、氮化鉭、氮化矽或氮氧化矽)、或氧化 物(例如，氧化鈦、二氧化矽或氮氧化矽)、鈦等，及/或可被形成有介於約100埃到1,000埃的範圍內的厚度tbl。在一些實施例中，緩衝層116可通過CVD、PVD、ALD、熱氧化、或另一種合適的沉積製程來沉積及/或生長。在緩衝層116、鈍化結構112及基底102之上形成蝕刻停止層118。在一些實施例中，蝕刻停止層118可例如為或包含氧化鋁、氮氧化矽、另一種合適的氧化物等且被形成為介於約100埃到1,000埃的範圍內的厚度。在一些實施例中，蝕刻停止層118與緩衝層116具有相同的厚度。蝕刻停止層118對深溝渠隔離結構開口(圖13的深溝渠隔離結構開口1202)進行襯墊，以使得蝕刻停止層118從結合墊114上方連續地延伸到基底102的溝渠。在一些實施例中，蝕刻停止層118可通過CVD、PVD、ALD、熱氧化、或另一種合適的沉積製程來沉積及/或生長。
此外，如圖14的剖視圖1400中所示，在蝕刻停止層118之上形成上部介電結構1402。上部介電結構1402可例如為或包含氧化金、二氧化矽、另一種氧化物等。上部介電結構1402填充深溝渠隔離結構開口(圖13的深溝渠隔離結構開口1202)。在一些實施例中，上部介電結構1402可通過CVD、PVD、ALD、熱氧化、或另一種合適的沉積製程來沉積及/或生長。在上部介電結構1402之上形成掩蔽層1404。在一些實施例中，掩蔽層1404可例如為硬罩幕、光阻等。掩蔽層1404在結合墊114上方界定開口。
如圖15的剖視圖1500中所示，根據掩蔽層1404將圖14 的結構圖案化，從而在緩衝層116之上界定凸塊結構開口1502。圖案化製程可包括對上部介電結構1402的未被掩蔽的部分及蝕刻停止層118的未被掩蔽的部分執行乾式蝕刻製程(例如，電漿蝕刻製程)。在一些實施例中，乾式蝕刻製程包括將上部介電結構1402及蝕刻停止層118暴露到一種或多種蝕刻劑，例如四氟甲烷(tetrafluoromethane，CF4)、三氟甲烷(trifluoromethane，CHF3)、二氟甲烷(difluoromethane，CH2F2)、六氟化硫(sulfur hexafluoride，SF6)、六氟環丁烯(hexafluorocyclobutene，C4F6)、八氟環戊烯(octafluorocyclopentene，C5F8)、八氟環丁烷(octafluorocyclobutane，C4F8)等。在一些實施例中，乾式蝕刻製程可對緩衝層116的一部分進行過蝕刻且移除緩衝層116的所述一部分，以使得緩衝層116的上表面116us與蝕刻停止層118的下表面118ls在垂直方向上偏置開非零垂直距離v1。因此，乾式蝕刻製程可將緩衝層116在結合墊114的上表面正上方的厚度tbl減小到減小的厚度tbl’。減小的厚度tbl’可例如介於約50埃到900埃的範圍內。在又一些實施例中，上部介電結構1402的側壁及蝕刻停止層118的側壁是傾斜的(未示出)。
在一些實施例中，憑藉緩衝層116的厚度tbl及材料，結合墊114的上表面被保護免受乾式蝕刻製程。舉例來說，如果厚度tbl為100埃或大於100埃，則在乾式蝕刻製程期間移除蝕刻停止層118的一部分之後，緩衝層116的至少一部分將保留在結合墊114的上表面之上。這在某種程度上防止導電材料(例如，鋁) 從結合墊114再沉積到蝕刻停止層118的側壁及上部介電結構1402的側壁，同時減少用於形成凸塊結構開口1502的材料。這在某種程度上防止導電材料(例如，鋁)從結合墊114再沉積到蝕刻停止層118的側壁及上部介電結構1402的側壁，同時有利於在乾式蝕刻製程期間使用高功率蝕刻(即，減少製作時間)。此外，在乾式蝕刻製程期間對結合墊114的上表面進行保護的緩衝層116會減輕及/或消除結合墊114的上表面上的處理製程(例如，利用氬蒸汽(argon vapor))的利用。這在某種程度上減少與製作結合墊114及上覆的凸塊結構(例如，圖17的凸塊結構120)相關聯的時間、成本及良率損失。
如圖16的剖視圖1600中所示，對圖15的結構執行蝕刻製程，從而使凸塊結構開口1502進一步擴大且暴露出結合墊114的上表面。在蝕刻製程之後，緩衝層116包括直接上覆在結合墊114的上表面上的彎曲側壁及/或傾斜側壁(未示出)。蝕刻製程可包括利用一種或多種蝕刻劑的濕式蝕刻製程。在一些實施例中，所述一種或多種蝕刻劑可例如為或包含過氧化氫(hydrogen peroxide，H2O2)。濕式蝕刻製程可例如達到70攝氏度的最大溫度。在一些實施例中，蝕刻製程對緩衝層116是選擇性的，這意味著緩衝層116的材料被所述一種或多種蝕刻劑以第一移除速率蝕刻，且蝕刻停止層118的材料、上部介電結構1402的材料及/或結合墊114的材料被所述一種或多種蝕刻劑以第二移除速率蝕刻，第二移除速率遠小於第一移除速率。在一些實施例中，在暴 露出結合墊114的上表面的蝕刻製程期間，來自結合墊114的導電材料(例如，鋁)不會再沉積到界定凸塊結構開口1502的緩衝層116的側壁上、蝕刻停止層118的側壁上及/或上部介電結構1402的側壁上。在又一些實施例中，在執行蝕刻製程之後，執行移除製程以移除掩蔽層1404(未示出)。
如圖17的剖視圖1700中所示，在凸塊結構開口(圖16的凸塊結構開口1502)中形成凸塊結構120。在一些實施例中，用於形成凸塊結構120的製程可包括：直接在結合墊114之上形成下部導電結構120b，以使得下部導電結構120b與緩衝層116的彎曲側壁及/或傾斜側壁(未示出)共形及/或直接接觸緩衝層116的彎曲側壁及/或傾斜側壁(未示出)；以及隨後在下部導電結構120b之上形成上部導電結構120a。在又一些實施例中，上部導電結構120a包含與下部導電結構120b的第二材料(例如，鎳)不同的第一材料(例如，金)。
如圖18的剖視圖1800中所示，執行蝕刻製程以移除上部介電結構(圖17的上部介電結構1402)。在一些實施例中，蝕刻製程包括執行將圖17的結構暴露到一種或多種蝕刻劑的蒸汽蝕刻及/或濕式蝕刻。所述一種或多種蝕刻劑可例如為或包含氫氟酸。在再一些實施例中，在以所述一種或多種蝕刻劑(例如氫氟酸)執行蝕刻製程之後，沿著凸塊結構120的相對的側壁120s1、120s2的導電材料不會被剝落及/或與相鄰的導電結構(例如，導電結合結構660)一起電短路。因此，由於緩衝層116保護結合墊 114的上表面且由於使用濕式蝕刻製程暴露出結合墊114的上表面，因而導電材料從相對的側壁120s1、120s2的剝落得以減輕及/或不會發生。
圖19示出形成上覆在結合墊上的凸塊結構的方法1900。儘管方法1900被示出及/或闡述為一系列動作或事件，然而應理解，所述方法並非僅限於所示次序或動作。因此，在一些實施例中，這些動作可以與所示不同的次序施行，及/或可同時施行。此外，在一些實施例中，所示動作或事件可被細分為多個動作或事件，這些動作或事件可在單獨的時間施行或者與其他動作或子動作同時施行。在一些實施例中，可省略一些所示動作或事件，且可包括其他未示出的動作或事件。
在動作1902處，提供包括上覆在基底上的最頂部導電配線層的內連結構，且在最頂部導電配線層之上形成鈍化結構。圖7示出與動作1902的一些實施例對應的剖視圖700。
在動作1904處，在最頂部導電配線層之上形成結合墊。結合墊懸在鈍化結構上且直接接觸最頂部導電配線。圖8到圖10示出與動作1904的一些實施例對應的剖視圖800到剖視圖1000。
在動作1906處，將內連結構及基底圖案化，從而界定深溝渠隔離結構開口。深溝渠隔離結構開口與結合墊在橫向上偏置開非零距離。圖11及圖12示出與動作1906的一些實施例對應的剖視圖1100及剖視圖1200。
在動作1908處，在結合墊之上沉積緩衝層，在緩衝層之 上沉積蝕刻停止層，且在蝕刻停止層之上沉積上部介電結構。蝕刻停止層對深溝渠隔離結構開口進行襯墊。圖14示出與動作1908的一些實施例對應的剖視圖1400。
在動作1910處，對緩衝層、蝕刻停止層及上部介電結構執行乾式蝕刻，從而界定凸塊結構開口。圖15示出與動作1910的一些實施例對應的剖視圖1500。
在動作1912處，對緩衝層執行濕式蝕刻，從而使凸塊結構開口擴大且暴露出結合墊的上表面。圖16示出與動作1912的一些實施例對應的剖視圖1600。
在動作1914處，在凸塊結構開口中形成凸塊結構。圖17示出與動作1914的一些實施例對應的剖視圖1700。
在動作1916處，將上部介電結構圖案化，從而暴露出凸塊結構的側壁。圖18示出與動作1916的一些實施例對應的剖視圖1800。
因此，在一些實施例中，本揭露涉及一種包括上覆在導電配線上的結合墊的半導體結構。所述結合墊以杯狀包圍緩衝層的下側表面且凸塊結構延伸穿過緩衝層以接觸結合墊。凸塊結構的側壁包括上覆在彎曲側壁區段上的垂直側壁區段。
在一些實施例中，本揭露提供一種半導體元件結構，所述半導體元件結構包括：結合墊，設置在半導體基底之上；蝕刻停止層，上覆在所述結合墊上；緩衝層，設置在所述結合墊之上且將所述蝕刻停止層與所述結合墊隔開；以及凸塊結構，包括基 部部分及上部部分，所述基部部分接觸所述結合墊的上表面，所述上部部分延伸穿過所述蝕刻停止層及所述緩衝層，其中所述凸塊結構的所述基部部分具有第一寬度或直徑且所述凸塊結構的所述上部部分具有第二寬度或直徑，所述第一寬度或直徑大於所述第二寬度或直徑。在上述半導體元件結構中，所述凸塊結構的所述基部部分在彎曲側壁處與所述緩衝層交會，且所述凸塊結構的所述上部部分在垂直側壁處與所述蝕刻停止層交會。在上述半導體元件結構中，所述半導體元件結構更包括：內連結構，包括設置在所述半導體基底之上的導電配線，其中所述結合墊設置在所述導電配線之上且耦合到所述導電配線；以及鈍化層，上覆在所述內連結構上且沿著所述結合墊的側壁設置。在上述半導體元件結構中，所述蝕刻停止層是由第一材料構成且所述緩衝層是由與所述第一材料不同的第二材料構成。在上述半導體元件結構中，所述第一材料是氧化鋁且所述第二材料是氮化鈦。在上述半導體元件結構中，所述凸塊結構的底表面與所述緩衝層的底表面對齊。在上述半導體元件結構中，所述凸塊結構的所述上部部分包括：下部導電結構，包含第一導電材料；以及上部導電結構，設置在所述下部導電結構之上，其中所述上部導電結構包含與所述第一導電材料不同的第二導電材料。在上述半導體元件結構中，所述第一導電材料是鎳且所述第二導電材料是金。在上述半導體元件結構中，所述結合墊的所述上表面包括外圍區及中心區，所述外圍區在所述半導體基底的上表面之上具有第一高度，所述中 心區在所述半導體基底的所述上表面之上具有第二高度，所述第一高度大於所述第二高度；且其中所述凸塊結構的所述基部部分在第三高度處與所述凸塊結構的所述上部部分交會，所述第三高度小於所述第一高度且大於所述第二高度。
在一些實施例中，本揭露提供一種半導體元件結構，所述半導體元件結構包括：內連結構，上覆在基底上，所述內連結構包括最頂部導電配線；鈍化結構，上覆在所述內連結構上；結合墊，上覆在所述最頂部導電配線上，其中所述結合墊延伸穿過所述鈍化結構且直接接觸所述最頂部導電配線的頂表面，其中所述結合墊具有在垂直方向上位於所述結合墊的頂表面下方的上表面，且其中所述結合墊的所述上表面在垂直方向上位於所述鈍化結構的頂表面下方；蝕刻停止層，上覆在所述結合墊及所述鈍化結構上；緩衝層，設置在所述蝕刻停止層與所述結合墊之間，其中所述結合墊沿著所述緩衝層的下側連續地延伸並以杯狀包圍所述緩衝層的所述下側；以及凸塊結構，包括基部部分及上部部分，所述基部部分接觸所述結合墊的所述上表面且設置在所述緩衝層內，所述上部部分從所述基部部分向上延伸且延伸穿過所述蝕刻停止層及所述緩衝層，其中所述基部部分具有在所述緩衝層內界定的第一寬度，且所述上部部分具有在所述緩衝層的所述頂表面上方界定的第二寬度，且其中所述第一寬度大於所述第二寬度。在上述半導體元件結構中，所述凸塊結構的所述基部部分是在所述緩衝層的底表面與所述緩衝層的上表面之間界定，所述緩衝層 的所述底表面直接接觸所述結合墊的所述上表面，且所述緩衝層的所述上表面直接接觸所述蝕刻停止層，所述凸塊結構的所述基部部分具有彎曲外側壁。在上述半導體元件結構中，所述凸塊結構的所述上部部分是從所述緩衝層的所述上表面到位於所述結合墊的所述頂表面上方的點界定，其中所述凸塊結構的所述上部部分具有垂直側壁。在上述半導體元件結構中，所述基部部分是由鎳構成且所述上部部分包括上覆在鎳層上的金層。在上述半導體元件結構中，所述凸塊結構在所述結合墊的內側壁之間在橫向上間隔開。在上述半導體元件結構中，所述蝕刻停止層在所述緩衝層的外側壁、所述頂表面、內側壁及上表面之上連續地延伸。在上述半導體元件結構中，所述結合墊包括上覆在氮化鉭層上的鋁銅層，其中所述凸塊結構直接接觸所述鋁銅層。在上述半導體元件結構中，所述結合墊及所述緩衝層二者包含氮化物。
在一些實施例中，本揭露提供一種形成半導體元件結構的方法，所述方法包括：在導電配線之上形成鈍化結構；在所述導電配線之上形成結合墊，其中所述結合墊懸在所述鈍化結構上；在所述結合墊之上沉積緩衝層；在所述緩衝層及所述鈍化結構之上沉積蝕刻停止層；在所述蝕刻停止層之上沉積上部介電結構；對所述緩衝層、所述蝕刻停止層及所述上部介電結構執行乾式蝕刻製程，所述乾式蝕刻製程界定上覆在所述結合墊的上表面上的凸塊結構開口，其中在所述乾式蝕刻製程之後，所述緩衝層的一部分上覆在所述結合墊的所述上表面上；對所述緩衝層執行 濕式蝕刻製程，所述濕式蝕刻製程移除所述緩衝層的上覆在所述結合墊的所述上表面上的所述一部分，其中所述濕式蝕刻製程使所述凸塊結構開口擴大且暴露出所述結合墊的上表面；以及在所述凸塊結構開口中形成凸塊結構。在上述形成半導體元件結構的方法中，所述濕式蝕刻製程在直接上覆在所述結合墊的所述上表面上的所述緩衝層中界定彎曲內側壁。在上述形成半導體元件結構的方法中，形成所述凸塊結構包括：直接在所述結合墊的所述上表面之上形成鎳層，其中所述鎳層與所述緩衝層的所述彎曲內側壁共形，且其中所述鎳層包括側壁，所述側壁具有直接上覆在彎曲側壁上的垂直側壁；以及直接在所述鎳層之上形成金層，其中所述金層包括與所述鎳層的所述垂直側壁直接接觸的垂直側壁。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本揭露的各個方面。所屬領域中的技術人員應知，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下在本文中作出各種改變、代替、及變更。
100:互補金屬氧化物半導體(CMOS)晶片
102:基底
103:源極/汲極區
104:半導體元件
105:閘極電介質
106:內連結構
107:內連介電結構
108:導通孔
109:側壁間隔件
110:導電配線
110a:最頂部導電配線
112:鈍化結構
111:閘極電極
114:結合墊
114c:中心區
114p:外圍區
114us:上表面
116:緩衝層
118:蝕刻停止層
120:凸塊結構
120bp:基部部分
120cs:彎曲外側壁/彎曲側壁
120s1、120s2:側壁
120u:上部部分
120vs:垂直外側壁/垂直側壁
h1:第一高度
h2:第二高度
h3:第三高度

Claims (10)

  1. 一種半導體元件結構，包括：結合墊，設置在半導體基底之上；蝕刻停止層，上覆在所述結合墊上；緩衝層，設置在所述結合墊之上且將所述蝕刻停止層與所述結合墊隔開；以及凸塊結構，包括基部部分及上部部分，所述基部部分接觸所述結合墊的上表面，所述上部部分延伸穿過所述蝕刻停止層及所述緩衝層，其中所述凸塊結構的所述基部部分具有第一寬度或直徑且所述凸塊結構的所述上部部分具有第二寬度或直徑，所述第一寬度或直徑大於所述第二寬度或直徑。
  2. 如申請專利範圍第1項所述的半導體元件結構，其中所述凸塊結構的所述基部部分在彎曲側壁處與所述緩衝層交會，且所述凸塊結構的所述上部部分在垂直側壁處與所述蝕刻停止層交會。
  3. 如申請專利範圍第1項所述的半導體元件結構，其中所述蝕刻停止層是由第一材料構成且所述緩衝層是由與所述第一材料不同的第二材料構成。
  4. 如申請專利範圍第1項所述的半導體元件結構，其中所述凸塊結構的底表面與所述緩衝層的底表面對齊。
  5. 如申請專利範圍第1項所述的半導體元件結構，其中所述凸塊結構的所述上部部分包括：下部導電結構，包含第一導電材料；以及上部導電結構，設置在所述下部導電結構之上，其中所述上 部導電結構包含與所述第一導電材料不同的第二導電材料。
  6. 如申請專利範圍第1項所述的半導體元件結構，其中所述結合墊的所述上表面包括外圍區及中心區，所述外圍區在所述半導體基底的上表面之上具有第一高度，所述中心區在所述半導體基底的所述上表面之上具有第二高度，所述第一高度大於所述第二高度；且其中所述凸塊結構的所述基部部分在第三高度處與所述凸塊結構的所述上部部分交會，所述第三高度小於所述第一高度且大於所述第二高度。
  7. 一種半導體元件結構，包括：內連結構，上覆在基底上，所述內連結構包括最頂部導電配線；鈍化結構，上覆在所述內連結構上；結合墊，上覆在所述最頂部導電配線上，其中所述結合墊延伸穿過所述鈍化結構且直接接觸所述最頂部導電配線的頂表面，其中所述結合墊具有在垂直方向上位於所述結合墊的頂表面下方的上表面，且其中所述結合墊的所述上表面在垂直方向上位於所述鈍化結構的頂表面下方；蝕刻停止層，上覆在所述結合墊及所述鈍化結構上；緩衝層，設置在所述蝕刻停止層與所述結合墊之間，其中所述結合墊沿著所述緩衝層的下側連續地延伸並以杯狀包圍所述緩衝層的所述下側；以及凸塊結構，包括基部部分及上部部分，所述基部部分接觸所述結合墊的所述上表面且設置在所述緩衝層內，所述上部部分從 所述基部部分向上延伸且延伸穿過所述蝕刻停止層及所述緩衝層，其中所述基部部分具有在所述緩衝層內界定的第一寬度，且所述上部部分具有在所述緩衝層的頂表面上方界定的第二寬度，且其中所述第一寬度大於所述第二寬度。
  8. 如申請專利範圍第7項所述的半導體元件結構，其中所述凸塊結構的所述基部部分是在所述緩衝層的底表面與所述緩衝層的上表面之間界定，所述緩衝層的所述底表面直接接觸所述結合墊的所述上表面，且所述緩衝層的所述上表面直接接觸所述蝕刻停止層，所述凸塊結構的所述基部部分具有彎曲外側壁。
  9. 一種形成半導體元件結構的方法，包括：在導電配線之上形成鈍化結構；在所述導電配線之上形成結合墊，其中所述結合墊懸在所述鈍化結構上；在所述結合墊之上沉積緩衝層；在所述緩衝層及所述鈍化結構之上沉積蝕刻停止層；在所述蝕刻停止層之上沉積上部介電結構；對所述緩衝層、所述蝕刻停止層及所述上部介電結構執行乾式蝕刻製程，所述乾式蝕刻製程界定上覆在所述結合墊的上表面上的凸塊結構開口，其中在所述乾式蝕刻製程之後，所述緩衝層的一部分上覆在所述結合墊的所述上表面上；對所述緩衝層執行濕式蝕刻製程，所述濕式蝕刻製程移除所述緩衝層的上覆在所述結合墊的所述上表面上的所述一部分，其中所述濕式蝕刻製程使所述凸塊結構開口擴大且暴露出所述結合墊的所述上表面；以及 在所述凸塊結構開口中形成凸塊結構。
  10. 如申請專利範圍第9項所述的形成半導體元件結構的方法，其中所述濕式蝕刻製程在直接上覆在所述結合墊的所述上表面上的所述緩衝層中界定彎曲內側壁。
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