JP5246103B2 - 貫通電極基板の製造方法 - Google Patents
貫通電極基板の製造方法 Download PDFInfo
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- JP5246103B2 JP5246103B2 JP2009194245A JP2009194245A JP5246103B2 JP 5246103 B2 JP5246103 B2 JP 5246103B2 JP 2009194245 A JP2009194245 A JP 2009194245A JP 2009194245 A JP2009194245 A JP 2009194245A JP 5246103 B2 JP5246103 B2 JP 5246103B2
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- electrode substrate
- substrate
- hole
- current
- conductive portion
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Classifications
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Description
図1は本実施形態に係る本発明の貫通電極基板100の断面図である。本実施形態に係る本発明の貫通電極基板100は、コアとなる基板102の表裏を貫通する貫通孔104を備えている。貫通孔104の内部には導通部106が形成されている。基板102はシリコンなどの半導体材料からなり、後述するがエッチング、レーザー、サンドブラスなどの方法により貫通孔104が形成されている。基板102の厚みは例えば10〜800μmであるが、これに限定されるものではない。なお、図1においては、説明の便宜上、貫通孔104を1つしか示していないが、基板102に複数の貫通孔104が形成され、それぞれの貫通孔104に導通部106が形成されるようにしてもよい。また、好ましくは、300〜800μm、又は20〜100μmの範囲の厚さの基板を用途に合わせて適宜選択すればよい。
ここで、図2及び図3を参照して本実施形態に係る本発明の貫通電極基板100の製造方法について説明する。
(1)基板102の準備及び貫通孔104の穿設(図2(A))
本実施形態においては、シリコンからなる基板102を準備する。基板102の厚みは特に限定されないが、300〜800μmである。基板102の一方の面側にレジスト、シリコン酸化膜、シリコン窒化膜、金属などから選択されるマスク(図示せず)を形成した後、そのマスクを介して基板102を厚み方向にエッチングし、貫通孔104を形成する。エッチング方法としてはRIE法、DRIE法などを用いることができる。なお、基板102に対して表裏貫通する貫通孔104をエッチングのみで形成してもよいし、基板102に有底孔を形成した後バックグラインドにより研磨して開口させることによって貫通孔104を形成してもよい。研磨により、基板102の厚みを300μm以下にしてもよい。
基板102の表面に絶縁膜108を形成する。本実施形態においては、絶縁膜108は酸化シリコン膜であり、熱酸化法あるいはCVD法により形成する。絶縁膜108には、酸化シリコン膜の他、窒化シリコン膜、窒化酸化シリコン膜、それらの積層膜などを用いてもよい。
基板102の少なくとも一方の面にシード層110を形成する。シード層110は基板102側にTi層、その上にCu層(以下、Cu/Ti層)、Cu層/TiN層又はCu/Cr層などにより構成される。本実施形態においては、シード層110にはCu/Cr層を用いる。シード層110の成膜方法は、PVD、スパッタ法などから適宜選択できる。シード層110に用いる金属材料は、導通部106の金属材料によって適宜選択することができる。シード層110は、電解メッキによって導通部106を形成するためのシード部及び給電部となる。
電解めっき法を用いてシード層110に給電し、貫通孔104内に金属材料を充填していく。本実施形態においては、貫通孔104に充填する金属材料として、銅(Cu)を用いる。本実施形態においては、図4又は図5に示すように、シード層110に電流をパルス状に供給する電解めっき法によって、貫通孔104内に金属材料を充填する。図4に示すパルス電流の供給方法は、極性を反転させないパルス電流をシード層110に供給する方法である。また、図5に示すパルス電流の供給方法は、周期的に極性を反転させたパルス電流をシード層110に印加する方法である。図5に示すパルス電流の供給によるめっき方法は、PRC(Periodical Reversed Current)法と呼ばれ、シード層110にプラス電圧とマイナス電圧を周期的に印加することによって、シード層110に流れる電流を一定の周期でフォワード(めっきされる側、即ちシード層110側がマイナス電位となる状態(正電流が流れる状態))とリバース(めっきされる側、即ちシード層110側がプラス電位となる状態(負電流が流れる状態))とを切り替えて行うめっき方法の一つであり、好ましいめっき方法の一つである。また、本実施形態のパルス電流による電解めっきにおいては、印加電圧、供給電流、電流密度、パルス切り替え時間(デューティー比)を適宜選択することができる。また、印加電圧、電流密度、パルス切り替え時間(デューティー比)を電解めっきの途中で変化させてもよい。パルス電流を供給することによってシード層110に流れる電流は、正電圧が印加されているときには0.5A以上1.5A以下の電流が流れ、負電圧が印加されているときには−6A以上−2A以下の電流が流れるようにしてもよい。
シード層110及び導通部106の不要部をエッチングあるいはCMP(Chemical Mechanical Polishing:化学機械研磨)により除去することにより、導通部106を形成する。以上のプロセスによって、本実施形態に係る本発明の貫通電極基板100を得ることができる。
ここでは、本実施形態に係る本発明の貫通電極基板100の製造方法の別の例について説明する。上述の貫通電極基板100の製造方法1と同様の構成については、改めて説明しない場合がある。なお、ここで説明する本実施形態に係る本発明の貫通電極基板100の製造方法2は、貫通孔の深さが比較的浅い場合(例えば、20μm〜100μm程度)の又は厚さが20〜100μm程度の薄い貫通電極基板を得たい場合によく用いられる。
基板102の一方の面側にレジスト、シリコン酸化膜、シリコン窒化膜、金属などから選択されるマスク(図示せず)を形成した後、そのマスクを介して基板102を厚み方向にエッチングし、基板102を貫通しない有底孔112を形成する。エッチング方法としてはRIE法、DRIE法などを用いることができる。
基板102の表面に絶縁膜108を形成する。
絶縁膜108が形成されている基板102面にシード層114を形成する。このシード層114は、図3(C)に示すように、孔112の内部にも形成する。シード層114は、上述のシード層110と同様、Cu層/Ti層などにより構成される。シード層114は、シード層110と同様、電解メッキによって導通部106を形成するためのシード部及び給電部となる。シード層114は、MOCVD法、スパッタ法又は蒸着法等によって形成される。
電解めっき法を用いてシード層114に給電し、孔112内に金属材料を充填していく。本実施形態の貫通電極基板の製造方法2においても、貫通電極基板の製造方法1と同様、図4又は図5に示すように、シード層110に電流をパルス状に供給する電解めっき法によって、貫通孔112内に金属材料を充填する。なお、パルス電流を供給する前に、図6に示すように、一定の直流電流をシード層110に供給してもよい。本実施形態においては、孔112に充填する金属材料として、銅(Cu)を用いた。貫通孔104に充填する金属材料としては、銅の他、金(Au)、ロジウム(Rh)、銀(Ag)、白金(Pt)、スズ(Sn)、アルミニウム(Al)、ニッケル(Ni)、クロム(Cr)等の金属及びこれらの合金などから選択され組み合わせた材料を用いることができる。
シード層114及び導通部106の不要部をエッチングあるいはCMPにより除去する。また、孔112が形成されている側と反対側の基板102面をバックグラインドによって導通部106の表面が露出するまで研磨することにより、導通部106を形成する。研磨により、基板102の厚さを薄くしてもよい。以上のプロセスによって、本実施形態に係る本発明の貫通電極基板100を得ることができる。
以下、本発明の貫通電極基板100の実施例について説明する。厚さ650μmの基板102を洗浄後、基板102の一方の面側にレジストを塗布し、露光、現像することにより、マスク(図示せず)を形成する。その後、そのマスクを介して基板102を厚み方向にDRIE法によりエッチングし、430μmの有底孔112を形成する(図2(A))。レジストからなるマスクを除去した後、バックグラインドにより400μmの厚さとなるまで基板102を研磨する。
ここで、図7及び図8を参照して、本実施形態に係る導通部106の金属材料の結晶粒径の分析に用いる後方散乱電子線回折法(Electron backscatter diffraction Pattern:EBSD)について説明する。
(結晶粒径の測定)
本実施形態に係る本発明の貫通電極基板100の導通部106を構成する金属材料の結晶粒径の測定は、EBSD法によって行う。図7はEBSD装置の構成を説明する図である。また、図8はEBSD装置により測定する試料測定の概念を説明する図である。本実施形態に係る導通部106の結晶粒径を測定するにあたっては、貫通部106の断面部に電子線212が照射されるように調節する。
使用した分析装置
SEM 日本電子製 JSM−7000FEBSD TSL社製 OIM ソフトウエアVer.4.6
観察条件
EBSD測定
加速電圧 25kV
試料傾斜角 70°
測定ステップ 0.3μm
(比較例1)
貫通孔に金属材料を充填する前までの工程については、実施例1と同様である。熱酸化膜形成前の基板102の厚さは400μmであった。基板にシード層を形成した後、電解めっき法を用いて図6に示す直流電流をシード層に供給し、導通部に金属材料を充填する。このときの電流は1.54A(電流密度1A/dm2)であった。その後の工程は実施例1と同様であった。
貫通孔に金属材料を充填する前までの工程については、2−2.貫通電極基板の製造方法2と同様である基板にシード層を形成した後、電解めっき法を用いて図6に示す直流電流をシード層に供給し、導通部に金属材料を充填する。このときの電流は1.54A(電流密度1A/dm2)であった。その後の工程は実施例1と同様であった。熱酸化膜形成前の基板102の厚さは70μmであった。
本実施形態2においては、実施形態1に係る本発明の貫通電極基板100上にLSIチップが積層された半導体装置の例及び実施形態1に係る本発明の貫通電極基板100を複数層積層した半導体装置の例について説明する。なお、実施形態1と同様の構成や製造方法については、ここでは改めて説明しない。
本実施形態3においては、上述の実施形態1及び2の貫通電極基板に搭載されるLSIチップとして、MEMSデバイスを用いる場合について説明する。本実施形態においては、MEMSデバイスは、物理量センサ302−1を例にとって説明する。
上記物理量センサ302−1により検出される加速度の変位信号を処理する各処理回路の構成例について図20を参照して説明する。
102:基板
104:貫通孔
106:導通部
106a:中央部
106b:直流電流領域
106c:直流−パルス切替領域
106d:パルス電流後期領域
106e:パルス電流初期領域
107:蓋めっき
108:絶縁膜
110:シード層
302:バンプ
304、306:LSI基板
306−1、306−2:チップ
308−1、308−2:電極パッド
Claims (2)
- ウェハ状の基板に表裏を貫通する複数の貫通孔を形成し、
前記基板及び前記貫通孔の表面に絶縁膜を形成し、
前記基板の少なくとも一方の面及び/又は前記貫通孔に金属からなるシード膜を形成し、
前記シード膜に第1の時間直流電流を供給する電解めっき法により、前記シード層が形成されている面の前記貫通孔の底部に金属層を形成し、
前記シード膜及び前記金属層に第2の時間、第1の電流密度でパルス電流を供給し、前記シード膜に第3の時間、前記第1の電流密度よりも大きな第2の電流密度でパルス電流を供給する電解めっき法により、前記貫通孔内に金属材料を充填することを特徴とする貫通電極基板の製造方法。 - 前記電解めっき法は、前記シード膜にプラス電圧とマイナス電圧を周期的に印加することによって行うことを特徴とする請求項1に記載の貫通電極基板の製造方法。
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CN201510085057.0A CN104681503B (zh) | 2008-10-16 | 2009-08-26 | 贯通电极基板和使用贯通电极基板的半导体装置 |
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US12/855,266 US8288772B2 (en) | 2008-10-16 | 2010-08-12 | Through hole electrode substrate with different area weighted average crystal grain diameter of metal in the conductive part and semiconductor device using the through hole electrode substrate |
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