CN104617037B - 贯通电极基板的制造方法 - Google Patents
贯通电极基板的制造方法 Download PDFInfo
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- CN104617037B CN104617037B CN201510085056.6A CN201510085056A CN104617037B CN 104617037 B CN104617037 B CN 104617037B CN 201510085056 A CN201510085056 A CN 201510085056A CN 104617037 B CN104617037 B CN 104617037B
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- electrode substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 181
- 238000000034 method Methods 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000007769 metal material Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 238000009713 electroplating Methods 0.000 claims description 27
- 239000012528 membrane Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 abstract description 53
- 230000000052 comparative effect Effects 0.000 description 26
- 238000007747 plating Methods 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 22
- 239000010949 copper Substances 0.000 description 18
- 230000001133 acceleration Effects 0.000 description 16
- 238000001887 electron backscatter diffraction Methods 0.000 description 16
- 238000011049 filling Methods 0.000 description 15
- 238000009826 distribution Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000005868 electrolysis reaction Methods 0.000 description 10
- 238000006073 displacement reaction Methods 0.000 description 8
- 238000000227 grinding Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000011651 chromium Substances 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 239000002245 particle Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 4
- 210000001367 artery Anatomy 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010948 rhodium Substances 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 210000003462 vein Anatomy 0.000 description 4
- 238000000708 deep reactive-ion etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000001376 precipitating effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- YLZOPXRUQYQQID-UHFFFAOYSA-N 3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]propan-1-one Chemical compound N1N=NC=2CN(CCC=21)CCC(=O)N1CCN(CC1)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F YLZOPXRUQYQQID-UHFFFAOYSA-N 0.000 description 1
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000006854 communication Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
本发明提供一种贯通电极基板的制造方法,在该贯通电极基板中,提高了将基板的表面和背面导通的导通部中的电特性。本发明的贯通电极基板(100)具备具有贯通表面和背面的贯通孔(104)的基板(102);和填充在贯通孔(104)内并含有金属材料的导通部(106),导通部(106)至少包含面积加权后的平均晶粒直径为13μm以上的金属材料。另外,导通部(106)包含晶粒直径为29μm以上的金属材料。此外,导通部的一端含有面积加权后的平均晶粒直径比13μm小的金属材料,导通部的另一端至少含有面积加权后的平均晶粒直径为13μm以上的金属材料。
Description
本案是申请日为2009年8月26日、申请号为200980130037.3、发明名称为“贯通电极基板及其制造方法和使用贯通电极基板的半导体装置”的专利申请的分案申请。
技术领域
本发明涉及贯通电极基板及其制造方法和使用着该贯通电极基板的半导体装置,该贯通电极基板具备贯通基板的表面和背面的贯通电极。在本说明书中,所谓半导体装置,是指利用半导体特性能够发挥功能的装置整体,半导体集成电路、电子设备也包含在半导体装置的范围内。
背景技术
近年来,随着电子设备的高密度、小型化的发展,LSI芯片也缩小到了与半导体封装同等的程度,仅仅依靠二维配置LSI芯片的高密度化正在达到其极限。因此,为了提高安装密度,需要将LSI芯片分开而将其按三维层叠。另外,为了使层叠有LSI芯片的半导体封装整体高速运转,需要使层叠电路彼此接近,缩短层叠电路间的配线距离。
因此,为了适应上述要求,对于LSI芯片间的中介层(interposer),提出了具备能够将基板的表面和背面导通的导通部的贯通电极基板(专利文献1)。根据专利文献1,贯通电极基板是通过利用电解电镀将导电材料(Cu)填充到设置在基板上的贯通孔的内部而形成的。
现有技术文献
专利文献
专利文献1:日本特开2006-54307号公报
专利文献2:日本特开2006-147971号公报
发明内容
发明要解决的课题
在将贯通电极基板用于多个LSI芯片间的连接或者LSI芯片与MEMS器件等之间的连接的情况下,在通过电解电镀而形成的导通部要求能够可靠地确保导通性,并且要求其电阻值低等的电特性的提高。
另一方面,在专利文献2等中,公开了在贯通电极的制造工序中,减少孔隙(空隙)的技术。但是,专利文献2中,虽然研究了确保导通部的导通性的途径,但是并没有研究导通部中的电特性。
本发明就是鉴于上述问题而提出的,其目的在于提供一种贯通电极基板及使用着该贯通电极基板的半导体装置,在该贯通电极基板中,提高了将基板的表面和背面导通的导通部中的电特性。
用于解决课题的手段
根据本发明的一种实施方式,提供一种贯通电极基板,其包括:具有贯通表面和背面的贯通孔的基板;和填充在所述贯通孔内并包含金属材料的导通部,所述导通部至少包含面积加权后的平均晶粒直径为13μm以上的金属材料。
优选,上述导通部至少包含晶粒直径为29μm以上的金属材料。
优选,上述导通部的一端包含面积加权后的平均晶粒直径比13μm小的金属材料,上述导通部的另一端至少包含面积加权后的平均晶粒直径在13μm以上的金属材料。
优选,上述基板由硅构成,上述导通部至少形成于设置在上述基板侧的绝缘层上。
优选,上述贯通孔的开口直径是10μm~100μm,并且上述基板的厚度是20~100μm。
优选,上述贯通孔的开口直径是10μm~100μm,并且上述基板的厚度是300~800μm。
也可以将上述贯通电极基板层叠多层。
还提供一种半导体装置,其至少包含一个具备连接端子部的半导体芯片,将上述连接端子部与上述贯通电极基板的导通部连接而构成。
另外,根据本发明的一个实施方式,还提供一种贯通电极基板的制造方法,其中,在基板上形成贯通表面和背面的贯通孔,在上述基板和上述贯通孔的表面形成绝缘膜,在上述基板的至少一个面及/或上述贯通孔形成金属构成的种子膜,通过对上述种子膜供给脉冲电压的电解电镀法,向上述贯通孔内填充金属材料。
优选,上述电解电镀法通过对上述种子膜周期性地施加正电压和负电压而进行。
优选,利用对上述种子膜供给第一时间直流电流的电解电镀法,在上述贯通孔形成金属材料之后,利用对上述种子膜供给第二时间脉冲电流的电解电镀法,在上述贯通孔内填充金属材料。
优选,对上述种子膜供给脉冲电流的上述电解电镀法包含在阶段性地增大上述脉冲电流的电流密度的同时在上述贯通孔内填充上述金属材料的工序。
根据本发明,能够提供一种贯通电极基板及使用着该贯通电极基板的半导体装置,在该贯通电极基板中,提高了将基板的表面和背面导通的导通部中的电特性。
附图说明
图1是第一实施方式涉及的本发明的贯通电极基板100的截面图。
图2是说明第一实施方式涉及的本发明的贯通电极基板100的制造工序的图。
图3是说明第一实施方式涉及的本发明的贯通电极基板100的制造工序的图。
图4是说明用于电解电镀的脉冲电压的图,该电解电镀用于向第一实施方式涉及的本发明的贯通电极基板100的贯通孔104填充金属材料。
图5是说明用于电解电镀的脉冲电压的图,该电解电镀用于向第一实施方式涉及的本发明的贯通电极基板100的贯通孔104填充金属材料。
图6是说明用于电解电镀的直流电压的图,该电解电镀用于向第一实施方式涉及的本发明的贯通电极基板100的贯通孔104填充金属材料。
图7是说明EBSD装置的结构的图。
图8是说明通过EBSD进行测定的试样测定的概念的图。
图9是表示测定了第一实施方式涉及的本发明的贯通电极基板100的导通部106的金属材料的晶粒直径的区域的图。
图10是实施例1涉及的本发明的贯通电极基板100的导通部106的金属材料的面积加权后的晶粒直径分布图。
图11是比较例1涉及的贯通电极基板的导通部的金属材料的面积加权后的晶粒直径分布图。
图12是比较例2涉及的贯通电极基板的导通部的金属材料的面积加权后的晶粒直径分布图。
图13是实施例1涉及的本发明的贯通电极基板100的导通部106的直流电流区域106b中的金属材料的面积加权后的晶粒直径分布图。
图14是实施例1涉及的本发明的贯通电极基板100的导通部106的直流-脉冲切换区域106c中的金属材料的面积加权后的晶粒直径分布图。
图15是实施例1涉及的本发明的贯通电极基板100的导通部106的电流初期区域106e中的金属材料的面积加权后的晶粒直径分布图。
图16是实施例1涉及的本发明的贯通电极基板100的导通部106的电流后期区域106d中的金属材料的面积加权后的晶粒直径分布图。
图17是表示基于电解电镀法的填充电镀的成长速度差异及膜厚的示意图。
图18是表示第一实施方式涉及的本发明的贯通电极基板100的导通部106的电镀的膜厚d的测定位置的示意图。
图19是用于说明在本发明涉及的贯通电极基板100上层叠有LSI芯片的半导体装置以及层叠有本发明涉及的贯通电极基板100的层叠型贯通电极基板300的截面图。
图20是表示加速度处理电路的一例的图,该加速度处理电路用于处理由物理量传感器检测出的加速度的位移信号。
图21是表示安装着传感器模块的便携式终端机的一例的图。
具体实施方式
下面,参照附图说明本发明涉及的贯通电极基板及其制造方法。然而,本发明的贯通电极基板能够通过多种不同的方式实现,并不能限定于以下所示的实施方式及实施例记载的内容进行解释。此外,在本实施方式和实施例所参照的附图中,对于同一部分或者具有相同功能的部分赋予相同的符号,省略其重复说明。
1.贯通电极基板的结构
图1是本实施方式涉及的本发明的贯通电极基板100的截面图。本实施方式中的本发明的贯通电极基板100具备贯通成为核心部的基板102的表面和背面的贯通孔104。在贯通孔104的内部形成有导通部106。基板102由硅等的半导体材料构成,利用后述的蚀刻、激光、喷砂等的方法形成有贯通孔104。基板102的厚度为例如10~800μm,但是并不限定于此。此外,在图1中,为了方便说明只表示了一个贯通孔104,但是也可以在基板102形成多个贯通孔104,在各个贯通孔104中形成导通部106。另外,优选按照用途适当地选择厚度在300~800μm或者20~100μm范围的基板。
在本实施方式中,在贯通孔104的内壁及基板102的表面设置有用于确保电绝缘性的绝缘膜108。绝缘膜108由例如SiO2构成,通过热氧化法、CVD法等形成。绝缘膜108的厚度是0.1~2μm左右,只要能够确保充分的绝缘性,则对其厚度没有特别的限定。
在本实施方式中,贯通孔104的开口直径是10~100μm左右。此外,贯通孔104的开口直径并不限定于此,可以根据贯通电极基板100的用途而适当地设定。
在本实施方式中,导通部106是将贯通电极基板100的表面和背面导通的配线,填充有包含金属材料的导电材料。本实施方式中,如后所述,导通部106通过电解电镀填充导电材料。作为用于导通部106的金属材料,例如能够使用铜。
在本实施方式涉及的本发明的贯通电极基板100中,如后所述,导通部106的金属材料包含面积加权后的平均晶粒直径为13μm以上的晶粒。另外,本实施方式涉及的本发明的贯通电极基板100中,如后所述,导通部106的金属材料包含最大晶粒直径为29μm以上的晶粒。本实施方式涉及的本发明的贯通电极基板100中,能够通过上述结构提高导通部106的电特性。
2.贯通电极基板100的制造方法
这里,参照图2及图3说明本实施方式涉及的本发明的贯通电极基板100的制造方法。
2-1.贯通电极基板100的制造方法1
(1)基板102的准备及贯通孔104的穿孔(图2(A))
本实施方式中,要准备由硅构成的基板102。虽然基板102的厚度没有特别限定,但是可以是300~800μm。在基板102的一个面侧形成选自抗蚀剂、硅氧化膜、硅氮化膜、金属等的掩模(未图示)后,隔着该掩模沿厚度方向对基板102进行蚀刻,形成贯通孔104。作为蚀刻方法,能够使用RIE法、DRIE法等。此外,既可以只通过蚀刻形成贯通基板102的表面和背面的贯通孔104,也可以在基板102上形成有底孔后,利用背面研磨(back grinding)技术进行研磨使之开口,从而形成贯通孔104。也可以通过研磨将基板102的厚度形成在300μm以下。
(2)绝缘膜108的形成(图2(B))
在基板102的表面形成绝缘膜108。在本实施方式中,绝缘膜108是氧化硅膜,通过热氧化法或者CVD法形成。对于绝缘膜108,除了氧化硅膜之外,也可以使用氮化硅膜、氮化氧化硅膜、这些膜的层积膜等。
(3)种子层的形成(图2(C))
在基板102的至少一个面形成有种子层110。种子层110通过在基板102侧形成Ti层、并在其上形成Cu层(下面称为Cu/Ti层)构成,或者由Cu层/TiN层或Cu/Cr层等构成。本实施方式中,在种子层110使用Cu/Cr层。种子层110的成膜方法能够从PVD、溅射法等进行适当选择。用于种子层110的金属材料能够根据导通部106的金属材料进行适当选择。种子层110成为用于利用电解电镀形成导通部106的种子部和供电部。
(4)导通部106的形成(图2(D))
使用电解电镀法对种子层110供电,向贯通孔104内填充金属材料。本实施方式中,使用铜(Cu)作为填充到贯通孔104中的金属材料。本实施方式中,如图4和图5所示,通过向种子层110呈脉冲状地供给电流的电解电镀法,向贯通孔104内填充金属材料。图4所示的脉冲电流的供给方法是向种子层110供给不反转极性的脉冲电流的方法。另外,图5所示的脉冲电流的供给方法是向种子层110施加周期性地反转极性的脉冲电流的方法。基于图5所示的脉冲电流的供给的电镀方法称为PRC(Periodical Reversed Current)法,是通过向种子层110周期性地施加正电压和负电压,从而按照一定的周期将流到种子层110的电流切换为正向(Forward)(电镀侧,即种子层110侧成为负电位的状态(流正电流的状态))和反向(电镀侧,即种子层110侧成为正电位的状态(流负电流的状态))而进行电镀的方法之一,是优选的电镀方法之一。另外,在本实施方式的基于脉冲电流的电解电镀中,能够适当选择施加电压、供给电流、电流密度、脉冲切换时间(占空比)。另外,也可以在电解电镀的中途改变施加电压、电流密度、脉冲切换时间(占空比)。通过供给脉冲电流而在种子层110流动的电流可以为:在施加正电压时,流过0.5A以上1.5A以下的电流;在施加负电压时,流过-6A以上-2A以下的电流。
此外,在供给脉冲电流前,如图6所示,也可以通过向种子层110供给一定的直流电流的电解电镀法,在形成有种子层110的面的贯通孔104的底部形成盖状的金属层。作为在贯通孔104中填充的金属材料,除了Cu外,还能够使用从金(Au)、铑(Rh)、银(Ag)、铂(Pt)、锡(Sn)、铝(Al)、镍(Ni)、铬(Cr)等的金属和这些金属的合金等选择而加以组合的材料。
在供给直流电流形成了盖状的金属层的情况下,优选在切换为脉冲电流的初始阶段,在一定时间内减小电流密度,逐渐(例如,按照经过的时间呈阶段性或者呈比例地)增大电流密度的方法。若供给直流电流形成盖状的金属层,则在连接贯通孔104的部分,金属层的成长存在变快的倾向。因此,盖状的金属层成为向着中心部凹陷的形状。能够想到通过在切换为脉冲电流的初始阶段,供给一定时间的小电流密度的脉冲电流,能够进行金属层的成长从而将该凹部平坦化。通过使用这样的电解电镀法,能够得到电特性优异的贯通电极,并且提高贯通电极基板的制造性。
(5)除去不需要的部分(图2(E))
利用蚀刻或者CMP(Chemical Mechanical Polishing:化学机械研磨)除去种子层110及导通部106的不需要的部分,形成导通部106。通过以上的处理,能够得到本实施方式涉及的本发明的贯通电极基板100。
(2-2.贯通电极基板的制造方法2)
这里,说明本实施方式涉及的本发明的贯通电极基板100的制造方法的其他例子。对于与上述的贯通电极基板100的制造方法1相同的结构不再进行重复说明。此外,这里说明的本实施方式涉及的本发明的贯通电极基板100的制造方法2,通常用于希望得到贯通孔的深度比较浅(例如,20μm~100μm左右)或厚度在20μm~100μm左右的薄的贯通电极基板的情况下。
(1)基板102的准备和孔的形成(图3(A))
在基板102的一个面侧形成选自抗蚀剂、硅氧化膜、硅氮化膜、金属等的掩模(未图示)后,隔着该掩模沿厚度方向对基板102进行蚀刻,形成不贯通基板102的有底孔112。作为蚀刻方法,能够使用RIE法、DRIE法等。
(2)绝缘膜108的形成(图3(B))
在基板102的表面形成绝缘膜108。
(3)种子层的形成(图3(C))
在形成有绝缘膜108的基板102的面形成种子层114。该种子层114如图3(C)所示,也形成在孔112的内部。种子层114与上述种子层110同样,由Cu层/Ti层等构成。种子层114与种子层110同样,通过电解电镀成为用于形成导通部106的种子部和供电部。种子层114通过MOCVD法、溅射法或者蒸镀法等形成。
(4)导通部106的形成(图3(D))
使用电解电镀法给种子层114供电,在孔112内填充金属材料。在本实施方式的贯通电极基板的制造方法2中,也与贯通电极基板的制造方法1相同,如图4和图5所示,通过向种子层110呈脉冲状供给电流的电解电镀法,在贯通孔112内填充金属材料。此外,在供给脉冲电流前,如图6所示,也可以给种子层110供给一定的直流电流。在本实施方式中,作为填充到孔112中的金属材料,使用了铜(Cu)。作为在贯通孔104中填充的金属材料,除了铜外,还能够使用从金(Au)、铑(Rh)、银(Ag)、铂(Pt)、锡(Sn)、铝(Al)、镍(Ni)、铬(Cr)等的金属和这些金属的合金等选择而加以组合的材料。
(5)除去不需要的部分(图3(E))
利用蚀刻或者CMP法除去种子层114及导通部106的不需要的部分。另外利用背面研磨技术对与形成有孔112的侧相反侧的基板102的面进行研磨直至露出导通部106的表面,形成导通部106。也可以利用研磨将基板102的厚度变薄。通过以上的处理,能够得到本实施方式涉及的本发明的贯通电极基板100。
(实施例1)
下面,说明本发明的贯通电极基板100的实施例。将厚度650μm的基板102洗净后,在基板102的一个面侧涂覆抗蚀剂,进行曝光、显影,由此形成掩模(未图示)。之后,利用DRIE法,隔着该掩模沿厚度方向对基板102进行蚀刻,形成430μm的有底孔112(图2(A))。在除去抗蚀剂构成的掩模后,利用背面研磨技术研磨基板102直至400μm的厚度。
将基板102洗净后,通过热氧化法在基板102的表面形成厚度1μm的热氧化膜。之后,利用LPCVD法形成厚度200nm的氮化硅膜。这些热氧化膜和氮化硅膜构成绝缘膜108(图2(B))。
通过在基板102的一个面依次蒸镀厚度30nm的Cr和厚度200nm的Cu,由此形成种子层110(图2(C))。
之后,对基板102进行灰化。接着,使用基于图6所示的直流电流的供给的电解电镀法,对种子层110供电,在形成有种子层110的面的贯通孔104的底部形成盖状的金属层。在本实施例1中,供给电流1.54A、电流密度1A/dm2的直流电流后,使用基于图5所示的脉冲电压的施加的电解电镀法,对种子层110供电,在贯通孔104内填充Cu(图2(D))。脉冲切换时间按照供给80msec的正电流、供给2msec的负电流的方式设定。在供给正电流时,流动1.05A的电流(电流密度3A/dm2),在供给负电流时,流动-4.2A的电流(电流密度-12A/dm2)。
此外,使用基于图5所示的脉冲电流的施加的电解电镀法开始填充Cu时,在最初的一小时左右供给小电流,并且使在供给正电流时,流过0.35A的电流(电流密度1A/dm2),在供给负电流时,流过-1.4A的电流(电流密度-4A/dm2)。通过使用这样的电解电镀法,在得到电特性优异的贯通电极的同时,也提高了贯通电极基板的制造性。
洗净基板102后,利用CMP除去种子层110及导通部106的不需要的部分,形成导通部106。利用以上的处理,能够得到本实施例涉及的本发明的贯通电极基板100。
(3.基于电子背散射衍射法(Electron backscatter diffraction Pattern:EBSD)的结晶状态分析)
这里,参照图7及图8,说明本实施方式涉及的导通部106的金属材料的晶粒直径分析中使用的电子背散射衍射法(Electron backscatter diffraction Pattern:EBSD)。
(3-1.EBSD的说明)
(晶粒直径的测定)
通过EBSD法进行构成本实施方式涉及的本发明的贯通电极基板100的导通部106的金属材料的晶粒直径的测定。图7是说明EBSD装置的结构的图。另外,图8是说明通过EBSD装置进行的试样测定的概念的图。在测定本实施方式涉及的导通部106的晶粒直径时,调节为将电子线212照射到贯通部106的截面部。
EBSD装置200在扫描型电子显微镜(SEM:Scanning Electron Microscopy)202设置专用检测器204,是由一维电子的背散射电子分析结晶方位的方法。具体而言,如果使得从电子枪210射出的电子线212通过镜体214入射到载置在试样室205内的试样台206上的具有结晶结构的试样208(照射),则在试样208引起非弹性散射,产生背散射电子216。其中,也能同时观察到试样208中基于布拉格衍射的结晶方位所特有的线状图案(一般称为菊池线图案)。该背散射电子216通过屏幕218,由SEM202的检测器204对其进行检测。于是,通过分析检测到的菊池线图案,能够求得试样208的晶粒直径。
在各晶粒直径不同的结晶构造的情况下,通过在移动照射到试样208的电子线的位置的同时反复测定晶粒直径(映像(maping)测定),能够得到面状的试样208中的晶粒直径的信息。晶粒的面积(A)通过在晶粒的数量(N)上乘以由测定的步长(s)决定的测定点的面积而算出。在EBSD测定中,将测定点表示为六角形,由此,晶粒的面积(A)由下式(1)表示。
将晶粒直径(D)作为具有与晶粒的面积(A)相等面积的圆的直径进行计数。晶粒直径(D)由下式(2)表示。
D=(4A/π)1/2(其中,π是圆周率)···(2)
本说明书中定义的“晶粒直径”是指按照上述方法测定的值。另外,在晶粒直径的测定中,包含边缘晶粒(Edge Grain)。
下面,说明对基于实施例1的构成本发明的贯通电极基板100的导通部106的金属材料、以及基于比较例1和2(后面详细叙述处理过程)的构成贯通电极基板的导通部的金属材料进行EBSD测定的结果。这里,利用氩离子对构成各导通部的金属材料的截面进行加工,即,通过离子抛光法制成测定试样。另外,EBCD测定中的测定点分别是图9所示导通部的深度方向中央部106a附近。
图10是构成实施例1中的本发明的贯通电极基板100的导通部106的金属材料的结晶的面积加权后的晶粒直径分布图。根据以晶粒直径(D)为横轴,以面积率(Rs)为纵轴的柱状图,能够算出构成导通部106的晶粒直径的最大值和平均值。
这里,面积率(Rs)(含该晶粒直径的比例(面积加权)),能够使用测定区域的面积(Sm)用下式(3)表示。
Rs=A×(N/Sm)···(3)
图10所示的柱状图的横轴表示晶粒直径的值(D),纵轴(area fraction)表示对包含该值的晶粒的比例进行面积加权。例如,图10的纵轴的0.15表示比例15%。从而,对各晶粒直径(D)乘以其比例(Rs),将其值累计则如下式(4)所示得到面积加权后的平均晶粒直径(Ds)。
Ds=Σ{Rs×D}···(4)
本实施例中,测定晶粒直径时,为了使测定区域有限(本实施例中,为50μm×150μm的区域),从所希望的区域切出上述面积区域进行观测。本说明书中,以包含测定区域的边缘(Edge)处的晶粒(Grain)的值为晶粒直径。另外,由于分析结果含有误差,所以使用不考虑小数点以下而将其丢弃后的值。
测定条件如下所述:
使用的分析装置
SEM日本电子制JSM-7000FEBSD TSL公司制OIM软件Ver.4.6
观察条件
EBSD测定
加速电压25kV
试样倾斜角70°
测定步距0.3μm
实施例1中的本发明的贯通电极基板100的导通部106的金属材料的最大粒径是29μm,平均粒径(面积加权)是13μm。评价导通部106的电特性的结果是,确认了实施例1中的本发明的贯通电极基板100的导通部106的电阻值是3.15×10-4Ω,导通部106具有优异的电特性,有优势。
另一方面,图11中表示比较例1(在比较例1中,到对贯通孔填充金属材料前的工序与实施例1相同,所以实施例1中的贯通部106的直径及长度(即,基板的厚度)与比较例1中的贯通部的直径及长度(即,基板的厚度)相同。)中的构成贯通电极基板的导通部的金属材料的结晶的面积加权后的晶粒直径分布图。比较例1中的构成贯通电极基板的导通部的金属材料的最大粒径是10μm,平均粒径(面积加权)是2μm。比较例1中的贯通电极基板的导通部106的电阻值是7.25×10-3Ω,可知导通部的电特性与实施例1相比较差。
因此,实施例1中的本发明的贯通电极基板100的导通部106的电阻与比较例1的导通部的电阻相比,缩小到1/23。
另外,图12表示比较例2中的构成贯通电极基板的导通部的金属材料的结晶的面积加权后的晶粒直径分布图。比较例2中的构成贯通电极基板的导通部的金属材料的最大粒径是11μm,平均粒径(面积加权)是2μm。为了测定比较例2中的贯通电极基板的导通部的电阻值,如图3所示,除去种子层114及导通部106的不需要的部分,将基板102的与形成有孔112的侧相反侧的面研磨至露出导通部106的表面。比较例2中的贯通电极基板的导通部106的电阻值是1.08×10-3Ω,可知导通部的电特性与实施例1相比较差。
这里,综合实施例1、比较例1及比较例2中的最大粒径及平均粒径,则能够得出如下所示图表。
表1
平均粒径(面积加权)[μm] | 最大粒径[μm] | |
实施例1 | 13 | 29 |
比较例1 | 2 | 10 |
比较例2 | 2 | 11 |
根据上述结果,可知当贯通电极基板100的导通部106的平均粒径(面积加权)为13μm以上时,电阻值小,导通部106具有优异的电特性。这是因为当贯通电极基板100的导通部106的金属粒径大时,电阻变小。另外,当贯通电极基板100的导通部106的最大粒径为29μm以上时,电阻值小,导通部106具有优异的电特性。
这里,实施例1中,在通过供给直流电流而形成有盖状的金属层的导通部106的金属填充开始侧,和通过供给脉冲电流而填充有金属材料的金属填充结束侧,测定晶粒直径,并进行比较。
图9是表示测定了填充在导通部106中的金属材料的晶粒直径的区域的图。测定区域从电镀开始侧开始,依次为直流电流区域106b,直流-脉冲切换区域106c和脉冲电流后期区域106d。在直流电流区域106b中,与基板102连接的部分的填充速度有变快的倾向,在从直流电流向脉冲电流切换的分界处,为导通部106的中心部存在凹陷的金属材料的结晶的填充状态。
如图13所示,在导通部106的直流电流区域106b中,面积加权后的平均粒径为1.92μm。如图14所示,在直流-脉冲切换区域106c中,面积加权后的平均粒径为4.82μm。但是,在直流-脉冲切换区域106c的脉冲电流初期区域106e中,如图15所示,面积加权后的平均粒径为5.84μm,可知与直流电流区域相比,平均粒径显著变大。进而,如图16所示,在脉冲电流后期区域106d中,面积加权后的平均粒径为23.58μm,也会产生具有50μm以上的粒径的结晶。
下面,说明上述比较例1及比较例2。
(比较例1)
向贯通孔填充金属材料之前的工序与实施例1相同。热氧化膜形成前的基板102的厚度为400μm。在基板上形成种子层后,使用电解电镀法,向种子层供给图6所示的直流电流,对导通部填充金属材料。这时的电流是1.54A(电流密度1A/dm2)。之后的工序与实施例1相同。
(比较例2)
向贯通孔填充金属材料之前的工序与2-2.贯通电极基板的制造方法2相同,在基板上形成种子层后,使用电解电镀法,向种子层供给图6所示的直流电流,对导通部填充金属材料。这时的电流是1.54A(电流密度1A/dm2)。之后的工序与实施例1相同。热氧化膜形成前的基板102的厚度是70μm。
实施例1及比较例1均使用电解电镀法,如图17所示,填充电镀的成长速度在各贯通电极基板的导通部有所不同。如图17(a)所示,电解电镀法中,在贯通孔104的种子层110侧,形成基于金属材料的电镀盖107,接着,如图17(b)所示,填充金属材料。这里,所谓“电镀盖”是指在电解电镀的初始阶段,在种子层表面析出金属材料,在电解密度高的贯通孔的开口部集中析出金属材料,由此形成的闭塞贯通孔的开口部的金属层。通过电解电镀法,金属层从电镀盖107向贯通孔104的上方成长。这时,金属层的成长速度在各贯通孔104有所不同。
在测定绝缘膜108与填充在贯通孔104中的镀层的台阶差的同时进行基于电解电镀法的金属材料的填充,图17(c)所示的成长最慢的贯通孔104中的金属层的上表面与基板102的绝缘膜108的表面的台阶差消失的时刻结束该基于电解电镀法的金属材料的填充。对于所有的贯通孔104中都填充了金属层的贯通电极基板,针对数个导通部测定如图17(d)所示成长到从贯通电极基板露出的金属层的膜厚d,并进行比较。
实施例1及比较例1中,对于图18所示的9个测定点(A~I)的导通部测定膜厚d。实施例1中对三枚基板进行测定,比较例1中,使用4枚基板进行测定。表2表示其测定结果。
表2
令膜厚的平均为ave,膜厚的最大值为Max,最小值为Min,则膜厚的偏差用{(Max-Min)/ave/2×100}表示。如表2所示,实施例1中,观察各基板间的偏差,膜厚的偏差在10%左右,较小,相对于此,比较例1中,存在膜厚的偏差在50%以上、接近70%的具有大的偏差的基板。即,实施例1的供给脉冲电流导致的金属层的成长与比较例1的供给直流电流导致的金属层的成长相比,具有能够实现偏差少的均匀成长的优异效果。
(实施方式2)
本实施方式2中,对在实施方式1中涉及的本发明的贯通电极基板100上层叠有LSI芯片的半导体装置的例子及将实施方式1涉及的本发明的贯通电极基板100层叠多层而成的半导体装置的例子进行说明。此外,对于与实施方式1相同的结构和制造方法不进行重复说明。
参照图19(A)和(B)。图19(A)中,表示本实施方式涉及的半导体装置,其层叠有三个实施方式1的本发明的贯通电极基板100。在贯通电极基板100形成有DRAM等的半导体元件。三个贯通电极基板100层叠,经由突起(bump)302相互连接。贯通电极基板100起到将分别形成的DRAM电连接的互联板(インターボーザ)的作用。层叠为三层的贯通电极基板100经由突起302与LSI基板304连接。此外,层叠的贯通电极基板100的数量并不限定于三层。在突起304处能够使用In(铟)、Cu、Au等的金属。另外,贯通电极基板100之间的接合也可以主要使用聚酰亚胺、BCB(Benzocyclobutene:苯并环丁烯)等的树脂,通过涂覆、烧结进行粘接。另外,贯通电极基板100之间的接合也可以使用环氧树脂。再者,贯通电极基板100之间的接合也可以使用基于等离子体活化的接合、共晶接合等。
如本实施方式所示,在层叠有本发明的贯通电极基板100的情况下,若令本发明的贯通电极基板100的导通部106(贯通孔)的电阻为Ri,层叠连接的本发明的贯通电极基板100的层叠数为N,则串联连接的导通部106(贯通孔)整体的电阻为N×Ri,能够缩小导通部106(贯通孔)的电阻。
图19(B)中表示的半导体装置的例子中,其具有搭载有MEMS器件或CPU、存储器等的LSI芯片(半导体芯片)306-1及306-2的贯通电极基板100。LSI芯片306-1及306-2的连接端子即电极垫308-1及308-2分别经由突起304与贯通电极基板100的导通部106电连接。搭载有LSI芯片306-1及306-2的贯通电极基板100被搭载于LSI基板306,通过线焊将LSI基板306与LSI芯片306-1连接。例如,通过令LSI芯片306-1为三轴加速度传感器,LSI芯片306-2为两轴磁性传感器,能够通过一个模块实现五轴运动传感器。这样,实施方式1中的本发明的贯通电极基板100能够用作将多个LSI芯片之间进行三维安装的互联板(交互板)。
另外,如上所述,实施方式1涉及的本发明的贯通电极基板100中,导通部106的电阻值小,电特性提高,结果,能够减小将贯通电极基板100用于半导体装置时的在导通部106产生的热量。由此,能够实现高密度地安装有贯通电极基板100的半导体装置。
(实施方式3)
本实施方式3中,对于使用MEMS器件作为搭载在上述实施方式1及2的贯通电极基板的LSI芯片的情况进行说明。本实施方式中,用物理量传感器302-1作为MEMS器件的例子加以说明。
下面,说明对利用物理量传感器302-1检测出的加速度的位移信号进行处理的处理电路。
<处理电路>
参照图20说明对利用上述物理量传感器302-1检测出的加速度的位移信号进行处理的各处理电路的构成例。
图20是表示对利用物理量传感器302-1检测出的加速度的位移信号进行处理的加速度处理电路400的电路结构的图。这时,物理量传感器是压电电阻型加速度传感器。图20中,加速度处理电路400由放大电路401、采样保持电路(S/H)402~404、输出电阻Rout、电容器Cx、Cy、Cz构成。其中,图中的X轴输出、Y轴输出、Z轴输出是与所施加的加速度相应而从物理量传感器302-1输出的X轴方向、Y轴方向、Z轴方向的各位移信号。此外,输出电阻Rout与电容器Cx、Cy、Cz起到使与加速度信号对应的频率成分通过的低通滤波器的作用。
放大电路401,按照规定的放大率,将与所施加的加速度相应而从物理量传感器302-1输出的X轴方向、Y轴方向、Z轴方向的各位移信号(静电容量变化)放大,分别输出到采样保持电路402~404。采样保持电路402在规定的定时对被放大电路401放大的X轴方向位移信号进行采样/保持,经由输出电路Rout及电容器Cx,输出X方向的加速度检测信号Xout。采样保持电路403在规定的定时对被放大电路401放大的Y轴方向位移信号进行采样/保持,经由输出电路Rout及电容器Cy,输出Y方向的加速度检测信号Yout。采样保持电路404在规定的定时对被放大电路401放大的Z轴方向位移信号进行采样/保持,经由输出电路Rout及电容器Cz,输出Z方向的加速度检测信号Zout。
安装有该物理量传感器302-1和处理电路400等的本发明的贯通电极基板100或者本发明的层叠型贯通电极基板300,搭载在便携式信息终端或者便携式电话等上作为传感器模块。图21表示安装有本发明的贯通电极基板100或者本发明的层叠型贯通电极基板300的半导体装置的一个例子,即便携式信息终端500的一个例子,上述贯通电极基板100或者层叠型贯通电极基板300上安装有物理量传感器302-1和处理电路400等。图21中,便携式信息终端500由框体501、显示部502、键盘部503构成。传感器模块安装在键盘部502的内部。便携式信息终端500的内部存储有各种程序,具有利用各种程序执行通信处理或信息处理等的功能。该便携式信息终端500中,通过应用程序利用由安装有物理量传感器302-1和处理电路400等的传感器模块检测的加速度或角速度,由此,例如能够附加检测下落时的加速度并关闭电源等的功能。
如上所述,通过在便携终端机装配安装有物理量传感器302-1和处理电路400等的传感器模块,能够实现新的功能,能够提高便携终端机的便利性和可靠性。
符号说明
100:贯通电极基板
102:基板
104:贯通孔
106:导通部
106a:中央部
106b:直流电流区域
106c:直流-脉冲切换区域
106d:脉冲电流后期区域
106e:脉冲电流初期区域
107:电镀盖
108:绝缘膜
110:种子层
302:突起
304、306:LSI基板
306-1、306-2:芯片
308-1、308-2:电极垫
Claims (2)
1.一种贯通电极基板的制造方法,其特征在于:
在晶片状的基板中形成多个贯通表面和背面的贯通孔,
在所述基板和所述贯通孔的表面形成绝缘膜,
在所述基板的至少一方的面形成由金属构成的种子膜,
利用对所述种子膜供给第一时间直流电流的电解电镀法,在形成有所述种子膜的面的所述贯通孔的底部形成盖状的金属层,
通过对所述种子膜和所述金属层以第二时间、第一电流密度供给脉冲电流,对所述种子膜以第三时间、且比所述第一电流密度大的第二电流密度供给脉冲电流的电解电镀法,向所述贯通孔内填充金属材料。
2.根据权利要求1所述的贯通电极基板的制造方法,其特征在于:
所述电解电镀法通过对所述种子膜周期性地施加正电压和负电压来进行。
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US20110062594A1 (en) | 2011-03-17 |
US8288772B2 (en) | 2012-10-16 |
CN104681503A (zh) | 2015-06-03 |
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CN102150246B (zh) | 2015-03-25 |
US20120329276A1 (en) | 2012-12-27 |
JP5246103B2 (ja) | 2013-07-24 |
CN102150246A (zh) | 2011-08-10 |
JP2010118645A (ja) | 2010-05-27 |
CN104681503B (zh) | 2017-10-03 |
CN104617037A (zh) | 2015-05-13 |
US8637397B2 (en) | 2014-01-28 |
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