JP2018064125A - 半導体集積回路装置 - Google Patents
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Abstract
Description
図1は第1の実施形態に係る半導体集積回路装置が備えたスタンダードセルのレイアウト構成例を示す平面図である。また図2は図1のスタンダードセルの回路図である。図2に示すとおり、図1のスタンダードセル1は2入力のNOR回路を実現するセルである。図1および他の平面図では、フィンとその上に形成されたゲートとによって、フィン型トランジスタが構成されている。ローカル配線は、平面視でフィンまたはゲートと重なる部分において、フィンまたはゲートの上層に接して形成されており、電気的に接続されている。メタル配線はローカル配線の上層に位置しており、コンタクトを介してローカル配線と接続されている。なお、図1では図の見やすさのために、フィンにハッチを付している。ただし、ゲートの下に位置する部分についてはハッチを省いている。また、ローカル配線およびメタル配線にも種類が異なるハッチを付しており、メタル配線とローカル配線とがコンタクトで接続された部分を黒く塗りつぶして示している。他の平面図においても同様である。
図4は第2の実施形態に係る半導体集積回路装置が備えたスタンダードセルのレイアウト構成例を示す平面図である。図4のスタンダードセル2は、図2に示す2入力のNOR回路を実現するセルであるが、図2の各トランジスタがそれぞれ2枚のフィンで構成されている。
図8は実施形態におけるスタンダードセルの他のレイアウト構成例を示す平面図、図9は図8のスタンダードセルの回路図である。ただし図8では、図9の各トランジスタがそれぞれ2枚のフィンで構成されている。図8のレイアウト構成では、フィン41,42の終端部にダミートランジスタが形成されている。図面左側における領域DN4では、フィン41,42とダミーゲート配線43,44とによって、ダミートランジスタが構成されている。図面右側における領域DN5では、フィン41,42とダミーゲート配線45,46とによって、ダミートランジスタが形成されている。
8a 接地配線(電源配線)
11 フィン
12,13 ゲート配線
14,15 ダミーゲート配線
16,22 フィン
21 フィン(第2フィン)
31,32,37,38 フィン
33,34,35,36,39,40 ダミーゲート配線
41,42 フィン
43,44,45,46 ダミーゲート配線
51,52 フィン
53,54,55,56 ダミーゲート配線
N1,N2,N1a,N2a アクティブトランジスタ
D1,D2,D1a,D2a ダミートランジスタ
Claims (11)
- 第1方向に延びるフィンを有するスタンダードセルを備え、
前記スタンダードセルは、
前記フィンと、前記第1方向と垂直をなす第2方向に延びており、前記フィン上に設けられたゲート配線とによって構成されたアクティブトランジスタと、
前記フィンと、前記ゲート配線と並列に、前記フィン上に設けられたダミーゲート配線とによって構成され、前記アクティブトランジスタとソースまたはドレインの一方のノードを共有しているダミートランジスタとを備えている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記スタンダードセルは、
前記フィンと、前記ゲート配線と並列にかつ前記ダミーゲート配線と反対側に、前記フィン上に設けられた第2ゲート配線とによって構成され、前記アクティブトランジスタとソースまたはドレインの他方のノードを共有している第3トランジスタを備えている
ことを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第3トランジスタは、アクティブトランジスタである
ことを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第3トランジスタは、ダミートランジスタである
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記アクティブトランジスタが前記ダミートランジスタと共有しているノードは、電源電位が供給されるソースである
ことを特徴とする半導体集積回路装置。 - 請求項5記載の半導体集積回路装置において、
前記ダミートランジスタは、ソース、ドレインおよびゲートがいずれも電源配線に接続されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記アクティブトランジスタが前記ダミートランジスタと共有しているノードは、ドレインであり、前記ダミートランジスタは、ソースおよびゲートが電源配線に接続されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記スタンダードセルは、
前記フィンが形成された第1導電型領域において、前記フィンと並列に配置された第2フィンを有し、
前記ゲート配線および前記ダミーゲート配線は、前記第2フィン上まで延びており、
前記第2フィンと前記ゲート配線とによって構成された第2アクティブトランジスタと、
前記第2フィンと前記ダミーゲート配線とによって構成され、前記第2アクティブトランジスタとソースまたはドレインの一方のノードを共有している第2ダミートランジスタとを備えている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記スタンダードセルは、
前記フィンが形成された第1導電型領域において、全てのアクティブトランジスタは、ソースおよびドレインの両方のノードを他のトランジスタと共有している
ことを特徴とする半導体集積回路装置。 - 請求項9記載の半導体集積回路装置において、
前記スタンダードセルにおいて、全てのアクティブトランジスタは、ソースおよびドレインの両方のノードを他のトランジスタと共有している
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記スタンダードセルは、クロックツリーを構成するセルである
ことを特徴とする半導体集積回路装置。
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CN108630607B (zh) * | 2013-08-23 | 2022-04-26 | 株式会社索思未来 | 半导体集成电路装置 |
WO2015033490A1 (ja) * | 2013-09-04 | 2015-03-12 | パナソニック株式会社 | 半導体装置 |
JP6396834B2 (ja) | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20160284836A1 (en) * | 2015-03-25 | 2016-09-29 | Qualcomm Incorporated | System, apparatus, and method for n/p tuning in a fin-fet |
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CN109314080B (zh) * | 2016-07-01 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
CN107623509B (zh) * | 2016-07-14 | 2023-06-20 | 三星电子株式会社 | 包括三态反相器的触发器 |
JP6970348B2 (ja) * | 2016-08-01 | 2021-11-24 | 株式会社ソシオネクスト | 半導体チップ |
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JP6970357B2 (ja) * | 2017-08-31 | 2021-11-24 | 株式会社ソシオネクスト | 半導体集積回路装置 |
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CN111466020A (zh) * | 2017-12-12 | 2020-07-28 | 株式会社索思未来 | 半导体集成电路装置 |
TWI756405B (zh) * | 2018-04-13 | 2022-03-01 | 聯華電子股份有限公司 | 靜態隨機存取記憶體的信噪比的調整方式以及反相器的結構 |
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JP7364922B2 (ja) * | 2018-12-26 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
JP7364928B2 (ja) * | 2019-02-18 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US11094695B2 (en) * | 2019-05-17 | 2021-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit device and method of forming the same |
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US10833075B2 (en) | 2020-11-10 |
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US11362088B2 (en) | 2022-06-14 |
US20210013201A1 (en) | 2021-01-14 |
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US20180130799A1 (en) | 2018-05-10 |
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US11764217B2 (en) | 2023-09-19 |
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US9899381B2 (en) | 2018-02-20 |
US20220278096A1 (en) | 2022-09-01 |
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US20230387116A1 (en) | 2023-11-30 |
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