JP6428956B2 - 半導体集積回路装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 description 13
- 238000002955 isolation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 101100008044 Caenorhabditis elegans cut-1 gene Proteins 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 101100008046 Caenorhabditis elegans cut-2 gene Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
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- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Description
図1は第1の実施形態に係る半導体集積回路装置が備えたスタンダードセルのレイアウト構成例を示す平面図である。また、図2は図1の構成の線K1−K1における断面図であり、図3は図1の構成の線K2−K2における断面図である。なお、本実施形態では説明を簡単にするために、インバータセルを例として示しているが、これに限られるものではない。
図6は第2の実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。なお、本実施形態では説明を簡単にするために、インバータセルを例として示しているが、これに限られるものではない。また、隣接するスタンダードセル2A,2Bは互いに異なる種類のセルであってもかまわない。
図10は第3の実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。図10では、図面横方向(第1方向に相当)に並べて配置されたスタンダードセル3A,3B,3C,3Dを含む第1セル列CR1と、図面横方向に並べて配置されたスタンダードセル3E,3F,3G,3Hを含み、図面縦方向(第1方向と垂直をなす第2方向に相当)において第1セル列CR1に隣接して配置された第2セル列CR2とを示している。なお、図10では説明の簡単のために、セル枠と、第1および第2セル列CR1,CR2の間のセル列境界CRBに沿って並んだフィン以外は、図示を省略している。第1セル列CR1では、セル列境界CRBに沿って、図面横方向に延びるフィン31,32,33a,33b,34が同一直線上に並んでいる。第2セル列CR2では、セル列境界CRBに沿って、図面横方向に延びるフィン35a,35b,36,37,38a,38bが同一直線上に並んでいる。
2A,2B スタンダードセル
3A,3B,3C,3D,3E,3F,3G,3H スタンダードセル
5f ローカル配線
6f コンタクト
8c メタル配線
11,12 アクティブフィン
13,14 ダミーフィン
15,15A ゲート配線
16,17 ダミーフィンに設けられたゲート配線
21,22,23,24 アクティブフィン
25 ダミーフィン
26,27 ゲート配線
28 ダミーフィンに設けられたゲート配線
29 拡散層配線
31,33a アクティブフィン
32,33b ダミーフィン
CB セル境界
CR1 第1セル列
CR2 第2セル列
CRB セル列境界
Claims (10)
- 第1方向に並べて配置されたスタンダードセルからなる第1セル列と、
前記第1方向に並べて配置されたスタンダードセルからなり、前記第1方向と垂直をなす第2方向において前記第1セル列に隣接して配置された第2セル列とを備え、
前記第1セル列は、
フィン型アクティブトランジスタを備え、前記第1セル列と前記第2セル列との間のセル列境界に最も近い位置に配置された前記第1方向に延びる第1アクティブフィンを備えた第1スタンダードセルと、
前記第1スタンダードセルと前記第1方向において隣接して配置され、前記第1方向に延びる第1ダミーフィンおよび電源が供給される拡散領域を備えたTAPセルとを備え、
前記第1ダミーフィンは前記第1アクティブフィンと前記第2方向における同一位置に配置され、前記拡散領域は前記セル列境界から前記第1アクティブフィンより遠い位置に配置されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1セル列は、
前記第1アクティブフィンと前記第2方向における同一位置に配置された第2アクティブフィンを備えた第2スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第2スタンダードセルは前記第1アクティブフィンと前記第2方向における同一位置に配置された第2ダミーフィンを備えた
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1セル列は、
前記第1アクティブフィンと前記第2方向における同一位置に配置された第2ダミーフィンを備えた第2スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記TAPセルは、
前記セル列境界に配置された前記拡散領域に電源供給する電源配線を備えた
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2セル列は、
前記セル列境界に最も近い位置に配置された前記第1方向に延びる第1フィンを備えた第3スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記第2セル列は、
前記第1フィンと前記第2方向における同一位置に配置された第2フィンを備えた第4スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記第1セル列は、
前記第1アクティブフィンと前記第2方向における同一位置に配置された第2アクティブフィンを備えた第2スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記第2スタンダードセルは前記第1アクティブフィンと前記第2方向における同一位置に配置された第2ダミーフィンを備えた
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記第1セル列は、
前記第1アクティブフィンと前記第2方向における同一位置に配置された第2ダミーフィンを備えた第2スタンダードセルを備えた
ことを特徴とする半導体集積回路装置。
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WO2015029280A1 (ja) * | 2013-08-28 | 2015-03-05 | パナソニック株式会社 | 半導体集積回路装置 |
JP6396834B2 (ja) * | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9859210B2 (en) * | 2015-06-19 | 2018-01-02 | Qualcomm Incorporated | Integrated circuits having reduced dimensions between components |
KR102318131B1 (ko) * | 2015-12-03 | 2021-10-26 | 삼성전자주식회사 | 반도체 장치 |
US9721841B1 (en) * | 2016-04-27 | 2017-08-01 | United Microelectronics Corp. | Electronic circuit of fin FET and methof for fabricating the electronic circuit |
CN109075126B (zh) * | 2016-05-06 | 2023-01-31 | 株式会社索思未来 | 半导体集成电路装置 |
US10236302B2 (en) * | 2016-06-22 | 2019-03-19 | Qualcomm Incorporated | Standard cell architecture for diffusion based on fin count |
CN109314080B (zh) | 2016-07-01 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
WO2018042986A1 (ja) * | 2016-08-29 | 2018-03-08 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US10354947B2 (en) | 2017-02-06 | 2019-07-16 | Samsung Electronics Co., Ltd. | Integrated circuit including standard cell |
KR102285790B1 (ko) * | 2017-07-04 | 2021-08-04 | 삼성전자 주식회사 | 필러 셀을 포함하는 집적 회로 |
JP6970357B2 (ja) | 2017-08-31 | 2021-11-24 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US11018157B2 (en) | 2017-09-28 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local interconnect structure |
WO2019142333A1 (ja) | 2018-01-19 | 2019-07-25 | 株式会社ソシオネクスト | 半導体集積回路装置 |
KR102495912B1 (ko) * | 2018-08-10 | 2023-02-03 | 삼성전자 주식회사 | 표준 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법 |
KR102495913B1 (ko) * | 2018-08-10 | 2023-02-03 | 삼성전자 주식회사 | 다중 높이 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법 |
JP6598949B2 (ja) * | 2018-08-30 | 2019-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
WO2020137660A1 (ja) * | 2018-12-25 | 2020-07-02 | 株式会社ソシオネクスト | 半導体集積回路装置 |
JP7364928B2 (ja) * | 2019-02-18 | 2023-10-19 | 株式会社ソシオネクスト | 半導体集積回路装置 |
JP6818107B2 (ja) * | 2019-10-01 | 2021-01-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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