TWI756405B - 靜態隨機存取記憶體的信噪比的調整方式以及反相器的結構 - Google Patents
靜態隨機存取記憶體的信噪比的調整方式以及反相器的結構 Download PDFInfo
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Abstract
一種反相器的結構,包含一第一鰭狀結構設置於一基底上的P型電晶體區,一第二鰭狀結構設置於基底上N型電晶體區,一閘極線設置於P型電晶體區和N型電晶體區,閘極線包含第一末端位在P型電晶體區以及第二末端位在N型電晶體區,二虛置閘極線分別位在閘極線兩側並且和閘極線平行,虛置閘極線包含第三末端位在P型電晶體區以及第四末端位在N型電晶體區,第一末端和第一鰭狀結構之間的第一距離大於第三末端和第一鰭狀結構之間的第三距離,並且第二末端和第二鰭狀結構之間的第二距離小於第四末端和第二鰭狀結構之間的第四距離。
Description
本發明係關於一種靜態隨機存取記憶體之信噪比的調整方式以及反相器的結構,特別是一種利用調整閘極長短以改善信噪比與反相器之效能的方式及結構。
在一個由六個電晶體所構成的靜態隨機存取記憶體(static random access memory,SRAM)中的每一個位元是儲存在四個場效電晶體構成兩個交叉耦合的反相器中,另外兩個場效電晶體是靜態隨機存取記憶體的位元線(Bit Line)的控制開關。靜態隨機存取記憶體本身屬於一種揮發性(volatile)的記憶單元(memory cell,MC),亦即當供給靜態隨機存取記憶體之電力消失之後,所儲存之資料會同時抹除。靜態隨機存取記憶體儲存資料之方式是利用記憶單元內電晶體的導電狀態來達成,其設計是採用互耦合電晶體為基礎,沒有電容器放電的問題,不需要不斷充電以保持資料不流失,也就是不需作記憶體更新的動作,這與同屬揮發性記憶體的動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)利用電容器帶電狀態儲存資料的方式並不相同。靜態隨機存取記憶體在電腦系統中當作快取記憶體(cache memory)等之應用,然而隨著電子元件的速度提升對於靜態隨機存取記憶體的效能以及讀寫速度的要求也隨之提高。
有鑑於此,本發明利用變化閘極長度,來提升電晶體的臨界電壓、讀取電流以及信噪比,以改善反相器和靜態隨機存取記憶體的效能。
根據本發明之一較佳實施例,一種反相器的結構,包含:一基底包含一P型電晶體區和一N型電晶體區,一第一鰭狀結構設置於P型電晶體區,一第二鰭狀結構設置於N型電晶體區,其中第二鰭狀結構平行第一鰭狀結構,一閘極線設置於P型電晶體區和N型電晶體區並且和第一鰭狀結構垂直,其中閘極線包含一第一末端位在P型電晶體區以及一第二末端位在N型電晶體區以及二第一虛置閘極線分別位在閘極線兩側並且第一虛置閘極線和第一鰭狀結構垂直,第一虛置閘極線包含一第三末端位在P型電晶體區以及一第四末端位在N型電晶體區,其中第一末端和第一鰭狀結構之間的一第一距離大於第三末端和第一鰭狀結構之間的一第三距離,並且第二末端和第二鰭狀結構之間的一第二距離小於第四末端和第二鰭狀結構之間的一第四距離。
根據本發明之一較佳實施例,一種靜態隨機存取記憶體之信噪比的調整方式,包含首先提供一基底,一第一長鰭狀結構和一第二長鰭狀結構設置於基底上,一第一短鰭狀結構和一第二短鰭狀結構設置於基底上並且位在第一長鰭狀結構和第二長鰭狀結構之間,一第一閘極線與第一長鰭狀結構、第一短鰭狀結構和第二長鰭狀結構交錯,一第二閘極線與第一長鰭狀結構、第二短鰭狀結構和第二長鰭狀結構交錯,其中第一長鰭狀結構包含一第一側和一第二側,第二側面向第一短鰭狀結構,第一側和第二側相對,第二長鰭狀結構包含一第三側和一第四側,第四側面向第二短鰭狀結構,第三側和第四側相對,然後進行一閘極線截斷步驟,閘極線截斷步驟包含將位在第一長鰭狀結構和第二短鰭狀結構之間的第二閘極線去除一第一長度,將位在第二長鰭狀結構和第一短鰭狀結構之間的第一閘極線去除第一長度,將位在第一長鰭狀結構之第一側的第一閘極線去除一第二長度,將位在第二長鰭狀結構之第三側的第二閘極線
去除第二長度,值得注意的是:當第一長度大於第二長度時,靜態隨機存取記憶體的信噪比大於當第一長度等於該第二長度時靜態隨機存取記憶體的信噪比。
10:基底
12a:第一長鰭狀結構
12b:第二長鰭狀結構
14a:第一短鰭狀結構
14b:第二短鰭狀結構
16a:第一閘極線
16b:第二閘極線
18:第一側
19:區域
20:第二側
22:第三側
24:第四側
26:介電層
28:儲存節點
30:儲存節點
50:基底
52:P型電晶體區
54:N型電晶體區
56a:第一鰭狀結構
56b:第二鰭狀結構
58:閘極線
60:第一虛置閘極線
62:P型電晶體
64:N型電晶體
66:介電層
68:第二虛置閘極線
100:靜態隨機存取記憶體
116a:第一閘極線段落
116b:第二閘極線段落
158:第一末端
160:第三末端
168:第五末端
200:靜態隨機存取記憶體
258:第二末端
260:第四末端
268:第六末端
300:靜態隨機存取記憶體
BL1:位元線
BL2:位元線
d1:第一調整長度
d2:第二調整長度
d3:第三調整長度
L:基本長度
L1:第一長度
L2:第二長度
L3:第三長度
PD1:第一下拉電晶體
PD2:第二下拉電晶體
PG1:第一存取電晶體
PG2:第二存取電晶體
PU1:第一上拉電晶體
PU2:第二上拉電晶體
S1:第一距離
S2:第二距離
S3:第三距離
S4:第四距離
S5:第五距離
S6:第六距離
VCC:電壓源
VSS:電壓源
WL:字元線
第1圖至第2圖為根據本發明之第一較佳實施例所繪示的一種靜態隨機存取記憶體的製作方法。
第3圖至第4圖為根據本發明之第二較佳實施例所繪示的一種靜態隨機存取記憶體之信噪比的調整方式。
第5圖為第4圖中的靜態隨機存取記憶體之等效電路圖。
第6圖至第7圖為根據本發明之第三較佳實施例所繪示的一種靜態隨機存取記憶體之讀取電流值的調整方式。
第8圖為根據本發明之第四較佳實施例所繪示的一種反相器的結構。
第9圖為根據本發明之第五較佳實施例所繪示的N型電晶體結構。
第10圖為根據本發明之第六較佳實施例所繪示的P型電晶體結構。
第1圖至第2圖為根據本發明之第一較佳實施例所繪示的一種靜態隨機存取記憶體的製作方法。
如第1圖所示,首先提供一基底10,一第一長鰭狀結構12a、一第二長鰭狀結構12b、一第一短鰭狀結構14a和一第二短鰭狀結構14b設置於基底10上,第一短鰭狀結構14a和第二短鰭狀結構14b位在第一長鰭狀結構12a和第二長鰭狀結構12b之間,第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構
14a和第二短鰭狀結構14b彼此互相平行。另外,一第一閘極線16a與第一長鰭狀結構12a、第一短鰭狀結構14a和第二長鰭狀結構12b交錯,一第二閘極線16b與第一長鰭狀結構12a、第二短鰭狀結構14b和第二長鰭狀結構12b交錯,第一閘極線16a和第二閘極線16b彼此互相平行,值得注意的是:第一短鰭狀結構14a不和第二閘極線16b重疊或交錯,第二短鰭狀結構14b不和第一閘極線16a重疊或交錯。詳細來說,第一長鰭狀結構12a包含一第一側18和一第二側20,第二側20係面向第一短鰭狀結構14a,第一側18和第二側20相對,第二長鰭狀結構12b包含一第三側22和一第四側24,第四側24面向第二短鰭狀結構14b,第三側22和第四側24相對。基底10可以為一矽基底、一鍺基底、一砷化鎵基底、一矽鍺基底、一磷化銦基底、一氮化鎵基底或一碳化矽基底基底。第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構14a和第二短鰭狀結構14b可以是由基底10延伸出來並且與基底10具有相同材料,第一閘極線16a和第二閘極線16b可以包含一導電多晶矽和一閘極介電層。
接著進行一閘極線截斷步驟,提供一基本長度L,基本長度L、第一閘極線16a和第二閘極線16b平行。同時將位在第一長鰭狀結構12a和第二短鰭狀結構14b之間的第二閘極線16b、位在第二長鰭狀結構12b和第一短鰭狀結構14a之間的第一閘極線16a、位在第一長鰭狀結構12a之第一側18的第一閘極線16a和位在第二長鰭狀結構12b之第三側22的第二閘極線16b去除基本長度L,也就是說第一閘極線16a和第二閘極線16b同時各自被去除了二個不連續的基本長度L。如第2圖所示,在閘極線截斷步驟之後,第一閘極線16a被截斷成三條第一閘極線段落116a,第二閘極線16b被截斷成三條第二閘極線段落116b,最後再形成一介電層26包覆各個第一閘極線段落116a之末端以及各個第二閘極線段落16b之末端。
閘極線截斷步驟可以利用微影製程加上蝕刻製程完成,舉例而言,
可以形成一光阻(圖未示)覆蓋基底10、第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構14a、第二短鰭狀結構14b、第一閘極線16a和第二閘極線16b,然後利用一光罩(圖未示)圖案化光阻,在光阻上定義出後續要去除的區域19包含了要去除的第一閘極線16a和第二閘極線16b之位置,之後以蝕刻製程同時將部分的第一閘極線16a和部分的第二閘極線16b移除數個基本長度L,以形成數條第一閘極線段落116a和數條第二閘極線段落116b。
請繼續參閱第2圖,完成後的數條第一閘極線段落116a、數條第二閘極線段落116b、第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構14a和第二短鰭狀結構14b共同組成一靜態隨機存取記憶體100,此靜態隨機存取記憶體100具有一初始的信噪比和一初始的讀取電流值。
第3圖至第4圖為根據本發明之第二較佳實施例所繪示的一種靜態隨機存取記憶體之信噪比的調整方式,其中具有相同功能和位置的元件將給予如第一較佳實施例中相同的標號。
如第3圖所示,首先提供如第一較佳實施例中所述之基底10、第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構14a、第二短鰭狀結構14b、第一閘極線16a與第二閘極線16b,其中詳細的材料和位置請參閱第一較佳實施例,在此不予贅述。
接著進行一閘極線截斷步驟,提供一第一長度L1和一第二長度L2,其中第一長度L1大於第一較佳實施例中的基本長度L,第二長度L2小於第一較佳實施例中的基本長度L,也就是說第一長度L1大於第二長度L2。第一長度L1、第二長度L2和基本長度L平行。第一閘極線16a第二閘極線16b上的第一長度L1較基本長度L分別向第一長鰭狀結構12a和第二長鰭狀結構12b的方向上增加了一第一調整長度d1,在第一閘極線16a和第二閘極線上16b的第二長度L2較基本長度L分別向遠離第一側18和第三側22的方向上減少了一第二調整長度d2,第一調整長
度d1和第二調整長度d2可以相同也可以相異。如同第一較佳實施例中的教示,閘極線截斷步驟可以使用微影製程加上蝕刻製程完成。
在閘極線截斷步驟中,將位在第一長鰭狀結構12a和第二短鰭狀結構14b之間、離第一短鰭狀結構14a和第一長鰭狀結構12a較近並且離第二短鰭狀結構14b較遠的第二閘極線16b移除第一長度L1,將位在第二長鰭狀結構12b和第一短鰭狀結構14a之間離第二短鰭狀結構14b和第二長鰭狀結構12b較近並且離第一短鰭狀結構14a較遠的第一閘極線16a移除第一長度L1,將位在第一長鰭狀結構12a之第一側18的第一閘極線16a和位在第二長鰭狀結構12b之第三側22的第二閘極線16b移除第二長度L2。
如第4圖所示,在閘極線截斷步驟之後,第一閘極線16a被截斷成三條第一閘極線段落116a,第二閘極線16b被截斷成三條第二閘極線段落116b,二條第一閘極線段落116a、二條第二閘極線段落116b、第一長鰭狀結構12a、第二長鰭狀結構12b、第一短鰭狀結構14a和第二短鰭狀結構14b共同組成一靜態隨機存取記憶體200,再形成一介電層26包覆各個第一閘極線段落116a之末端以及各個第二閘極線段落116b之末端,介電層26可以為氮化矽、氧化矽等絶緣材料。
第一長鰭狀結構12a和第一閘極線段落116a交疊處形成一第一下拉電晶體(Pull-Down transistor)PD1,第一長鰭狀結構12a和第二閘極線段落116b交疊處形成一第一存取電晶體(pass gate transistor)PG1,第一短鰭狀結構14a和第一閘極線段落116a交疊處形成一第一上拉電晶體(Pull-Up transistor)PU1,第二短鰭狀結構14b和第二閘極線段落116b交疊處形成一第二上拉電晶體PU2,第二長鰭狀結構12b和第一閘極線段落116a交疊處形成一第二存取電晶體PG2,第二長鰭狀結構12b和第二閘極線段落116b交疊處形成一第二下拉電晶體PD2。第一較佳實施例和第二較佳實施例的不同之處在於移除的閘極線長度不同,第二較佳實施例所製作出來的第一存取電晶體PG1和第二存取電晶體PG2中的閘極線段
落會比第一較佳實施例所製作出來的在相同位置的閘極線段落短,而第二較佳實施例所製作出來的第一下拉電晶體PD1和第二下拉電晶體PD2中的閘極線段落會比第一較佳實施例所製作出來的在相同位置的閘極線段落長。又因為介電層26中內含有應力,因此會由第一閘極線段落116a之末端以及第二閘極線段落116b之末端向第一閘極線段落116a和第二閘極線段落116b施加應力,最後造成在第二較佳實施例中的第一存取電晶體PG1、第二存取電晶體PG2、第一下拉電晶體PD1和第二下拉電晶體PD2所受到的應力和第一較佳實施例中的不同,因此第二較佳實施例中各個電晶體的臨界電壓和第一較佳實施例中的也會不同,最後靜態隨機存取記憶體200的信噪比就會較靜態隨機存取記憶體100大。
第5圖為第4圖中的靜態隨機存取記憶體之等效電路圖。請同時參閱第4圖和第5圖,第一上拉電晶體PU1、第二上拉電晶體PU2、第一下拉電晶體PD1和第二下拉電晶體PD2構成栓鎖電路(latch),使資料可以栓鎖在儲存節點(Storage Node)28或30。其中,第一上拉電晶體PU1和第一下拉電晶體PD1一同構成一反相器(inverter),且這兩者所構成的串接電路兩端點分別耦接於一電壓源Vcc與一電壓源Vss;同樣地,第二上拉電晶體PU2與第二下拉電晶體PD2構成另一反相器,而這兩者所構成的串接電路兩端點亦分別耦接於電壓源Vcc與電壓源Vss。上述兩反相器互相耦合以儲存資料。
在一實施例中,第一上拉電晶體PU1、第二上拉電晶體PU2是由P型電晶體所組成,而第一下拉電晶體PD1、第二下拉電晶體PD2和第一存取電晶體PG1、第二存取電晶體PG2則是由N型電晶體所組成,但本發明不限於此。此外,在儲存節點30處電連接有第一存取電晶體PG1的源極;同樣地,在儲存節點28電連接有第二存取電晶體PG2的源極。至於第一存取電晶體PG1和第二存取電晶體PG2的閘極則分別耦接至字元線WL,而第一存取電晶體PG1和第二存取電晶體PG2的汲極則分別耦接至相對應之位元線BL1與BL2。
第6圖至第7圖為根據本發明之第三較佳實施例所繪示的一種靜態隨機存取記憶體之讀取電流值的調整方式,其中具有相同功能和位置的元件將給予如第一較佳實施例中相同的標號。第三較佳實施例和第二較佳實施例的不同之處在於在第三較佳實施例中以第三長度L3取代第二較佳實施例中的第一長度L1,並且第三較佳實施例在相同位置延用第二較佳實施例中的第二長度L2。詳細來說,第三長度較基本長度L分別向遠離第一長鰭狀結構12a和第二長鰭狀結構12b的方向上減少了一第三調整長度d3,也就是說第三長度L3較基本長度L小,以此方式製作出來的靜態隨機存取記憶體300的讀取電流值會較靜態隨機存取記憶體100的讀取電流值大。
第8圖為根據本發明之第四較佳實施例所繪示的一種反相器的結構,本發明之反相器的結構可以應用在靜態隨機存取記憶體中,反相器的結構包含一基底50,基底包含一P型電晶體區52和一N型電晶體區54,一第一鰭狀結構56a設置於P型電晶體區52,一第二鰭狀結構56b設置於N型電晶體區54,其中第二鰭狀結構56b平行第一鰭狀結構56a。一條閘極線58設置於P型電晶體區52和N型電晶體區54並且和第一鰭狀結構56a和第二鰭狀結構56b垂直,其中閘極線58包含一第一末端158位在P型電晶體區52以及一第二末端258位在N型電晶體區54。二條第一虛置閘極線60分別位在閘極線58的兩側並且第一虛置閘極線60和第一鰭狀結構56a以及第二鰭狀結構56b垂直,二條第一虛置閘極線60各自包含一第三末端160位在P型電晶體區52以及一第四末端260位在N型電晶體區54,值得注意的是:其中第一末端158和第一鰭狀結構56a之間的一第一距離S1大於第三末端160和第一鰭狀結構56a之間的一第三距離S3,並且第二末端258和第二鰭狀結構56b之間的一第二距離S2小於第四末端260和第二鰭狀結構56b之間的一第四距離S4。第一距離S1、第二距離S2、第三距離S3、第四距離S4和閘極線58平行。
此外閘極線58上和第一鰭狀結構56a之重疊區域構成一P型閘極,在P
型閘極兩側的第一鰭狀結構56a內設置有P型源極/汲極摻雜區(圖未示),由第P型閘極、P型源極/汲極摻雜區以及第一鰭狀結構56a共同構成一P型電晶體62;在閘極線58上和第二鰭狀結構56b之重疊區域構成一N型閘極,在N型閘極兩側的第二鰭狀結構56b內設置有N型源極/汲極摻雜區(圖未示),由第N型閘極、N型源極/汲極摻雜區以及第二鰭狀結構56b共同構成一N型電晶體64。由N型電晶體62和P型電晶體64共同構成一反相器。
此外一介電層66包覆第一末端158、第二末端258、第三末端160和第四末端260。介電層66可以為氮化矽、氧化矽或是其它絶緣材料,並且在介電層66中內含有應力,因此介電層66中的應力可以施加在第一末端158、第二末端258、第三末端160和第四末端260,進而改變N型閘極或P型閘極正下方的鰭狀結構中的應力。介電層66中的應力為伸張應力,所以,在P型電晶體62中,當P型電晶體62之P型閘極的閘極線58之第一末端158離P型電晶體62之第一鰭狀結構56a越遠時,P型電晶體62的效能越好;N型電晶體64中的N型閘極的閘極線58之第二末端258離N型電晶體64中的第二鰭狀結構56b越近時,N型電晶體64的效能越好。
根據本發明之一較佳實施例,反相器的結構,可以另包含二條第二虛置閘極線68,各條第二虛置閘極線68各自設置於各條第一虛置閘極線60之一側,並且不在第一虛置閘極線60和閘極線58之間。第一虛置閘極線60和第二虛置閘極線68都是浮置,只有閘極線58有外接電壓,第一虛置閘極線60和第二虛置閘極線68是在形成閘極線58時為了避免負載現象(loading effect)而形成。
另外,各條第二虛置閘極線68具有一第五末端168位在P型電晶體區52以及一第六末端268位在N型電晶體區54,第三距離S3大於第五末端168和第一鰭狀結構56a之間的一第五距離S5,第四距離S4小於第六末端268和該第二鰭狀結構56b之間的一第六距離S6。同樣地第五末端168和第六末端268也被介電層66包
覆。第一虛置閘極線60和第二虛置閘極線68的末端和相鄰的鰭狀結構之間的距離會對P型電晶體62和N型電晶體64所受到應力產生影響,離閘極線58越近的虛置閘極線對P型電晶體62和N型電晶體64的效能影響越大,也就是說第一虛置閘極線60的第三末端160和第一鰭狀結構56a之間的第三距離S3對P型電晶體62的影響大於第二虛置閘極線68的第五末端168和第一鰭狀結構56a之間的第五距離S5對P型電晶體62的影響;相同的,第一虛置閘極線60的第四末端260和第二鰭狀結構56b之間的第四距離S4對N型電晶體64的影響大於第二虛置閘極線68的第六末端268和第二鰭狀結構56b之間的第六距離S6對N型電晶體64的影響。第一虛置閘極線60和第二虛置閘極線68的末端和鰭狀結構之間的距離係按照虛置閘極線和閘極線58之間的遠近,以及虛置閘極線是作為N型電晶體64或是P型電晶體62旁的虛置閘極線來決定其末端和鰭狀結構之間的距離。所以,P型電晶體區52內的第一末端158、第三末端160和第五末端168至第一鰭狀結構56a之間的距離是第一距離S1最大,第三距離S3次之,而第五距離S5最小;N型電晶體區54內的第二末端258、第四末端260和第六末端268至第二鰭狀結構56b之間的距離是第六距離S6最大,第四距離S4次之,而第二距離S2最小。
第9圖為根據本發明之第五較佳實施例所繪示的N型電晶體結構,其中具有相同功能和位置的元件將給予如第四較佳實施例中相同的標號。和第四較佳實施例不同的是:第五較佳實施例中只有一條第二鰭狀結構56b位在N型電晶體區54並且沒有P型電晶體區,所以閘極線58的第二末端258、第一虛置閘極線60的第四末端260和第二虛置閘極線68的第六末端268係按照第四較佳實施例中的N型電晶區54第六距離S6最大,第四距離S4次之,而第二距離S2最小的原則排列。此外,閘極線58、第一虛置閘極線60和第二虛置閘極線68可以只有一頭的末端按照上述原則排列,另一頭的末端切齊。也可以如第9圖所示的兩頭的末端都按照上述原則排列,若是兩頭的末端都按照上述原則排列其效能會比只有
一頭的末端按照上述原則排列的效能增加2倍。
第10圖為根據本發明之第六較佳實施例所繪示的P型電晶體結構,其中具有相同功能和位置的元件將給予如第四較佳實施例中相同的標號。和第四較佳實施例不同的是:第六較佳實施例中只有一條第一鰭狀結構56a位在P型電晶體區52並且沒有N型電晶體區,所以閘極線58的第一末端158、第一虛置閘極線60的第三末端160和第二虛置閘極線68的第五末端168係按照第四較佳實施例中的P型電晶區內的第一距離S1最大,第三距離S3次之,而第五距離S5最小的原則排列,此外,閘極線58、第一虛置閘極線60和第二虛置閘極線68可以只有一頭的末端按照上述原則排列,另一頭的末端切齊,也可以如第10圖所示的兩頭的末端都按照上述原則排列,若是兩頭的末端都按照上述原則排列其效能會比只有一頭的末端按照上述原則排列的效能增加2倍。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
50:基底
52:P型電晶體區
54:N型電晶體區
56a:第一鰭狀結構
56b:第二鰭狀結構
58:閘極線
60:第一虛置閘極線
62:P型電晶體
64:N型電晶體
66:介電層
68:第二虛置閘極線
158:第一末端
160:第三末端
168:第五末端
258:第二末端
260:第四末端
268:第六末端
S1:第一距離
S2:第二距離
S3:第三距離
S4:第四距離
S5:第五距離
S6:第六距離
Claims (6)
- 一種反相器的結構,包含:一基底包含一P型電晶體區和一N型電晶體區;一第一鰭狀結構設置於該P型電晶體區;一第二鰭狀結構設置於該N型電晶體區,其中該第二鰭狀結構平行該第一鰭狀結構;一閘極線設置於該P型電晶體區和該N型電晶體區並且和該第一鰭狀結構垂直,其中該閘極線包含一第一末端位在該P型電晶體區以及一第二末端位在該N型電晶體區;以及二第一虛置閘極線分別位在該閘極線兩側並且該等第一虛置閘極線和該第一鰭狀結構垂直,各該第一虛置閘極線包含一第三末端位在該P型電晶體區以及一第四末端位在該N型電晶體區;其中該第一末端和該第一鰭狀結構之間的一第一距離大於該第三末端和該第一鰭狀結構之間的一第三距離,並且該第二末端和該第二鰭狀結構之間的一第二距離小於該第四末端和該第二鰭狀結構之間的一第四距離。
- 如請求項1所述之反相器的結構,另包含:二第二虛置閘極線,各該第二虛置閘極線各自設置於各該第一虛置閘極線之一側,並且不在第一虛置閘極線和該閘極線之間,各該第二虛置閘極線具有一第五末端位在該P型電晶體區以及一第六末端位在該N型電晶體區,該第三距離大於該第五末端和該第一鰭狀結構之間的一第五距離,該第四距離小於該第六末端和該第二鰭狀結構之間的一第六距離。
- 如請求項1所述之反相器的結構,其中該第一距離、該第二距離、該 第三距離、第四距離和該閘極線平行。
- 如請求項1所述之反相器的結構,其中該閘極線上和該第一鰭狀結構之重疊區域構成一P型閘極,在該P型閘極兩側的該第一鰭狀結構內設置有P型源極/汲極摻雜區。
- 如請求項1所述之反相器的結構,其中在該閘極線上和該第二鰭狀結構之重疊區域構成一N型閘極,在該N型閘極兩側的該第二鰭狀結構內設置有N型源極/汲極摻雜區。
- 如請求項1所述之反相器的結構,其中各該第一末端、該第二末端、該第三末端和該第四末端被一介電層包覆。
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