JP6970357B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 57
- 239000002070 nanowire Substances 0.000 claims description 52
- 230000005669 field effect Effects 0.000 claims description 7
- 230000003068 static effect Effects 0.000 claims description 7
- 230000004048 modification Effects 0.000 description 28
- 238000012986 modification Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 18
- 239000000758 substrate Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Description
図1は実施形態に係る半導体集積回路装置(半導体チップ)の全体構成を模式的に示す平面図である。図1では、図面横方向をX方向とし、図面縦方向をY方向としている(以降の図も同様)。図1に示す半導体集積回路装置1は、内部コア回路が形成されたコア領域2と、コア領域2の周囲に設けられ、インターフェース回路(IO回路)が形成されたIO領域3とを備えている。IO領域3には、半導体集積回路装置1の周辺部を囲むように、IOセル列5が設けられている。図1では図示を簡略化しているが、IOセル列5には、インターフェース回路を構成する複数のIOセル10が並んでいる。
図5は変形例1に係るVDDIO用ESD部101の構成を示す図である。図5の構成は、図3の構成とほぼ同様である。ただし、入出力信号が供給されるフィン構造部12A、14Aにおいて、フィン17の本数が、図3におけるフィン構造部12,14と比べて、少なくなっている。具体的には、フィン構造部12A,14Aは、Y方向における中央部の2本のフィンが省かれており、4本のフィン17を含む。ただし、Y方向において、フィン構造部12A,14Aが占める幅は、図3におけるフィン構造部12,14と同等である。すなわち、フィン構造部12A,14Aは、フィン間隔が、フィン構造部11,13,15のフィン間隔よりも広い部分を有している。
図6は変形例2に係るVDDIO用ESD部101の構成を示す図である。図6の構成は、図3の構成とほぼ同様である。ただし、フィン構造部11,13,15において、フィン16の上に、Y方向に延びるゲート19aが形成されており、フィン構造部12,14において、フィン17の上に、Y方向に延びるゲート19bが形成されている。すなわち、フィン構造部11〜15は、フィン16,17とゲート19a,19bとからなる、フィンFETと同一の構造を含む。
図9は変形例3に係るVDDIO用ESD部101の構成を示す図である。図9の構成は、図3の構成とほぼ同様である。ただし、入出力信号が供給されるフィン構造部12,14のX方向における両側に、複数のN導電型フィン16からなるフィン構造部41,42,43,44が設けられている。そして、配線層M1において、フィン構造部41,42,43,44の上に、配線51,52,53,54が設けられている。配線51,52,53,54は、フィン構造部11,13,15の上に配置された配線81,83,85と接続されている。
第2実施形態に係る半導体集積回路装置の全体構成は、図1に示すとおりである。本実施形態では、第1実施形態と同様に、半導体集積回路装置1はフィンFETを備えるものとする。そしてここでは、図2(b)に示すIOセル10BにおけるVDDIO用ESD部103,VSS用ESD部104を例にとって、本実施形態におけるESD保護回路の構成について説明する。
第3実施形態に係る半導体集積回路装置の全体構成は、図1に示すとおりである。本実施形態では、半導体集積回路装置1はナノワイヤFETを備えるものとする。そして、ここでは、図2(a)に示すIOセル10AにおけるVDDIO用ESD部101、VSS用ESD部102を例にとって、本実施形態におけるESD保護回路の構成について説明を行う。
図12は変形例1に係るVDDIO用ESD部101の構成を示す図である。図12の構成は、図11の構成において、パッド構造部111〜115からナノワイヤ141,146およびゲート143,148を省いた構成に相当する。すなわち、図12において、121,123,125はN導電型のパッド142を含むパッド構造部(第1パッド構造部)である。122,124はP導電型のパッド147を含むパッド構造部(第2パッド構造部)である。
図11の構成において、ゲート143,148を省いた構成としてもよい。また、図12の構成において、X方向に分離して並ぶパッド142,147を、X方向に延びる長い単一のパッドに変えてもよい。
第4実施形態に係る半導体集積回路装置の全体構成は、図1に示すとおりである。本実施形態では、第3実施形態と同様に、半導体集積回路装置1はナノワイヤFETを備えるものとする。そしてここでは、図2(b)に示すIOセル10BにおけるVDDIO用ESD部103,VSS用ESD部104を例にとって、本実施形態におけるESD保護回路の構成について説明を行う。
6,61,62,63,64 電源配線(第2電源配線)
7,71,72,73,74 電源配線(第2電源配線)
11,13,15 フィン構造部(第1フィン構造部)
12,14 フィン構造部(第2フィン構造部)
16,17 フィン
19a,19b ゲート
21,23,25 フィン構造部(第1フィン構造部)
22,24 フィン構造部(第2フィン構造部)
26,27 フィン
31,33,35 フィン構造部(第1フィン構造部)
32,34 フィン構造部(第2フィン構造部)
41,42,43,44 フィン構造部(第3フィン構造部)
81,83,85 配線(第1電源配線)
82,84 配線(第1信号配線)
91,93,95 配線(第1電源配線)
92,94 配線(第1信号配線)
101,103 VDDIO用ESD部(ESD保護回路)
102,104 VSS用ESD部(ESD保護回路)
111,113,115,121,123,125,131,133,135 パッド構造部(第1パッド構造部)
112,114,122,124,132,134 パッド構造部(第2パッド構造部)
141,146,151,156 ナノワイヤ
142,147,152,157 パッド
143,148,153,158 ゲート
191,193,195 配線(第1電源配線)
192,194 配線(第1信号配線)
Claims (14)
- フィンFET(Field Effect Transistor)を備えた半導体集積回路装置であって、
ESD(Electro Static Discharge)保護回路を備え、
前記ESD保護回路は、
第1方向に延び、前記第1方向と垂直をなす第2方向に並ぶ複数の第1導電型のフィンを含む第1フィン構造部と、
前記第1方向に延び、前記第2方向に並ぶ複数の第2導電型のフィンを含み、前記第1フィン構造部と前記第2方向において対向する第2フィン構造部と、
前記第1および第2フィン構造部の上層にある第1配線層に形成され、第3方向に延び、前記第1フィン構造部と接続された、電源供給用の第1電源配線と、
前記第1配線層に形成され、前記第3方向に延び、前記第2フィン構造部と接続された、信号転送用の第1信号配線と、
前記第1配線層より上層の第2配線層に形成され、前記第3方向と垂直をなす第4方向に延び、前記第1電源配線と接続された、電源供給用の第2電源配線とを備え、
前記第2方向において、前記第2フィン構造部が占める幅は、前記第1フィン構造部が占める幅よりも大きく、
前記第4方向において、前記第1信号配線の幅は、前記第1電源配線の幅よりも大きい
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第3方向は、前記第1方向と同一であり、前記第4方向は、前記第2方向と同一である
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第3方向は、前記第2方向と同一であり、前記第4方向は、前記第1方向と同一である
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2フィン構造部は、フィンの本数が、前記第1フィン構造部におけるフィンの本数よりも多い
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1および第2フィン構造部は、フィン上に前記第2方向に延びるように形成されたゲートを含む
ことを特徴とする半導体集積回路装置。 - 請求項5記載の半導体集積回路装置において、
前記第2フィン構造部は、ゲートが、フローティング状態になっている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記ESD保護回路は、
前記第2フィン構造部の、前記第1方向における少なくともいずれか一方の側に配置され、前記第1方向に延び、前記第2方向に並ぶ複数の前記第1導電型のフィンを含む第3フィン構造部を備え、
前記第3フィン構造部は、前記第1および第2電源配線を介して、電源が供給される
ことを特徴とする半導体集積回路装置。 - ナノワイヤFET(Field Effect Transistor)を備えた半導体集積回路装置であって、
ESD(Electro Static Discharge)保護回路を備え、
前記ESD保護回路は、
第1方向に延び、前記第1方向と垂直をなす第2方向に複数列に並ぶ第1導電型のパッドを含む第1パッド構造部と、
前記第1方向に延び、前記第2方向に複数列に並ぶ第2導電型のパッドを含み、前記第1パッド構造部と前記第2方向において対向する第2パッド構造部と、
前記第1および第2パッド構造部の上層にある第1配線層に形成され、第3方向に延び、前記第1パッド構造部と接続された、電源供給用の第1電源配線と、
前記第1配線層に形成され、前記第3方向に延び、前記第2パッド構造部と接続された、信号転送用の第1信号配線と、
前記第1配線層より上層の第2配線層に形成され、前記第3方向と垂直をなす第4方向に延び、前記第1電源配線と接続された、電源供給用の第2電源配線とを備え、
前記第2方向において、前記第2パッド構造部が占める幅は、前記第1パッド構造部が占める幅よりも大きく、
前記第4方向において、前記第1信号配線の幅は、前記第1電源配線の幅よりも大きい
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記第3方向は、前記第1方向と同一であり、前記第4方向は、前記第2方向と同一である
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記第3方向は、前記第2方向と同一であり、前記第4方向は、前記第1方向と同一である
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記第2パッド構造部は、前記第2方向におけるパッドの列数が、前記第1パッド構造部におけるパッドの列数よりも多い
ことを特徴とする半導体集積回路装置。 - 請求項9記載の半導体集積回路装置において、
前記第1および第2パッド構造部は、それぞれ、前記第1方向において前記パッドとナノワイヤとが交互に並ぶ構造体と、前記ナノワイヤの周囲を囲み、前記第2方向に延びるように形成されたゲートとを含む
ことを特徴とする半導体集積回路装置。 - 請求項12記載の半導体集積回路装置において、
前記第2パッド構造部は、ゲートが、フローティング状態になっている
ことを特徴とする半導体集積回路装置。 - フィンFET(Field Effect Transistor)を備えた半導体集積回路装置であって、
ESD(Electro Static Discharge)保護回路を備え、
前記ESD保護回路は、
第1方向に延び、前記第1方向と垂直をなす第2方向に並ぶ複数の第1導電型のフィンと、フィン上に前記第2方向に延びるように形成されたゲートとを含む、第1フィン構造部と、
前記第1方向に延び、前記第2方向に並ぶ複数の第2導電型のフィンと、フィン上に前記第2方向に延びるように形成されたゲートとを含み、前記第1フィン構造部と前記第2方向において対向する第2フィン構造部と、
前記第1および第2フィン構造部の上層にある第1配線層に形成され、第3方向に延び、前記第1フィン構造部と接続された、電源供給用の第1電源配線と、
前記第1配線層に形成され、前記第3方向に延び、前記第2フィン構造部と接続された、信号転送用の第1信号配線と、
前記第1配線層より上層の第2配線層に形成され、前記第3方向と垂直をなす第4方向に延び、前記第1電源配線と接続された第2電源配線とを備え、
前記第2フィン構造部は、ゲートが、フローティング状態になっている
ことを特徴とする半導体集積回路装置。
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