JP2010251552A - 配線基板及び半導体パッケージ並びにそれらの製造方法 - Google Patents
配線基板及び半導体パッケージ並びにそれらの製造方法 Download PDFInfo
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- JP2010251552A JP2010251552A JP2009099989A JP2009099989A JP2010251552A JP 2010251552 A JP2010251552 A JP 2010251552A JP 2009099989 A JP2009099989 A JP 2009099989A JP 2009099989 A JP2009099989 A JP 2009099989A JP 2010251552 A JP2010251552 A JP 2010251552A
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- Prior art keywords
- layer
- metal layer
- wiring board
- wiring
- protruding
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 301
- 229910052751 metal Inorganic materials 0.000 claims abstract description 301
- 238000000034 method Methods 0.000 claims abstract description 52
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims description 76
- 238000005530 etching Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 39
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 3
- 238000009413 insulation Methods 0.000 abstract 3
- 230000010485 coping Effects 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 53
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 39
- 229910045601 alloy Inorganic materials 0.000 description 25
- 239000000956 alloy Substances 0.000 description 25
- 238000007747 plating Methods 0.000 description 22
- 229910052718 tin Inorganic materials 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 17
- 238000010586 diagram Methods 0.000 description 15
- 229910052709 silver Inorganic materials 0.000 description 12
- 239000000243 solution Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000000654 additive Substances 0.000 description 7
- 239000007864 aqueous solution Substances 0.000 description 6
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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Abstract
【解決手段】支持体上に、前記支持体の表面を露出する柱状の貫通孔を有する第1金属層を形成し、前記柱状の貫通孔から露出する前記支持体の表面及び前記柱状の貫通孔の内壁面を覆うように第2金属層11aを形成する。前記第2金属層上に前記柱状の貫通孔を充填するように第3金属層11bを形成する。次に、前記第3金属層を覆うように前記第1金属層上に絶縁層12aを形成し、前記絶縁層の一方の面に、前記第3金属層と電気的に接続する配線層13aを形成する。次に、前記支持体及び前記第1金属層を除去し、前記第2金属層及び前記第3金属層を含んで構成され前記絶縁層の他方の面から突出する突出部11を形成する突出部形成工程と、を有する。
【選択図】図15
Description
第1の実施の形態では、本発明を多層配線層(ビルドアップ配線層)を有する配線基板に適用する例を示す。
始めに、第1の実施の形態に係る配線基板の構造について説明する。図15は、第1の実施の形態に係る配線基板を例示する断面図である。図15を参照するに、配線基板10は、第1絶縁層12aと、第2絶縁層12bと、第3絶縁層12cと、第1配線層13aと、第2配線層13bと、第3配線層13cと、ソルダーレジスト層14と、接続端子16と、第4金属層17とを有するビルドアップ配線層を備えた配線基板である。
続いて、第1の実施の形態に係る配線基板の製造方法について説明する。図16〜図30は、第1の実施の形態に係る配線基板の製造工程を例示する図である。図16〜図30において、図15と同一部品については、同一符号を付し、その説明は省略する場合がある。
第2の実施の形態では、本発明を多層配線層(ビルドアップ配線層)を有する配線基板に適用する他の例を示す。第2の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
始めに、第2の実施の形態に係る配線基板の構造について説明する。図31は、第2の実施の形態に係る配線基板を例示する断面図である。図31を参照するに、配線基板30は、第1絶縁層12aと、第2絶縁層12bと、第3絶縁層12cと、第1配線層13aと、第2配線層13bと、第3配線層13cと、ソルダーレジスト層14と、接続端子36と、第4金属層17とを有するビルドアップ配線層を備えた配線基板である。
続いて、第2の実施の形態に係る配線基板の製造方法について説明する。図32〜図35は、第2の実施の形態に係る配線基板の製造工程を例示する図である。図32〜図35において、図31と同一部品については、同一符号を付し、その説明は省略する場合がある。
第3の実施の形態では、本発明を多層配線層(ビルドアップ配線層)を有する配線基板に適用する他の例を示す。第3の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
始めに、第3の実施の形態に係る配線基板の構造について説明する。図36は、第3の実施の形態に係る配線基板を例示する断面図である。図36を参照するに、配線基板50は、第1絶縁層12aと、第2絶縁層12bと、第3絶縁層12cと、第1配線層13aと、第2配線層13bと、第3配線層13cと、ソルダーレジスト層14と、接続端子56と、第4金属層17とを有するビルドアップ配線層を備えた配線基板である。
第4の実施の形態では、本発明を多層配線層(ビルドアップ配線層)を有する配線基板に適用する他の例を示す。第4の実施の形態において、第2の実施の形態と共通する部分についてはその説明を省略し、第2の実施の形態と異なる部分を中心に説明する。
始めに、第4の実施の形態に係る配線基板の構造について説明する。図37は、第4の実施の形態に係る配線基板を例示する断面図である。図37を参照するに、配線基板60は、第1絶縁層12aと、第2絶縁層12bと、第3絶縁層12cと、第1配線層13aと、第2配線層13bと、第3配線層13cと、ソルダーレジスト層14と、接続端子66と、第4金属層17とを有するビルドアップ配線層を備えた配線基板である。
第5の実施の形態では、本発明をビルドアップ配線層を有する配線基板に半導体チップを搭載した半導体パッケージに適用する例を示す。第5の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
始めに、第5の実施の形態に係る半導体パッケージの構造について説明する。 図38は、第5の実施の形態に係る半導体パッケージを例示する断面図である。図38において、図15と同一部品については、同一符号を付し、その説明は省略する場合がある。図38を参照するに、半導体パッケージ70は、図15に示す配線基板10と、半導体チップ71と、アンダーフィル樹脂75とを有する。
続いて、第5の実施の形態に係る半導体パッケージの製造方法について説明する。図39及び図40は、第5の実施の形態に係る半導体パッケージの製造工程を例示する図である。図39及び図40において、図38と同一部品については、同一符号を付し、その説明は省略する場合がある。
第6の実施の形態では、本発明をビルドアップ配線層を有する配線基板に半導体チップを搭載した半導体パッケージに適用する他の例を示す。第6の実施の形態において、第2の実施の形態と共通する部分についてはその説明を省略し、第2の実施の形態と異なる部分を中心に説明する。
始めに、第6の実施の形態に係る半導体パッケージの構造について説明する。 図41は、第6の実施の形態に係る半導体パッケージを例示する断面図である。図41において、図31と同一部品については、同一符号を付し、その説明は省略する場合がある。図41を参照するに、半導体パッケージ80は、図31に示す配線基板30と、半導体チップ71と、アンダーフィル樹脂75とを有する。
10a、30a、50a、60a 配線基板の一方の面
11、31、51、61 突出金属層
11a、51a 第2金属層
11b、51b 第3金属層
11x、31x、51x、61x 突出部
12a 第1絶縁層
12b 第2絶縁層
12c 第3絶縁層
12x 第1ビアホール
12y 第2ビアホール
12z 第3ビアホール
13a 第1配線層
13b 第2配線層
13c 第3配線層
14 ソルダーレジスト層
14x 開口部
15、35、55、65 はんだバンプ
16、36、56、66 接続端子
17 第4金属層
21 支持体
21a 支持体の一方の面
22、24 レジスト層
23 第1金属層
70、80 半導体パッケージ
71 半導体チップ
72 本体
73 電極パッド
75 アンダーフィル樹脂
L10、L30、L50、L60 突出量
P10、P30、P50、P60 ピッチ
T10 厚さ
φ10、φ30、φ50、φ60 直径
Claims (15)
- 支持体上に、前記支持体の表面を露出する柱状の貫通孔を有する第1金属層を形成する第1金属層形成工程と、
前記柱状の貫通孔から露出する前記支持体の表面及び前記柱状の貫通孔の内壁面を覆うように第2金属層を形成する第2金属層形成工程と、
前記第2金属層上に前記柱状の貫通孔を充填するように第3金属層を形成する第3金属層形成工程と、
前記第3金属層を覆うように前記第1金属層上に絶縁層を形成する絶縁層形成工程と、
前記絶縁層の一方の面に、前記第3金属層と電気的に接続する配線層を形成する配線層形成工程と、
前記支持体及び前記第1金属層を除去し、前記第2金属層及び前記第3金属層を含んで構成され前記絶縁層の他方の面から突出する突出部を形成する突出部形成工程(1)と、を有する配線基板の製造方法。 - 前記突出部形成工程(1)に代えて、前記支持体及び前記第1金属層を除去した後、更に前記第2金属層を除去し、前記第3金属層を含んで構成され前記絶縁層の他方の面から突出する突出部を形成する突出部形成工程(2)を有する請求項1記載の配線基板の製造方法。
- 前記第1金属層形成工程は、
前記支持体上に前記柱状の貫通孔に対応する柱状のレジスト層を形成する第1工程と、
前記支持体上の前記柱状のレジスト層が形成されていない領域に前記第1金属層を形成する第2工程と、
前記柱状のレジスト層を除去する第3工程と、を有する請求項1又は2記載の配線基板の製造方法。 - 前記支持体は導電体であり、前記第1金属層形成工程において、前記第1金属層は、前記支持体を給電層とする電解めっき法により形成される請求項1乃至3の何れか一項記載の配線基板の製造方法。
- 前記支持体は導電体であり、前記第2金属層形成工程において、前記第2金属層は、前記支持体を給電層とする電解めっき法により形成される請求項1乃至4の何れか一項記載の配線基板の製造方法。
- 前記支持体は導電体であり、前記第3金属層形成工程において、前記第3金属層は、前記支持体を給電層とする電解めっき法により形成される請求項1乃至5の何れか一項記載の配線基板の製造方法。
- 前記支持体及び前記第1金属層は同一のエッチング液により除去可能な材料により構成されている請求項1乃至6の何れか一項記載の配線基板の製造方法。
- 前記第2金属層は、前記支持体及び前記第1金属層を除去するエッチング液により除去不可能な材料により構成されている請求項1乃至7の何れか一項記載の配線基板の製造方法。
- 前記第2金属層は、異なる材料からなる複数の金属層が積層された構造を有する請求項1乃至8の何れか一項記載の配線基板の製造方法。
- 請求項1乃至9の何れか一項記載の製造方法で製造された突出部を有する配線基板と、電極パッドを有する半導体チップと、を準備する準備工程と、
前記突出部と前記電極パッドとを対向させるように、前記配線基板上に前記半導体チップを配置する配置工程と、
前記突出部と前記電極パッドとを電気的に接続する接続工程と、を有する半導体パッケージの製造方法。 - 前記配線基板の前記突出部が形成されている面と前記半導体チップとの間に樹脂を充填する樹脂充填工程を更に有する請求項10記載の半導体パッケージの製造方法。
- 絶縁層と、
前記絶縁層の一方の面に形成された配線層と、
前記配線層と電気的に接続され、前記絶縁層の他方の面から突出する柱状の突出部と、を有する配線基板。 - 前記柱状の突出部は、異なる材料からなる複数の金属層が積層された構造を有する請求項12記載の配線基板。
- 請求項12又は13記載の配線基板と、電極パッドを有する半導体チップと、を有し、
前記突出部と前記電極パッドとは電気的に接続されている半導体パッケージ。 - 前記突出部と前記電極パッドとは、前記突出部と前記電極パッドとの対向する面間に形成された略一定厚のはんだ層を介して接続されている請求項14記載の半導体パッケージ。
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US12/755,555 US8458900B2 (en) | 2009-04-16 | 2010-04-07 | Wiring substrate having columnar protruding part |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012114431A (ja) * | 2010-11-23 | 2012-06-14 | Ibiden Co Ltd | 半導体搭載用基板、半導体装置及び半導体装置の製造方法 |
JP2013102062A (ja) * | 2011-11-09 | 2013-05-23 | Ibiden Co Ltd | 半導体実装部材及びその製造方法 |
JP2013118255A (ja) * | 2011-12-02 | 2013-06-13 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法、半導体パッケージ |
JP2015173239A (ja) * | 2014-02-24 | 2015-10-01 | 日立化成株式会社 | バンプ付き配線基板及びその製造方法 |
US9406599B2 (en) | 2014-08-29 | 2016-08-02 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method for manufacturing wiring substrate |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5147779B2 (ja) * | 2009-04-16 | 2013-02-20 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体パッケージの製造方法 |
TWI454320B (zh) * | 2011-08-19 | 2014-10-01 | Jieng Tai Internat Electric Corp | 填補穿孔的方法 |
KR101287742B1 (ko) * | 2011-11-23 | 2013-07-18 | 삼성전기주식회사 | 인쇄 회로 기판 및 그 제조 방법 |
TWI637467B (zh) * | 2012-05-24 | 2018-10-01 | 欣興電子股份有限公司 | 中介基材及其製作方法 |
JP2013247201A (ja) * | 2012-05-24 | 2013-12-09 | Shinko Electric Ind Co Ltd | 配線基板、実装構造、及び配線基板の製造方法 |
US9269681B2 (en) * | 2012-11-16 | 2016-02-23 | Qualcomm Incorporated | Surface finish on trace for a thermal compression flip chip (TCFC) |
US8802504B1 (en) * | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
CN104219867A (zh) * | 2013-05-31 | 2014-12-17 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制作方法 |
US8981842B1 (en) * | 2013-10-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company Limited | Integrated circuit comprising buffer chain |
KR20150064976A (ko) * | 2013-12-04 | 2015-06-12 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US20150195912A1 (en) * | 2014-01-08 | 2015-07-09 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Substrates With Ultra Fine Pitch Flip Chip Bumps |
US9693455B1 (en) * | 2014-03-27 | 2017-06-27 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with plated copper posts and method of manufacture thereof |
US20150279815A1 (en) * | 2014-03-28 | 2015-10-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Substrate Having Conductive Columns |
JP2016021496A (ja) * | 2014-07-15 | 2016-02-04 | イビデン株式会社 | 配線基板及びその製造方法 |
US10001439B2 (en) * | 2014-08-04 | 2018-06-19 | National Institute Of Advanced Industrial Science And Technology | Localized surface plasmon resonance sensing chip and localized surface plasmon resonance sensing system |
TWI562275B (en) * | 2014-11-27 | 2016-12-11 | Advance Process Integrate Technology Ltd | Process of forming waferless interposer |
US9899248B2 (en) * | 2014-12-03 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
US10325853B2 (en) | 2014-12-03 | 2019-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
TWI595810B (zh) * | 2015-05-22 | 2017-08-11 | 欣興電子股份有限公司 | 封裝結構及其製作方法 |
CN106298707B (zh) * | 2015-06-05 | 2019-05-21 | 欣兴电子股份有限公司 | 封装结构及其制作方法 |
US9755030B2 (en) * | 2015-12-17 | 2017-09-05 | International Business Machines Corporation | Method for reduced source and drain contact to gate stack capacitance |
WO2017187747A1 (ja) * | 2016-04-28 | 2017-11-02 | 株式会社村田製作所 | 弾性波装置 |
CN107424973B (zh) * | 2016-05-23 | 2020-01-21 | 凤凰先驱股份有限公司 | 封装基板及其制法 |
JP2018032661A (ja) * | 2016-08-22 | 2018-03-01 | イビデン株式会社 | プリント配線板およびその製造方法 |
CN107872929B (zh) * | 2016-09-27 | 2021-02-05 | 欣兴电子股份有限公司 | 线路板与其制作方法 |
US9922924B1 (en) * | 2016-11-03 | 2018-03-20 | Micron Technology, Inc. | Interposer and semiconductor package |
US9922845B1 (en) * | 2016-11-03 | 2018-03-20 | Micron Technology, Inc. | Semiconductor package and fabrication method thereof |
KR101944997B1 (ko) * | 2017-01-06 | 2019-02-01 | 조인셋 주식회사 | 금속패드 인터페이스 |
TWI644598B (zh) * | 2017-04-21 | 2018-12-11 | 南亞電路板股份有限公司 | 電路板結構及其形成方法 |
TWI643532B (zh) * | 2017-05-04 | 2018-12-01 | 南亞電路板股份有限公司 | 電路板結構及其製造方法 |
US10325842B2 (en) | 2017-09-08 | 2019-06-18 | Advanced Semiconductor Engineering, Inc. | Substrate for packaging a semiconductor device package and a method of manufacturing the same |
US10515889B2 (en) | 2017-10-13 | 2019-12-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
US10163758B1 (en) * | 2017-10-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method for the same |
JP2019140174A (ja) * | 2018-02-07 | 2019-08-22 | イビデン株式会社 | プリント配線板およびプリント配線板の製造方法 |
US10573572B2 (en) | 2018-07-19 | 2020-02-25 | Advanced Semiconductor Engineering, Inc. | Electronic device and method for manufacturing a semiconductor package structure |
KR102530754B1 (ko) * | 2018-08-24 | 2023-05-10 | 삼성전자주식회사 | 재배선층을 갖는 반도체 패키지 제조 방법 |
JP7154913B2 (ja) * | 2018-09-25 | 2022-10-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
US11109481B2 (en) * | 2019-02-15 | 2021-08-31 | Ibiden Co., Ltd. | Method for manufacturing printed wiring board and printed wiring board |
WO2020203724A1 (ja) * | 2019-03-29 | 2020-10-08 | 株式会社村田製作所 | 樹脂多層基板、および樹脂多層基板の製造方法 |
JP2020188209A (ja) * | 2019-05-16 | 2020-11-19 | イビデン株式会社 | プリント配線板とプリント配線板の製造方法 |
WO2021031125A1 (zh) * | 2019-08-20 | 2021-02-25 | 华为技术有限公司 | 线路嵌入式基板、芯片封装结构及基板制备方法 |
CN112885806B (zh) * | 2019-11-29 | 2022-03-08 | 长鑫存储技术有限公司 | 基板及其制备方法、芯片封装结构及其封装方法 |
JP2021093417A (ja) * | 2019-12-09 | 2021-06-17 | イビデン株式会社 | プリント配線板、及び、プリント配線板の製造方法 |
JP2021132068A (ja) * | 2020-02-18 | 2021-09-09 | イビデン株式会社 | プリント配線板、プリント配線板の製造方法 |
KR20220009193A (ko) * | 2020-07-15 | 2022-01-24 | 삼성전자주식회사 | 반도체 패키지 장치 |
US20220199427A1 (en) * | 2020-12-23 | 2022-06-23 | Intel Corporation | Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors |
US20220312591A1 (en) * | 2021-03-26 | 2022-09-29 | Juniper Networks, Inc. | Substrate with conductive pads and conductive layers |
US20230187400A1 (en) * | 2021-12-13 | 2023-06-15 | Amkor Technology Singapore Holding Pte. Ltd. | Electronic devices and methods of manufacturing electronic devices |
CN117794104A (zh) * | 2022-09-21 | 2024-03-29 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008177619A (ja) * | 2008-04-11 | 2008-07-31 | Toppan Printing Co Ltd | チップキャリア及び半導体装置並びにチップキャリアの製造方法 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3968193A (en) * | 1971-08-27 | 1976-07-06 | International Business Machines Corporation | Firing process for forming a multilayer glass-metal module |
US4240198A (en) * | 1979-02-21 | 1980-12-23 | International Telephone And Telegraph Corporation | Method of making conductive elastomer connector |
US5054192A (en) * | 1987-05-21 | 1991-10-08 | Cray Computer Corporation | Lead bonding of chips to circuit boards and circuit boards to circuit boards |
US4847136A (en) * | 1988-03-21 | 1989-07-11 | Hughes Aircraft Company | Thermal expansion mismatch forgivable printed wiring board for ceramic leadless chip carrier |
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
US5334804A (en) * | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
JPH08236654A (ja) * | 1995-02-23 | 1996-09-13 | Matsushita Electric Ind Co Ltd | チップキャリアとその製造方法 |
US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
US5900674A (en) * | 1996-12-23 | 1999-05-04 | General Electric Company | Interface structures for electronic devices |
US6002168A (en) * | 1997-11-25 | 1999-12-14 | Tessera, Inc. | Microelectronic component with rigid interposer |
US6057600A (en) * | 1997-11-27 | 2000-05-02 | Kyocera Corporation | Structure for mounting a high-frequency package |
US6054772A (en) * | 1998-04-29 | 2000-04-25 | National Semiconductor Corporation | Chip sized package |
JP3825181B2 (ja) * | 1998-08-20 | 2006-09-20 | 沖電気工業株式会社 | 半導体装置の製造方法及び半導体装置 |
US6329713B1 (en) * | 1998-10-21 | 2001-12-11 | International Business Machines Corporation | Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate |
IL128200A (en) * | 1999-01-24 | 2003-11-23 | Amitec Advanced Multilayer Int | Chip carrier substrate |
JP3973340B2 (ja) | 1999-10-05 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置、配線基板、及び、それらの製造方法 |
JP2001144204A (ja) * | 1999-11-16 | 2001-05-25 | Nec Corp | 半導体装置及びその製造方法 |
JP3629178B2 (ja) * | 2000-02-21 | 2005-03-16 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置及びその製造方法 |
US6441479B1 (en) * | 2000-03-02 | 2002-08-27 | Micron Technology, Inc. | System-on-a-chip with multi-layered metallized through-hole interconnection |
JP3677429B2 (ja) * | 2000-03-09 | 2005-08-03 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置の製造方法 |
DE10031204A1 (de) * | 2000-06-27 | 2002-01-17 | Infineon Technologies Ag | Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile |
JP3653452B2 (ja) | 2000-07-31 | 2005-05-25 | 株式会社ノース | 配線回路基板とその製造方法と半導体集積回路装置とその製造方法 |
JP2002111185A (ja) * | 2000-10-03 | 2002-04-12 | Sony Chem Corp | バンプ付き配線回路基板及びその製造方法 |
JP3546961B2 (ja) | 2000-10-18 | 2004-07-28 | 日本電気株式会社 | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
US6673653B2 (en) * | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
JP3875867B2 (ja) * | 2001-10-15 | 2007-01-31 | 新光電気工業株式会社 | シリコン基板の穴形成方法 |
JP3874669B2 (ja) | 2002-01-25 | 2007-01-31 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
JP4268434B2 (ja) * | 2003-04-09 | 2009-05-27 | 大日本印刷株式会社 | 配線基板の製造方法 |
JP4708148B2 (ja) * | 2005-10-07 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2007165513A (ja) * | 2005-12-13 | 2007-06-28 | Shinko Electric Ind Co Ltd | 半導体装置用の多層配線基板の製造方法及び半導体装置の製造方法 |
KR100782798B1 (ko) * | 2006-02-22 | 2007-12-05 | 삼성전기주식회사 | 기판 패키지 및 그 제조 방법 |
JP2008091639A (ja) * | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | 電子装置およびその製造方法 |
KR100832651B1 (ko) * | 2007-06-20 | 2008-05-27 | 삼성전기주식회사 | 인쇄회로기판 |
US20090056998A1 (en) * | 2007-08-31 | 2009-03-05 | International Business Machines Corporation | Methods for manufacturing a semi-buried via and articles comprising the same |
KR100992181B1 (ko) * | 2007-12-26 | 2010-11-04 | 삼성전기주식회사 | 패키지용 기판 및 그 제조방법 |
KR20100065691A (ko) | 2008-12-08 | 2010-06-17 | 삼성전기주식회사 | 금속범프를 갖는 인쇄회로기판 및 그 제조방법 |
JP5147779B2 (ja) * | 2009-04-16 | 2013-02-20 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体パッケージの製造方法 |
-
2009
- 2009-04-16 JP JP2009099989A patent/JP5147779B2/ja active Active
-
2010
- 2010-04-07 US US12/755,555 patent/US8458900B2/en active Active
- 2010-04-12 TW TW99111229A patent/TWI472283B/zh active
- 2010-04-15 KR KR1020100034673A patent/KR101709629B1/ko active IP Right Grant
-
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- 2013-05-13 US US13/892,416 patent/US9018538B2/en active Active
-
2015
- 2015-03-31 US US14/673,981 patent/US20150206833A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008177619A (ja) * | 2008-04-11 | 2008-07-31 | Toppan Printing Co Ltd | チップキャリア及び半導体装置並びにチップキャリアの製造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012114431A (ja) * | 2010-11-23 | 2012-06-14 | Ibiden Co Ltd | 半導体搭載用基板、半導体装置及び半導体装置の製造方法 |
JP2013102062A (ja) * | 2011-11-09 | 2013-05-23 | Ibiden Co Ltd | 半導体実装部材及びその製造方法 |
JP2013118255A (ja) * | 2011-12-02 | 2013-06-13 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法、半導体パッケージ |
JP2015173239A (ja) * | 2014-02-24 | 2015-10-01 | 日立化成株式会社 | バンプ付き配線基板及びその製造方法 |
US9406599B2 (en) | 2014-08-29 | 2016-08-02 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method for manufacturing wiring substrate |
US9515018B2 (en) | 2014-08-29 | 2016-12-06 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method for manufacturing wiring substrate |
Also Published As
Publication number | Publication date |
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US20150206833A1 (en) | 2015-07-23 |
KR20100114845A (ko) | 2010-10-26 |
TWI472283B (zh) | 2015-02-01 |
US20100263923A1 (en) | 2010-10-21 |
JP5147779B2 (ja) | 2013-02-20 |
KR101709629B1 (ko) | 2017-02-23 |
US8458900B2 (en) | 2013-06-11 |
US9018538B2 (en) | 2015-04-28 |
TW201041472A (en) | 2010-11-16 |
US20130250533A1 (en) | 2013-09-26 |
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