ITMI910351A0 - Cella dram avente una struttura sagomata a tunnel e procedimento di formazione di essa - Google Patents
Cella dram avente una struttura sagomata a tunnel e procedimento di formazione di essaInfo
- Publication number
- ITMI910351A0 ITMI910351A0 IT91MI351A ITMI910351A ITMI910351A0 IT MI910351 A0 ITMI910351 A0 IT MI910351A0 IT 91MI351 A IT91MI351 A IT 91MI351A IT MI910351 A ITMI910351 A IT MI910351A IT MI910351 A0 ITMI910351 A0 IT MI910351A0
- Authority
- IT
- Italy
- Prior art keywords
- tunnel
- procedure
- forming
- shaped structure
- dram cell
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900017706A KR930005741B1 (ko) | 1990-11-01 | 1990-11-01 | 터널구조의 디램 셀 및 그의 제조방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI910351A0 true ITMI910351A0 (it) | 1991-02-12 |
| ITMI910351A1 ITMI910351A1 (it) | 1992-08-12 |
| IT1245152B IT1245152B (it) | 1994-09-13 |
Family
ID=19305570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI910351A IT1245152B (it) | 1990-11-01 | 1991-02-12 | Cella dram avente una struttura sagomata a tunnel e procedimento di formazione di essa |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5262663A (it) |
| JP (1) | JPH0831572B2 (it) |
| KR (1) | KR930005741B1 (it) |
| DE (1) | DE4101940A1 (it) |
| FR (1) | FR2668856B1 (it) |
| GB (1) | GB2249429A (it) |
| IT (1) | IT1245152B (it) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930015002A (ko) * | 1991-12-18 | 1993-07-23 | 김광호 | 반도체 메모리 장치 및 그 제조방법 |
| KR960003498B1 (ko) * | 1992-06-18 | 1996-03-14 | 금성일렉트론주식회사 | 반도체장치의 캐패시터 제조방법 |
| KR950002202B1 (ko) * | 1992-07-01 | 1995-03-14 | 현대전자산업주식회사 | 적층 박막 트랜지스터 제조방법 |
| JP3703885B2 (ja) | 1995-09-29 | 2005-10-05 | 株式会社東芝 | 半導体記憶装置とその製造方法 |
| KR100289749B1 (ko) * | 1998-05-12 | 2001-05-15 | 윤종용 | 도전패드형성방법 |
| US6211036B1 (en) | 1998-09-04 | 2001-04-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an improved capacitor structure, and a method of manufacturing the same |
| JP4711063B2 (ja) * | 2005-09-21 | 2011-06-29 | セイコーエプソン株式会社 | 半導体装置 |
| US10079290B2 (en) * | 2016-12-30 | 2018-09-18 | United Microelectronics Corp. | Semiconductor device having asymmetric spacer structures |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920005632B1 (ko) * | 1987-03-20 | 1992-07-10 | 가부시기가이샤 히다찌세이사꾸쇼 | 다층 산화 실리콘 질화 실리콘 유전체의 반도체장치 및 그의 제조방법 |
| JPH06105770B2 (ja) * | 1988-02-04 | 1994-12-21 | 日本電気株式会社 | ダイナミック型半導体記憶装置 |
| JPH01302852A (ja) * | 1988-05-31 | 1989-12-06 | Fujitsu Ltd | 半導体メモリのメモリセル構造 |
| JP2742271B2 (ja) * | 1988-09-30 | 1998-04-22 | 株式会社日立製作所 | 半導体記憶装置及びその製造方法 |
| JPH0294471A (ja) * | 1988-09-30 | 1990-04-05 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
| JP2586182B2 (ja) * | 1989-05-31 | 1997-02-26 | 日本電気株式会社 | 半導体メモリセルおよびその製造方法 |
-
1990
- 1990-11-01 KR KR1019900017706A patent/KR930005741B1/ko not_active IP Right Cessation
- 1990-12-28 US US07/635,731 patent/US5262663A/en not_active Expired - Lifetime
-
1991
- 1991-01-15 GB GB9100820A patent/GB2249429A/en not_active Withdrawn
- 1991-01-21 DE DE4101940A patent/DE4101940A1/de not_active Ceased
- 1991-02-01 FR FR9101187A patent/FR2668856B1/fr not_active Expired - Fee Related
- 1991-02-12 IT ITMI910351A patent/IT1245152B/it active IP Right Grant
- 1991-08-27 JP JP3238883A patent/JPH0831572B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065802A (ja) | 1994-01-14 |
| US5262663A (en) | 1993-11-16 |
| DE4101940A1 (de) | 1992-05-07 |
| GB2249429A (en) | 1992-05-06 |
| IT1245152B (it) | 1994-09-13 |
| ITMI910351A1 (it) | 1992-08-12 |
| FR2668856A1 (fr) | 1992-05-07 |
| GB9100820D0 (en) | 1991-02-27 |
| JPH0831572B2 (ja) | 1996-03-27 |
| KR930005741B1 (ko) | 1993-06-24 |
| KR920010909A (ko) | 1992-06-27 |
| FR2668856B1 (fr) | 1997-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970225 |