EP1145324A2 - Structure de transistor mos comprenant une electrode de grille de tranchee et presentant une resistance d'enclenchement specifique reduite, et procede de production d'une structure de transistor mos - Google Patents

Structure de transistor mos comprenant une electrode de grille de tranchee et presentant une resistance d'enclenchement specifique reduite, et procede de production d'une structure de transistor mos

Info

Publication number
EP1145324A2
EP1145324A2 EP00920348A EP00920348A EP1145324A2 EP 1145324 A2 EP1145324 A2 EP 1145324A2 EP 00920348 A EP00920348 A EP 00920348A EP 00920348 A EP00920348 A EP 00920348A EP 1145324 A2 EP1145324 A2 EP 1145324A2
Authority
EP
European Patent Office
Prior art keywords
region
layer
regions
transistor structure
doping concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00920348A
Other languages
German (de)
English (en)
Other versions
EP1145324A3 (fr
Inventor
Franz Hirler
Wolfgang Werner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1145324A2 publication Critical patent/EP1145324A2/fr
Publication of EP1145324A3 publication Critical patent/EP1145324A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • MOS transistor structure with a trench gate electrode and a reduced specific on-resistance and method for producing a MOS transistor structure
  • the present invention relates to a MOS transistor structure with a trench gate electrode and a reduced on-resistance. It is an important goal in the development of MOS transistor structures, in particular for power transistors, to achieve a reduction in the specific on resistance of the transistor structure. On the one hand, the static power loss can be minimized, on the other hand, higher current densities can be achieved, which means that smaller and cheaper semiconductor components can be used for the same total current.
  • a known method of reducing the specific on-resistance is to use a transistor structure which has a trench gate electrode instead of a planar transistor structure.
  • the disadvantage of such transistor structures is the occurrence of electrical field peaks in the vicinity of the gate oxide of the trench electrodes, which damage the gate oxide if the source-drain voltages are too high due to avalanche in the adjacent silicon and injection of hot charge carriers and lead to the destruction of the component .
  • a remedy for this problem known from the prior art is an expansion of the body region to ' below the trench gate electrode into the transistor structure.
  • Such an arrangement is shown in FIG. 1 and can be found, for example, in WO 98/04004 or in US Pat. No. 5,525,821. It can also be provided that, as shown in FIG. 1, a deep diffusion 8 with a higher doping concentration is provided in the body region, so that an avalanche breakthrough occurs in the area of this deep diffusion 8.
  • Regions are envisaged whose loads largely cancel each other out in the event of a blockade.
  • the object of the present invention is therefore to provide a MOS transistor structure with a trench gate electrode, which enables a reduction in the specific on resistance in a simple and effective manner.
  • the MOS transistor structures according to the invention each have a highly doped substrate layer of the first conductivity type, which defines a first surface of the transistor structure.
  • a drain metallization is either provided directly on this first surface, or in the case of an IGBT it can be in In this area, an anode zone can also be provided, on which the corresponding metallization is then applied.
  • a body region of the second conductivity type extends into a from a second surface of the transistor structure
  • a source region of the first conduction type is embedded in this body region, which also extends from the second surface into the body region.
  • a gate electrode extends from the second surface of the transistor structure into the transistor structure, which is arranged in a trench which is lined with a gate oxide.
  • the trench has a depth that is less than the depth of the body region.
  • drift region of the first conduction type is provided which adjoins the bottom of the trench and which extends to the substrate layer.
  • This drift region can have a lateral extent, in particular in the region of the highly doped substrate layer, which is greater than the lateral extent of the trench of the gate electrode.
  • the integral of the doping concentration of the body region in the lateral direction between two adjacent drift regions is greater than or equal to the integral of the doping concentration in a drift region in the same lateral direction.
  • the solutions according to the invention prevent an avalanche breakthrough in the region of the trench gate electrode, a structure being provided at the same time, the structure size of which can largely be varied freely.
  • There is practically no obstacle to downsizing the transistor structures as a result of which an increase in the channel width per area and thus a reduction in the specific switch-on resistance can be achieved.
  • higher doping of the body region and the drift region is possible, since the two regions largely clear each other out in the event of a blockage and thus a largely intrinsic area arises that can effectively absorb reverse voltages.
  • the increased doping concentration comes into play, which results in a higher conductivity.
  • the integral of the doping concentration of the body region in the lateral direction is equal to the integral of the doping concentration in the adjacent drift region in the same lateral direction.
  • a practically complete mutual clearing of the two areas is achieved in the event of a blockage.
  • the integral of the doping concentration of the body region is chosen to be greater than the integral of the doping concentration in the drift region, then a rest of charge carriers remain in the body region in the event of a block, which can ensure that a possible avalanche breakthrough in the region of the body region and not in the region the trench gate electrode.
  • the present transistor structure is thus constructed much more simply than the structure from the prior art, especially than the structure from US Pat. No. 5,216,275, in which additional structuring of the drift region is still necessary. In the case of the present invention, this is avoided by advantageously adapting the body region itself.
  • the integral of the doping concentration in the body region in the lateral direction is at most 2 ⁇ 10 ⁇ 2 cm -2. This value is usually in the range just below the breakthrough charge, ie the charge in the corresponding body region in which a breakthrough would take place at the pn junction to the adjacent drift region before the area can be completely cleared out. In order to avoid such a breakthrough, the doping concentration is chosen to be correspondingly lower. It can be provided that the body region is formed by an epitaxial layer. The drift region can then take place, for example, by implantation steps, diffusion steps or filling previously formed trenches with semiconductor material. For this purpose, reference is made to the following description of various manufacturing options. The production of doped areas by filling trenches is known in principle from US Pat. No. 5,216,275.
  • the doping concentration of the body region has a gradient.
  • a gradient in the lateral direction and / or a gradient in the vertical direction can be provided in the body region.
  • the doping concentration of the body layer can be varied during the growth.
  • a drift region is only formed after the structuring of gate trenches in the body layer.
  • the doping material is implanted in the body layer in such a way that a drift region arises which extends from the bottom of the gate trench to the highly doped substrate layer. This can be done by a corresponding choice of the geometry and the implantation parameters, or by an out-diffusion of the doping material down to the highly doped substrate layer after the implantation. Alternatively, several implantation steps with different implantation energy can be carried out in order to produce a drift region of the desired extent up to the highly doped substrate layer.
  • the gate trench can be structured in the body layer in such a way that it directly adjoins a source region. However, it can also be provided that the trench is structured into the body layer by a source region, so that the trench automatically adjoins the source region and the body layer.
  • a MOS transistor structure is produced using a construction technique. It happens:
  • the described columnar structures are formed as soon as the first partial layer is grown. However, it can also be provided that one or more partial layers are first grown on the highly doped substrate layer to form a further drift region. It is only when later partial layers are grown that the columnar structures are formed by the provision of the corresponding areas of opposite conduction type in the partial layers. In this case, the entire structure has the
  • Body region a certain distance from the highly doped substrate layer, the two regions being separated from one another by a drift region.
  • This method is somewhat more complex than the first method due to the need for repeated growth of partial layers and the introduction of doped regions into the partial layers.
  • a more precise doping of the different areas i.e. H. the body region and the drift region, as well as their position and extent in the transistor structure.
  • the first method according to the invention has the advantage that the epitaxial growth enables the body layer to be produced with a relatively precisely defined doping concentration in accordance with the desired specifications, the drift region then being formed by a single or can be generated by several, directly successive implantation sections, possibly with subsequent diffusion.
  • a third method according to the invention for producing a MOS transistor structure has the following steps:
  • the body region can thus be generated, for example, by placing an epitaxial layer with a doping of the appropriate conductivity type on the highly doped substrate layer, or possibly on a drift region that is on the highly doped S u b strat harsh was provided, is grown.
  • the drift region is then formed by structuring trenches and filling them with semiconductor material.
  • the gate trenches can then be formed, for example, using the same mask with which the trenches for the drift region were produced, insofar as the tolerances for a renewed application of this common mask permit this. In the ideal case, an additional mask for structuring the gate trenches can thus be saved.
  • the doping concentration of the body regions and of the drift regions is set such that the integral of the doping concentration in a drift region in the lateral direction between two adjacent body regions is less than or equal to the integral of the doping concentration of the body region in the same lateral direction.
  • the integral of the doping concentration in a body region in the lateral direction is preferably limited to a maximum of 2 ⁇ 10 ⁇ 2 cm ⁇ 2.
  • the doping concentration of the body regions is set in such a way that they have a gradient in the vertical and / or lateral direction.
  • Figure 1 transistor arrangement with deep diffusion in the body region according to the prior art.
  • Figure 2 Transistor arrangement with an epitaxial layer as a body layer and implanted drift regions under the gate trenches.
  • Figure 3 Schematic representation of a transistor arrangement with body regions that extend to the highly doped substrate layer.
  • Figure 4 Arrangement according to Figure 3, wherein a drift region is provided between the body regions and the substrate layer.
  • Figure 5 Representation of the manufacturing steps of a transistor structure with implantation of doping material through the bottom of the gate trenches.
  • Figure 6 Manufacture of a MOS transistor arrangement by filling trenches in a body layer with semiconductor material of opposite conductivity type.
  • FIG. 7 Production of a transistor arrangement in the construction technology by successive growth of partial layers and introduction of doping material of opposite conductivity type into the partial layers.
  • FIG. 1 shows a MOS transistor arrangement according to the prior art.
  • a highly doped n + substrate layer 2 defines a first surface 21 of the transistor arrangement.
  • a drain metallization 1 is applied to this first surface 21.
  • An n ⁇ drift region 6 is arranged above the heavily doped substrate layer 2.
  • N + source regions 10 have diffused into the body region 9.
  • the Body region 9 and source regions 10 extend from a second surface 3 of the MOS transistor arrangement into the transistor structure.
  • gate electrodes 5, which are surrounded by a gate oxide 4 and are arranged in a gate trench, extend from the second surface 3 into the transistor structure.
  • An oxide layer 12 covers the gate electrodes 5 and parts of the source regions 10.
  • a metallization 13 serves to contact the source regions 10 and the body region 9.
  • FIG. 2 shows an exemplary embodiment of a transistor structure according to the invention, the body region 9 being formed by an epitaxial layer. As shown in FIG. 2, this can have a gradient with respect to its doping concentration. Thus, a lower portion of the body layer is formed having a p ⁇ -doping, and an upper portion 7 of the body layer having a higher p-doping, which serves to adjust the threshold voltage in the channel region of the transistor structure.
  • the body layer 9 borders directly on the highly doped n + -
  • the n ⁇ drift region 6 is formed only by implanted regions below the gate electrode 5.
  • the doping concentration of the body layer 9 and the drift region 6 are adjusted so that the lateral integral of the doping concentration of the body layer 9 between two drift regions 6 is greater than or equal to the integral of the doping concentration in a drift region 6 in the same lateral direction.
  • the integral of the doping concentration is a maximum of 2 x 10 ⁇ 2 cm ⁇ 2.
  • the body regions 6 and the body regions 9 schematically show two possible arrangements for the drift regions 6 and the body regions 9.
  • the body regions can extend as far as the highly doped n + substrate layer 2 and thus directly adjoin it.
  • the body regions 9 do not extend all the way to the highly doped substrate layer 2, but that the n ⁇ drift region 6 extends on the one hand under the gate electrodes 5, and on the other hand is also arranged between the body regions 9 and the highly doped substrate layer 2.
  • the dashed lines in the drift region 6 are intended to indicate that the areas under the gate electrodes 5 and between the body regions 9 and the heavily doped substrate layer 2 generally have largely uniform doping.
  • a slightly different doping concentration is selected under the gate electrodes than in the region which adjoins the highly doped substrate layer.
  • FIG. 5 shows in steps a to d the production of a transistor structure, the formation of the drift region 6 under the gate electrodes 5 by implantation of doping material through the bottom of the gate trenches 14.
  • a p-body layer 9 is first provided on a highly doped n + substrate layer 2. It can also be provided, as shown in FIG. 5a, that a first drift region 6 is already arranged between the body layer 9 and the substrate layer 2. The formation of n + source regions 10 in the region of the second surface 3 of the transistor structure can also take place in this step.
  • the gate trenches 14 are then structured into the p-body layer 9.
  • the areas of the body layer that are not to be structured are covered by a mask, for example made of an oxide layer 16 and a nitride layer 15.
  • the n-doping material is then implanted through the bottoms of the gate trenches 14 into the p-body layer 9.
  • n-doped regions 17 are formed in the p-body layer 9.
  • these n-regions 17 can already extend to the drift region 6.
  • the n regions 17 are expanded by a subsequent diffusion step.
  • the n regions 17 enlarged in this way then merge, as shown in FIG. 5d, into the drift region 6 arranged under the p-body layer 9.
  • the gate trenches can then be filled with a gate oxide 4 and a gate electrode 5 to complete the transistor structure.
  • the oxide layer 12 is arranged over the gate electrode and the metallization 13 over the source regions 10 and the body layer 9.
  • FIG. 5d clearly shows, an implantation and, if necessary, a subsequent diffusion can result in the initially continuous body layer 9 being subdivided into individual, separate body regions 9.
  • the separation of the body layer into individual body regions 9 is achieved solely by the implantation of a drift region 6 under the gate electrode 5.
  • FIG. 6 shows the production of a transistor arrangement by filling trenches with semiconductor material.
  • a highly doped substrate layer 2, a drift region 6, and a p-body layer 9 arranged above it, possibly already source regions 10, are provided.
  • the provision of an n-drift region 6 according to FIG. 6a can also be dispensed with.
  • trenches 18 are first structured into the p-body layer 9, so that the body layer 9 is subdivided into individual body regions 9.
  • a mask made of silicon oxide 16 and silicon nitride 15 can be used for this purpose.
  • the trenches 18 are then filled with n-doped semiconductor material 19, which completely lines the trenches 18 and also covers the surface 3 of the transistor structure.
  • the semiconductor material 19 is etched back in the area of the surface 3 to such an extent that the body regions 9 come to the surface 3 again.
  • the gate trenches 14 are then structured into the drift regions 6 between the body regions 9, the gate trenches 14 having a smaller depth than the trenches 19 which were previously structured to form the drift regions 6 between the body regions 9.
  • the same mask can ideally be used that was previously used to form the trenches 19.
  • FIG. 6e shows the finished transistor structure after filling the gate trenches 14 with a gate oxide 4 and a gate electrode 5, and after attaching the oxide layer 12 and the metallization 13.
  • FIG. 7 shows the production of a transistor arrangement in a packaging technique, successive epitaxial sublayers 20 being grown on a highly doped substrate layer 2.
  • Figures 7e and 7f show an alternative to Figures 7a and 7c.
  • a plurality of p-epitaxial sublayers 20 are grown in succession on a highly doped n + substrate layer 2.
  • n-doped regions 6 are formed in the sub-layers 20. This can be done, for example, by implantation or diffusion.
  • the n-doped regions are arranged in such a way that they form continuous drift regions 6 over several partial layers 20 as column-like structures. In this case, 6 p-body regions 9, which likewise have a columnar structure, are automatically formed between these drift regions.
  • FIG. 7b Such an arrangement after The growth of all sub-layers 20 is shown in FIG. 7b.
  • the last of the sub-layers forms the second surface 3 of the transistor structure.
  • n + source regions 10 are subsequently formed in the p-body regions 9, and gate trenches 14 are structured in the drift regions 6, so that the gate trenches 14 each have at least one source region 10 and one Border p-body region 9.
  • the gate trenches 14 extend from the second surface 3 of the transistor structure into the transistor structure, but to a lesser depth than the p-body regions 9.
  • a gate oxide 4 and a gate electrode are formed 5 in each of the gate trenches 14. The usual application of the oxide layer 12 and a metallization 13 on the transistor structure can then take place.
  • n-doped epitaxial layers are grown as partial layers. It can be provided that some sub-layers are first produced on the highly doped substrate layer 2, but into which no p-doped regions are diffused. A drift region is thus formed over the n + -doped substrate layer 2. Only after the formation of a certain number of n-doped sublayers is the formation of p-doped regions 9 in the further sublayers 20, as shown in FIG. 7e. The p-doped regions 9 are arranged in such a way that column-like structures result which represent p-body regions 9.
  • n-drift regions 6 which likewise have a columnar structure, as is clear from FIG. 7f.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne une structure de transistor MOS comprenant une électrode de grille de tranchée et présentant une résistance d'enclenchement spécifique réduite, l'intégrale de la concentration de dopage de la région de corps, dans le sens latéral entre deux régions de migration voisines, étant supérieure ou égale à l'intégrale de la concentration de dopage dans une région de migration, dans le même sens latéral. L'invention concerne en outre un procédé de production d'une telle structure de transistor MOS, les régions de corps et les régions de migration étant obtenues par croissance épitaxiale et implantation, croissance épitaxiale répétée ou par remplissage de tranchées avec un matériau conducteur dopé.
EP00920348A 1999-03-24 2000-03-01 Structure de transistor mos comprenant une electrode de grille de tranchee et presentant une resistance d'enclenchement specifique reduite, et procede de production d'une structure de transistor mos Withdrawn EP1145324A3 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19913375 1999-03-24
DE19913375A DE19913375B4 (de) 1999-03-24 1999-03-24 Verfahren zur Herstellung einer MOS-Transistorstruktur
PCT/DE2000/000621 WO2000057481A2 (fr) 1999-03-24 2000-03-01 Structure de transistor mos comprenant une electrode de grille de tranchee et presentant une resistance d'enclenchement specifique reduite, et procede de production d'une structure de transistor mos

Publications (2)

Publication Number Publication Date
EP1145324A2 true EP1145324A2 (fr) 2001-10-17
EP1145324A3 EP1145324A3 (fr) 2001-10-24

Family

ID=7902261

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00920348A Withdrawn EP1145324A3 (fr) 1999-03-24 2000-03-01 Structure de transistor mos comprenant une electrode de grille de tranchee et presentant une resistance d'enclenchement specifique reduite, et procede de production d'une structure de transistor mos

Country Status (5)

Country Link
US (1) US6465843B1 (fr)
EP (1) EP1145324A3 (fr)
JP (1) JP2002540603A (fr)
DE (1) DE19913375B4 (fr)
WO (1) WO2000057481A2 (fr)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210823A (ja) * 2000-01-21 2001-08-03 Denso Corp 半導体装置
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
JP4932088B2 (ja) * 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
US7291884B2 (en) * 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7009247B2 (en) * 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US6569738B2 (en) * 2001-07-03 2003-05-27 Siliconix, Inc. Process for manufacturing trench gated MOSFET having drain/drift region
US7033876B2 (en) 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US20060038223A1 (en) * 2001-07-03 2006-02-23 Siliconix Incorporated Trench MOSFET having drain-drift region comprising stack of implanted regions
US6849898B2 (en) 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
US6764906B2 (en) * 2001-07-03 2004-07-20 Siliconix Incorporated Method for making trench mosfet having implanted drain-drift region
DE10239862B4 (de) * 2002-08-29 2007-03-15 Infineon Technologies Ag Trench-Transistorzelle, Transistoranordnung und Verfahren zur Herstellung einer Transistoranordnung
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
JP5299373B2 (ja) * 2003-01-16 2013-09-25 富士電機株式会社 半導体素子
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7166890B2 (en) 2003-10-21 2007-01-23 Srikant Sridevan Superjunction device with improved ruggedness
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
DE102004009323B4 (de) * 2004-02-26 2017-02-16 Infineon Technologies Ag Vertikaler DMOS-Transistor mit Grabenstruktur und Verfahren zu seiner Herstellung
WO2005084221A2 (fr) * 2004-03-01 2005-09-15 International Rectifier Corporation Structure de contact auto-alignee pour dispositif a tranchees
TWI256676B (en) * 2004-03-26 2006-06-11 Siliconix Inc Termination for trench MIS device having implanted drain-drift region
US7045857B2 (en) * 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
DE102005012117B4 (de) * 2005-03-16 2008-10-16 Infineon Technologies Austria Ag Transistorbauelement
JP2006269720A (ja) * 2005-03-24 2006-10-05 Toshiba Corp 半導体素子及びその製造方法
CN102867825B (zh) 2005-04-06 2016-04-06 飞兆半导体公司 沟栅场效应晶体管结构及其形成方法
WO2006135746A2 (fr) 2005-06-10 2006-12-21 Fairchild Semiconductor Corporation Transistor à effet de champ à équilibrage de charge
US7492003B2 (en) * 2006-01-24 2009-02-17 Siliconix Technology C. V. Superjunction power semiconductor device
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US20090053869A1 (en) * 2007-08-22 2009-02-26 Infineon Technologies Austria Ag Method for producing an integrated circuit including a trench transistor and integrated circuit
JP2010541212A (ja) 2007-09-21 2010-12-24 フェアチャイルド・セミコンダクター・コーポレーション 電力デバイスのための超接合構造及び製造方法
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
JP5298565B2 (ja) * 2008-02-22 2013-09-25 富士電機株式会社 半導体装置およびその製造方法
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
JP5216801B2 (ja) 2010-03-24 2013-06-19 株式会社東芝 半導体装置
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
CN102468169A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 Umos晶体管及其形成方法
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
JP2014518017A (ja) 2011-05-18 2014-07-24 ビシャイ‐シリコニックス 半導体デバイス
CN102412266B (zh) * 2011-10-13 2014-12-10 上海华虹宏力半导体制造有限公司 提高soa能力的功率器件结构及其制造方法
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
CN105632931B (zh) 2014-11-04 2020-04-28 台湾积体电路制造股份有限公司 半导体器件的制造方法及半导体器件
JP6032337B1 (ja) 2015-09-28 2016-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4906588A (en) * 1988-06-23 1990-03-06 Dallas Semiconductor Corporation Enclosed buried channel transistor
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
CN1019720B (zh) * 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
JPH0621468A (ja) * 1992-06-29 1994-01-28 Toshiba Corp 絶縁ゲート型半導体装置
JP2837033B2 (ja) * 1992-07-21 1998-12-14 三菱電機株式会社 半導体装置及びその製造方法
US5410170A (en) * 1993-04-14 1995-04-25 Siliconix Incorporated DMOS power transistors with reduced number of contacts using integrated body-source connections
US6001678A (en) * 1995-03-14 1999-12-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
KR100199997B1 (ko) * 1995-09-06 1999-07-01 오카메 히로무 탄화규소 반도체장치
US5637898A (en) * 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
WO1997029518A1 (fr) * 1996-02-05 1997-08-14 Siemens Aktiengesellschaft Composant semi-conducteur commande par effet de champ
DE69739206D1 (de) * 1996-07-19 2009-02-26 Siliconix Inc Hochdichte-graben-dmos-transistor mit grabenbodemimplantierung
JP3938964B2 (ja) * 1997-02-10 2007-06-27 三菱電機株式会社 高耐圧半導体装置およびその製造方法
JP3915180B2 (ja) * 1997-07-03 2007-05-16 富士電機デバイステクノロジー株式会社 トレンチ型ｍｏｓ半導体装置およびその製造方法
DE19808182C1 (de) * 1998-02-26 1999-08-12 Siemens Ag Elektrisch programmierbare Speicherzellenanordnung und ein Verfahren zu deren Herstellung
KR100275756B1 (ko) * 1998-08-27 2000-12-15 김덕중 트렌치 절연 게이트 바이폴라 트랜지스터
DE19908809B4 (de) * 1999-03-01 2007-02-01 Infineon Technologies Ag Verfahren zur Herstellung einer MOS-Transistorstruktur mit einstellbarer Schwellspannung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0057481A2 *

Also Published As

Publication number Publication date
DE19913375A1 (de) 2000-10-05
US6465843B1 (en) 2002-10-15
WO2000057481A2 (fr) 2000-09-28
EP1145324A3 (fr) 2001-10-24
DE19913375B4 (de) 2009-03-26
WO2000057481A3 (fr) 2001-07-26
JP2002540603A (ja) 2002-11-26

Similar Documents

Publication Publication Date Title
DE19913375B4 (de) Verfahren zur Herstellung einer MOS-Transistorstruktur
DE112016003510B4 (de) HALBLEITERVORRlCHTUNG UND VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG
DE19839970C2 (de) Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung
DE102008039845B4 (de) IGBT mit einem Halbleiterkörper
DE10106006B4 (de) SJ-Halbleiterbauelement und Verfahren zu dessen Herstellung
DE102006036347B4 (de) Halbleiterbauelement mit einer platzsparenden Randstruktur
DE102009038731B4 (de) Halbleiterbauelement mit Ladungsträgerkompensationsstruktur und Verfahren zur Herstellung eines Halbleiterbauelements
DE60125784T2 (de) Graben-mosfet-struktur mit geringer gate-ladung
DE10161129B4 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
EP1160871B1 (fr) Dispositif semi-conducteur à compensation de charge et sa méthode de fabrication
DE102008023519B4 (de) Halbleiterbauteil mit isolierter Steuerelektrode und Verfahren zu seiner Herstellung
EP1190447B1 (fr) Transistor mos a tranchee
DE102007030755B3 (de) Halbleiterbauelement mit einem einen Graben aufweisenden Randabschluss und Verfahren zur Herstellung eines Randabschlusses
DE69735349T2 (de) Graben-dmos-transistor mit leichtdotierter wanne
DE102008044408B4 (de) Halbleiterbauelementanordnung mit niedrigem Einschaltwiderstand
DE10239815B4 (de) Insulated-Gate-Halbleiterbauelement und Verfahren zur Herstellung von diesem
DE102004022199B4 (de) Chip einer Halbleiteranordnung
DE102005004355B4 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE102017107174B4 (de) IGBT mit dV/dt-Steuerbarkeit und Verfahren zum Verarbeiten eines IGBT
DE10041344A1 (de) SJ-Halbleitervorrichtung
DE102009002813B4 (de) Verfahren zur Herstellung eines Transistorbauelements mit einer Feldplatte
DE102004041198B4 (de) Laterales Halbleiterbauelement mit einer Feldelektrode und einer Entladestruktur
WO1999056321A1 (fr) Transistor lateral haute tension de paroi laterale
DE112018007354T5 (de) Siliciumcarbid-halbleitereinheit und herstellungsverfahren für dieselbe
EP0913000A1 (fr) Composant a semiconducteur pouvant etre commande par effet de champ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAK Availability of information related to the publication of the international search report

Free format text: ORIGINAL CODE: 0009015

17P Request for examination filed

Effective date: 20010111

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

XX Miscellaneous (additional remarks)

Free format text: DERZEIT SIND DIE WIPO-PUBLIKATIONSDATEN A3 NICHT VERFUEGBAR.

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20031002

RBV Designated contracting states (corrected)

Designated state(s): AT DE FR GB IE IT