CN1808711A - 封装体及封装体模块 - Google Patents
封装体及封装体模块 Download PDFInfo
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Abstract
本发明提供一种封装体,其包含一承载器、一第一芯片、一第一介电层以及至少一第一导通结构。其中,承载器具有一第一表面与一第二表面,第二表面设置至少一第一接合垫;第一芯片设置第一表面上;第一介电层设置于第一表面,并包覆第一芯片;第一导通结构位于第一介电层之中及沿着第一芯片周缘设置,以将第一芯片与第一接合垫电性连结。
Description
背景技术
本发明关于一种封装体及封装体模块,特别关于一种传输路径较短的封装体及封装体模块。
技术领域
随着科技进步,对封装体与封装体模块的功能与尺寸限制的要求也相对提高,由此可见,封装体与封装体模块在尺寸体积要求轻薄短小的情况下,随着传输讯号的增加,其内部线路与接合垫的设计,不但要避免线路间彼此电性干扰的问题,更要求具有配置容易、布线简单的功能。
一般来说,封装体具有一芯片设置于一承载器,芯片与承载器的电性连结大致三种方式。第一种为丝焊或引线键合(wire bonding),利用多个金线将芯片与承载器电性连接,然而,金线本身容易造成阻抗不匹配的问题,且封装时金线间的距离不易控制,造成干扰甚至短路而影响封装体的性能。第二种为覆晶封装或倒装片封装(flip chippackage),于多个芯片垫上分别设置凸块(solder bump),再通过凸块与承载器机械及电性连结,但回焊凸块与芯片封装的过程,容易造成热应力与芯片毁损的问题。第三种为引脚***型(pin through hole,PTH),于芯片周缘或底面设置多个针状或薄板状的金属引脚,而承载器具有多个对应设置的***脚座(socket)或导电孔(via),用以供芯片的各引脚焊接固定,惟封装体尺寸不易微小化。
因此,本发明提供一种封装体及封装体模块,其具有传输路径较短、电性较佳、布线简单与工艺容易的优点,以解决上述问题。
发明内容
鉴于上述问题,本发明的目的为提供一种封装体及封装体模块,其具有传输路径较短、电性较佳、布线简单与工艺容易的优点。
缘是,为达上述目的,依据本发明的一种封装体包含一承载器、一第一芯片、一第一介电层以及至少一第一导通结构。其中,承载器具有一第一表面与一第二表面,第二表面设置至少一第一接合垫或焊盘;第一芯片设置第一表面上;第一介电层设置于第一表面,并包覆第一芯片;第一导通结构位于第一介电层之中及沿着第一芯片周缘设置,以将第一芯片与第一接合垫电性连结。
为达上述目的,依据本发明的一种封装体模块具有多个封装体,其中之一封装体包含一承载器、一第一芯片、一第一介电层以及至少一第一导通结构;承载器具有一第一表面与一第二表面,第二表面设置至少一第一接合垫;第一芯片设置于第一表面上;第一介电层设置于第一表面,并包覆第一芯片;第一导通结构位于第一介电层之中及沿着第一芯片周缘设置,以将第一芯片与第一接合垫电性连结。该封装体更包含至少一第二接合垫配置于第一介电层上且电性连结至第一导通结构。该封装体的第二接合垫更经由一焊球或一凸块连接至另一封装体的第一接合垫。
承上所述,本发明的一种封装体及封装体模块,由于第一导通结构位于第一芯片周缘的较短传输路径设计,使得第一芯片可直接通过第一导通结构与承载器、另一芯片、另一封装体或一线路板电性连结,与习用结构相较,本发明具有较佳的电性导通路径,提高封装弹性,使得布线容易,而有利于封装体与封装体模块的生产制造。
附图说明
图1a与1b为本发明的一种封装体的示意图;
图2为本发明的一种封装体与另一芯片电性连结的示意图;
图3为本发明的一种封装体与另一封装体电性连结的示意图;
图4为本发明的另一种封装体的示意图;
图5为本发明的又一种封装体的示意图;
图6为本发明的一种封装体的制作流程图;
图7为本发明的一种封装体模块的示意图;以及
图8为本发明的另一种封装体模块的示意图。
组件符号说明:
1封装体
2封装体
3封装体
4封装体模块
5封装体模块
11承载器
111第一表面
112第二表面
113第一接合垫
114内部线路
12第一芯片
13第一介电层
14第一导通结构
15第二接合垫
16保护层
17第二介电层
18a第二导通结构
18b第二导通结构
19第二芯片
12a芯片
12b封装体
20焊球
具体实施方式
以下将参照相关图式,说明依据本发明较佳实施例的一种封装体及其制作方法,及一封装体模块。
请参阅图1a与1b,本发明的一种封装体1包含一承载器11、一第一芯片12、一第一介电层13以及至少一第一导通结构14。
承载器11具有一第一表面111与一第二表面112,第二表面112设置至少一第一接合垫113。本实施例中,承载器11可为一基板,其材质可为有机材质、无机材质或陶瓷材质,且承载器11内部具有一内部线路114。当然,承载器11也可为一空白基板,且具有多个通孔,各通孔内填入一导电材质而形成内部线路114。另外,第一接合垫113上更可设置一凸块或焊球(图中未示),使得承载器11可通过第一接合垫113上的凸块或焊球而与一芯片、一封装体或一线路板(图中未示)连结。此外,本发明的承载器11也可为一引线框架(lead frame)。
第一芯片12设置于承载器11的第一表面111上,且第一芯片12可为一芯片组、一处理器、一内存、一通讯芯片或一绘图芯片。
第一介电层13设置于第一表面111,且包覆第一芯片12。至少一第一导通结构14位于第一介电层13之中及沿着第一芯片12周缘设置,以将第一芯片12与第一接合垫113电性连结。
本实施例中,更包含至少一第二接合垫15,其设置于第一介电层13上,且第二接合垫15与第一导通结构14电性连接。第二接合垫15更可经由第一导通结构14电性连接至第一接合垫113。此外,本实施例更包含一保护层16,其设置于第一介电层13上,并暴露出第二接合垫15。藉此,保护层16对承载器11、第一芯片12及第一导通结构14间的电性连接提供一保护作用。
经由第一导通结构14或再配合承载器11的内部线路114,芯片12电性连接至第一接合垫113与第二接合垫15,并以第一接合垫113与第二接合垫15作为本封装体1的电性接点,用以连接至另一芯片、另一封装体、或一线路板。
请参考图2,上述的封装体1的第二接合垫15可经由丝焊方式与一芯片12a电性连接,形成一堆积式多芯片封装体。或如图3的实施例,上述的封装体1的第二接合垫15可经由覆晶接合方式与具有一芯片的封装体12b电性连接,形成一堆积式多封装体模块。
由此可见,本发明的封装体1经由缩短第一芯片12与承载器11、另一芯片12a或另一封装体12b的电性导通路径,因而降低阻抗匹配的问题,确实具有较佳的电性。此外,本发明的封装体还为设计者提供具有弹性的结构与制造方式。
请参阅图4,封装体2具有封装体1的相同结构,更包含一第二介电层17与多个第二导通结构18a。第二介电层17设置于第一介电层13上,第二导通结构18a设置于第二介电层17之中,以将第一芯片12与第一导通结构14电性连结,可再经由第一导通结构14电性连结至第一接合垫113。经由第二导通结构18a可增加芯片12向外界电性连接数目,不受到第一导通结构14布线密度限制。
如图5所示,封装体3,具有封装体1的相同结构,更可包含一第二芯片19。类似于封装体1,第一介电层13包覆第一芯片12上。此外,封装体3更具有第二介电层17,位于第一介电层13上,且包覆第二芯片19。第二导通结构18b是以形成第一导通结构14的工艺所形成。将第二芯片19与第一导通结构14电性连结,形成一个堆积式多芯片封装体。
本发明的封装体并不限定仅具有第一芯片12、第一介电层13层、第二介电层17及第二芯片19,而可依据实际需要利用例如无凸块嵌入式封装技术(bumpless build up layer,BBUL),再继续于第二介电层17上堆栈其它介电层或芯片,而封装体的厚度可限制为0.2mm至0.3mm之间,以符合现今对封装体体积的要求。
请参阅图6,为本发明的一种封装体的制作流程图,首先,于步骤S1,提供一承载器11,承载器11有一第一表面111与一第二表面112,第二表面112设置至少一第一接合垫113。本实施例中,承载器11可为一基板,其材质可为有机材质、无机材质或陶瓷材质,且承载器11内部具有一内部线路114。当然,承载器11可为一空白基板,且具有多个通孔(图中未示)。另外,第一接合垫113上更可设置一凸块或焊球(图中未示)。此外,本发明的承载器11也可为一引线框架。
接着,于步骤S2,配置一第一芯片12于承载器11的第一表面111。第一芯片12可为一芯片组、一处理器、一内存、一通讯芯片或一绘图芯片。
接着,于步骤S3,形成一第一介电层13于第一表面111,并包覆第一芯片12。
接着,于步骤S4,移除部分第一介电层13,以暴露部分第一芯片12与部分邻近于第一芯片12周缘的第一接合垫113。
最后,于步骤S5,填入一导电材质于第一芯片12与第一接合垫113上的暴露部分,形成至少一第一导通结构14,以将第一芯片12与第一接合垫113电性连接。需要补充说明的是,当承载器11为具有多个通孔的空白基板时,在步骤S5或之后,也可同时或接续填入导电材质于各通孔中,而形成一内部线路114于承载器11中。
本实施例中,于步骤S5更可包含形成多个第二接合垫15于第一介电层13上的步骤,且第二接合垫15与第一导通结构14电性连结。第二接合垫15可加设一凸块或焊球(图中未示),使得另一芯片12a(如图2所示)或另一封装体12b(如图3所示)可通过丝焊或覆晶封装的方式与本发明的封装体电性连结。
本实施例中,于步骤S5之后,更可包含形成一保护层16于第一介电层13上的步骤,并暴露第二接合垫15(图中未示)。
请同时参阅图4与图6,本发明的封装体的制作方式更可包含下列步骤以形成一第二介电层17与至少一第二导通结构18a。首先,形成一第二介电层17于第一介电层13上;接着,移除部分第二介电层17,以暴露部分第一芯片12与部分第一导通结构14;最后,填入一导电材质于第一芯片12与第一导通结构14上的暴露部分,形成至少一第二导通结构18a,以将第一芯片12与第一导通结构14电性连结,再经由第一导通结构14与第一接合垫113电性连结。
请同时参阅图5与图6,本发明的封装体的制作方式更包含下列步骤,使得封装体更具有一第二芯片19、第二介电层17及至少一第二导通结构18b。首先,配置一第二芯片19于第一介电层13上;接着,形成一第二介电层17于第一介电层13上,并包覆第二芯片19;接着,移除部分第二介电层17,以暴露部分第二芯片19与部分第一导通结构14;最后,填入一导电材质于第二芯片19与第一导通结构14上的暴露部分,形成至少一第二导通结构18b,以将第二芯片19与第一导通结构14电性连结,再经由第一导通结构14与第一接合垫113电性连结。
如图7所示,本发明还揭露一种封装体模块4具有二相同的封装体1彼此电性连结,其中,封装体1包含一承载器11、一第一芯片12、一第一介电层13、至少一第一导通结构14、至少一第二接合垫15、至少一第一接合垫113及至少一焊球20。上部的封装体1可与下部封装体1的第一导通结构14连结。其中,承载器11、第一芯片12、第一介电层13及第一导通结构14已叙述于前,在此不再赘述。
如图8所示,本发明的另一种封装体模块5具有两个不同封装体2与封装体3相互堆积。其中封装体2具有第一导通结构14与第二导通结构18a作为芯片与外界连接的途径。封装体3具有两个芯片12、19相互堆栈。该封装体3更包含至少一第二接合垫15配置于一第二介电层17上且电性连结至一第二导通结构18b。该封装体3的第二接合垫15更经由一焊球20连接至封装体2的第一接合垫113。
综上所述,本发明的一种封装体及封装体模块,由于第一导通结构位于第一芯片周缘的较短传输路径设计,使得第一芯片可直接通过第一导通结构与承载器、另一芯片、另一封装体或一线路板电性连结,与习用结构相较,本发明具有较佳的电性导通路径,提高封装弹性,使得布线容易,而有利于封装体与封装体模块的生产制造。
以上所述仅为举例性,而非为限制性者。任何未脱离本发明的精神与范畴,而对其进行的等效修改或变更,均应包含于所附的权利要求中。
Claims (15)
1、一种封装体,包含:
一承载器,其具有一第一表面与一第二表面,该第二表面设置至少一第一接合垫;
一第一芯片,其设置于该第一表面上;
一第一介电层,其设置于该第一表面,并包覆该第一芯片;以及
至少一第一导通结构,其位于该第一介电层之中及沿着该第一芯片周缘设置,以将该第一芯片与该第一接合垫电性连结。
2、根据权利要求1所述的封装体,还包含:
至少一第二接合垫,其设置于该第一介电层上。
3、根据权利要求2所述的封装体,其中,该第一接合垫和/或第二接合垫上设置一凸块或焊球。
4、根据权利要求2所述的封装体,其中,该第二接合垫与该第一导通结构电性连结。
5、根据权利要求2所述的封装体,还包含:
一保护层,其设置于该第一介电层上,并暴露出该第二接合垫。
6、根据权利要求2所述的封装体,其中,该第一接合垫和/或该第二接合垫与一芯片、一封装体或一线路板电性连结。
7、根据权利要求1所述的封装体,还包含:
一第二介电层,其设置于该第一介电层上;以及
至少一第二导通结构,其位于该第二介电层之中,以将该第一芯片与该第一导通结构电性连结。
8、根据权利要求1所述的封装体,还包含:
一第二芯片,其设置于该第一介电层上;
一第二介电层,其设置于该第一介电层上,并包覆该第二芯片;以及
至少一第二导通结构,其位于该第二介电层之中,以将该第二芯片与该第一接合垫和/或该第一导通结构电性连结。
9、根据权利要求8所述的封装体,其中,该第二导通结构沿着该第二芯片周缘设置。
10、根据权利要求1所述的封装体,其中,该承载器为一基板或一引线框架。
11、一种封装体模块,其具有多个封装体,这些封装体其中之一包含:
一承载器,其具有一第一表面与一第二表面,该第二表面设置至少一第一接合垫;
一第一芯片,其设置于该第一表面上;
一第一介电层,其设置于该第一表面,并包覆该第一芯片;
至少一第二接合垫,其设置于该第一介电层上;以及
至少一第一导通结构,其位于该第一介电层之中及沿着该第一芯片周缘设置,以将该第一芯片与该第一接合垫电性连结,其中该封装体的该第二接合垫上设置一凸块或焊球,用以连接至另一封装体的该第一接合垫。
12、根据权利要求11所述的封装体模块,其中,这些封装体其中之一更包含:
一保护层,其设置于该第一介电层上,并暴露出该第二接合垫。
13、根据权利要求11所述的封装体模块,其中,该第一接合垫和/或该第二接合垫与一芯片、一封装体或一线路板电性连结。
14、根据权利要求11所述的封装体模块,其中,这些封装体其中之一还包含:
一第二介电层,其设置于该第一介电层上;以及
至少一第二导通结构,其位于该第二介电层之中,以将该第一芯片与该第一接合垫和/或该第一导通结构电性连结。
15、根据权利要求11所述的封装体模块,其中,该承载器为一基板或一引线框架。
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