CN113632209A - Rf半导体装置和其制造方法 - Google Patents
Rf半导体装置和其制造方法 Download PDFInfo
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- CN113632209A CN113632209A CN201980094528.0A CN201980094528A CN113632209A CN 113632209 A CN113632209 A CN 113632209A CN 201980094528 A CN201980094528 A CN 201980094528A CN 113632209 A CN113632209 A CN 113632209A
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- layer
- molding
- active layer
- molding compound
- silicon
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Abstract
本公开涉及一种射频(RF)装置,所述装置包含模制装置管芯和位于模制装置管芯之下的多层重新分布结构。模制装置管芯包含装置区域和第一模制化合物,所述装置区域具有后段制程(BEOL)部分和位于所述BEOL部分之上的前段制程(FEOL)部分。所述FEOL部分包含有源层、接触层以及隔离区段。在本文中,有源层和隔离区段位于接触层之上,并且有源层被隔离区段围绕。第一模制化合物位于有源层之上,而在所述第一模制化合物与所述有源层之间没有不具有锗含量的硅晶体。多层重新分布结构包含重新分布互连件和多个凸点结构,所述多个凸点结构位于所述多层重新分布结构的底部处并且通过所述重新分布互连件电耦接到所述模制装置管芯。
Description
相关申请
本申请要求于2019年1月23日提交的临时专利申请序列号62/795,804的权益,所述临时专利申请的公开内容通过引用整体并入本文。
本申请涉及同时提交的标题为“具有增强性能的RF装置和其形成方法(RFDEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME)”的美国专利申请第_____号,所述美国专利申请的公开内容通过引用整体并入本文。
技术领域
本公开涉及一种射频(RF)装置和其制造过程,并且更具体地涉及具有增强的热性能和增强的电性能的RF装置,以及提供具有增强性能的RF装置的晶圆级封装工艺。
背景技术
蜂窝装置和无线装置的广泛利用驱动了射频(RF)技术的快速发展。在其上制造RF装置的衬底在实现RF技术的高水平性能方面发挥着重要作用。在常规的硅衬底上制造RF装置可以受益于低成本的硅材料、大规模的晶圆生产能力、完善的半导体设计工具和完善的半导体制造技术。
尽管使用常规的硅衬底对RF装置制造有益处,但在本行业中众所周知,常规的硅衬底可能对于RF装置具有两个不期望的性质:谐波失真和低电阻率值。谐波失真是在硅衬底之上构建的RF装置中实现高水平线性化的关键障碍。另外,高速且高性能的晶体管更密集地集成在RF装置中。因此,由于大量晶体管集成在RF装置上,大量功率穿过晶体管,和/或晶体管操作速度高,由RF装置产生的热量将显著增加。因此,期望将RF装置封装在用于实现更好的散热的配置中。
晶圆级扇出型(WLFO)封装技术和嵌入式晶圆级球栅阵列型(EWLB)技术目前在便携式RF应用中引起了广泛关注。WLFO和EWLB技术被设计成在不增加封装体大小的情况下提供高密度输入/输出端口(I/O)。这种能力允许在单个晶圆内密集地封装RF装置。
为了适应RF装置发热量的增加并且减少RF装置的有害谐波失真,并且利用WLFO/EWLB封装技术的优势,因此本公开的目的是提供一种改进的用于增强的热性能和增强的电性能的封装工艺。进一步地,还需要在不增加封装体大小的情况下增强RF装置的性能。
发明内容
本公开涉及一种具有增强的热性能和增强的电性能的射频(RF)装置和其制造过程。所公开的RF装置包含模制装置管芯和多层重新分布结构。所述模制装置管芯包含第一模制化合物和装置区域,所述装置区域具有前段制程(front-end-of-line,FEOL)部分和后段制程(back-end-of-line,BEOL)部分。所述FEOL部分具有有源层、接触层以及隔离区段。在本文中,所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段。所述BEOL位于所述FEOL部分之下,并且包含连接层。所述第一模制化合物位于所述FEOL部分的所述有源层之上,而在所述第一模制化合物与所述有源层之间没有不具有锗含量的硅晶体。所述多层重新分布结构形成于所述模制装置管芯的所述BEOL部分之下。所述多层重新分布结构包含所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件。所述凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分。
在所述RF装置的一个实施例中,所述第一模制化合物的一部分位于所述隔离区段之上。
在所述RF装置的一个实施例中,所述隔离区段竖直延伸超过所述有源层的顶表面以在所述隔离区段内和所述有源层之上限定开口。在本文中,所述第一模制化合物填充所述开口。
根据另一个实施例,RF装置进一步包含钝化层,所述钝化层直接位于所述有源层的所述顶表面之上并且位于所述开口内。在本文中,所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且所述第一模制化合物与所述钝化层接触。
根据另一个实施例,RF装置进一步包含界面层,所述界面层直接位于所述有源层的所述顶表面之上并且位于所述开口内。在本文中,所述界面层由硅锗(SiGe)形成;并且所述第一模制化合物与所述界面层接触。
在所述RF装置的一个实施例中,所述第一模制化合物与所述有源层的所述顶表面接触。
在所述RF装置的一个实施例中,每个隔离区段的顶表面和所述有源层的顶表面共面,并且所述第一模制化合物位于所述有源层和所述隔离区段两者之上。
在所述RF装置的一个实施例中,所述第一模制化合物的热导率大于1W/m·K。
在所述RF装置的一个实施例中,所述第一模制化合物的介电常数小于8。
在所述RF装置的一个实施例中,所述第一模制化合物的介电常数介于3与5之间。
在所述RF装置的一个实施例中,所述FEOL部分被配置成提供开关场效应晶体管(FET)、二极管、电容器、电阻器和电感器中的至少一个。
根据另一个实施例,替代性RF装置包含模制装置管芯和多层重新分布结构。所述模制装置管芯包含第一模制化合物和装置区域,所述装置区域具有FEOL部分和BEOL部分。所述FEOL部分具有有源层、接触层以及隔离区段。在本文中,所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段。所述BEOL部分位于所述FEOL部分之下,并且包含连接层。所述第一模制化合物位于所述FEOL部分的所述有源层之上,而在所述第一模制化合物与所述有源层之间没有不具有锗含量的硅晶体。所述多层重新分布形成于所述模制装置管芯的所述BEOL部分之下,并且包含所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件。所述凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分。所述替代性RF装置进一步包含第二模制化合物,所述第二模制化合物位于所述多层重新分布结构之上并且包封所述模制装置管芯。
在所述替代性RF装置的一个实施例中,所述第一模制化合物由与所述第二模制化合物相同的材料形成。
在所述替代性RF装置的一个实施例中,所述第一模制化合物和所述第二模制化合物由不同的材料形成。
根据示例性过程,首先提供具有多个装置区域的前体晶圆。每个装置区域包含BEOL部分和位于所述BEOL部分之上的FEOL部分。所述FEOL部分具有有源层、接触层以及隔离区段。在本文中,所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段。另外,由硅锗(SiGe)形成的界面层直接位于每个装置区域的所述有源层之上,并且硅处理衬底直接位于每个界面层之上。接下来,完全去除所述硅处理衬底。然后施涂第一模制化合物以提供包含多个模制装置管芯的模制装置晶圆。在本文中,所述第一模制化合物从所述硅处理衬底被去除的位置施涂在每个装置区域的所述有源层之上。在每个装置区域的所述有源层与所述第一模制化合物之间不存在不具有锗含量的硅晶体。每个模制装置管芯包含对应的装置区域和所述第一模制化合物的位于所述对应的装置区域的所述有源层之上的一部分。
根据另一个实施例,所述示例性过程进一步包含,在去除所述硅处理衬底之前,通过接合层将所述前体晶圆与临时载体接合;以及在施涂所述第一模制化合物之后,将所述临时载体与所述前体晶圆上解除接合并且将所述接合层从所述前体晶圆清除。
根据另一个实施例,所述示例性过程进一步包含在所述模制装置晶圆之下形成多层重新分布结构。在本文中,所述多层重新分布结构包含所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件。每个凸点结构通过所述重新分布互连件和对应的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的模制装置管芯的一个有源层。
根据另一个实施例,所述示例性过程进一步包含将所述模制装置晶圆单切成多个单独的模制装置管芯。然后在所述单独的模制装置管芯周围和之上施涂第二模制化合物,以提供双模制装置晶圆。在本文中,所述第二模制化合物包封每个单独的模制装置管芯的顶表面和侧表面,而每个单独的模制装置管芯的底表面暴露。所述双模制装置晶圆的底表面是每个单独的模制装置管芯的所述底表面和所述第二模制化合物的底表面的组合。接下来,在所述双模制装置晶圆之下形成多层重新分布结构。所述多层重新分布结构包含所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件。每个凸点结构通过所述重新分布互连件和对应的单独的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的单独的模制装置管芯的一个有源层。
根据另一个实施例,所述示例性过程进一步包含在施涂所述第一模制化合物之前去除所述界面层,使得在施涂所述第一模制化合物之后,每个装置区域的所述有源层与所述第一模制化合物接触。
根据另一个实施例,所述示例性过程进一步包含在施涂所述第一模制化合物之前,去除所述界面层,并且直接在每个装置区域的所述有源层之上施涂钝化层。所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且在施涂所述第一模制化合物之后,所述钝化层与所述第一模制化合物接触。
在所述示例性过程的一个实施例中,提供所述前体晶圆始于提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底。所述界面层由SiGe形成。然后执行互补金属氧化物半导体(CMOS)工艺以提供所述前体晶圆。在本文中,所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层,并且延伸到所述硅处理衬底中,使得所述公共界面层分离成多个单独的界面层,并且所述公共硅外延层分离成多个单独的硅外延层。所述装置区域的每个有源层由对应的单独的硅外延层形成,每个单独的界面层直接位于对应的有源层的顶表面之上,并且所述硅处理衬底直接位于所述单独的界面层之上。
在所述示例性过程的一个实施例中,提供所述前体晶圆始于提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底。所述公共界面层由SiGe形成,并且包含多个连接在一起的界面层。然后执行CMOS工艺以提供所述前体晶圆。在本文中,所述隔离区段延伸穿过所述公共硅外延层并且延伸到所述公共界面层中,使得所述公共硅外延层分离成多个单独的硅外延层,并且所述界面层保持连接。所述装置区域的每个有源层由对应的单独的硅外延层形成,每个界面层直接位于对应的有源层的所述顶表面之上,并且所述硅处理衬底仍直接位于所述公共界面层之上。
本领域的技术人员将在结合附图阅读优选实施例的以下详细描述之后了解本公开的范围并且认识到本公开的另外的方面。
附图说明
并入本说明书中并且形成本说明书的一部分的附图展示了本公开的若干方面,并且与说明书一起用于解释本公开的原理。
图1示出了根据本公开的一个实施例的具有增强的热性能和增强的电性能的示例性射频(RF)装置。
图2示出了根据本公开的一个实施例的具有增强的热性能和增强的电性能的替代性RF装置。
图3-14提供了展示了制造图1所示的示例性RF装置的步骤的示例性晶圆级封装工艺。
图15-20提供了展示了制造图2所示的替代性RF装置的步骤的替代性晶圆级封装工艺。
应当理解,为了清楚说明,图1-20可以不按比例绘制。
具体实施方式
下文阐述的实施例表示使本领域的技术人员能够实践实施例的必要信息,并且展示了实践实施例的最佳方式。在根据附图阅读以下说明时,本领域的技术人员将理解本公开的概念并且将认识到本文中未特别提出的这些概念的应用。应当理解,这些概念和应用落入本公开和所附权利要求的范围内。
应当理解,尽管本文中可以使用术语第一、第二等来描述各种元件,但是这些元件不应受到这些术语的限制。这些术语仅用于将一个元件与另一个元件相区分。例如,在不偏离本公开的范围的情况下,第一元件可以被称为第二元件,并且类似地,第二元件可以被称为第一元件。如本文所使用的,术语“和/或”包含相关联列举项中的一个或多个的任何组合和全部组合。
应当理解,当如层、区域或衬底等元件被称为“在另一个元件上”或延伸“到另一个元件上”时,其可以直接在其它元件上或直接延伸到其它元件上或者还可以存在中间元件。相比之下,当元件被称为“直接地在另一个元件上”或“直接地延伸到另一个元件上”时,不存在中间元件。同样,应当理解,当如层、区域或衬底等元件被称为“在另一个元件之上”或“在另一个元件之上”延伸时,其可以直接在另一个元件之上或直接在另一个元件之上延伸,或者还可以存在中间元件。相比之下,当元件被称为“直接在另一个元件之上”或“直接在另一个元件之上延伸”时,不存在中间元件。还应当理解,当元件被称为“连接”或“耦接”到另一个元件时,其可以直接地连接或耦接到其它元件,或者可以存在中间元件。相比之下,当元件被称为“直接地连接”或“直接地耦接”到另一个元件时,不存在中间元件。
在本文中可以使用如“下方(below)”或“上方(above)”或“上部(upper)”或“下部(lower)”或“水平”或“竖直”等相对术语来描述如图所示的一个元件、层或区域与另一个元件、层或区域的关系。应当理解,除了附图中描绘的朝向之外,这些术语和上文所讨论的那些术语旨在涵盖装置的不同朝向。
本文所使用的术语仅出于描述特定实施例的目的并且不旨在限制本公开。如本文所使用的,单数形式“一个(a)”、“一种(an)”和“所述(the)”旨在同样包含复数形式,除非上下文另有明确指示。应进一步理解,当在本文中使用时,术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”和/或“包含(including)”指定所陈述的特征、整体、步骤、操作、元件和/或组件的存在,但不排除一个或多个其它特征、整体、步骤、操作、元件、组件和/或其组合的存在或添加。
除非另外限定,否则本文所使用的所有术语(包含技术术语和科技术语)具有本公开所属领域的普通技术人员通常所理解的相同含义。应进一步理解的是,本文所使用的术语应被解释为具有与其在本说明书和相关领域的上下文中的含义一致的含义,并且除非本文中明确地如此定义,否则将不会在理想化的或过度正式的意义上进行解释。
随着预期未来几年常规的射频绝缘体上硅(RFSOI)晶圆将出现短缺,替代性技术正在被设计成使用硅晶圆、富陷阱层形成和智能切割SOI晶圆工艺以满足高电阻率需求。一种替代性技术基于在硅衬底与硅外延层之间使用硅锗(SiGe)界面层而不是埋入式氧化物层(BOX);然而,这种技术也会遭受硅衬底造成的有害失真效应,与在RFSOI技术中所观察到的类似。本公开涉及一种具有增强的热性能和增强的电性能的射频(RF)装置以及制造所述装置的晶圆级封装工艺,基于这种没有来自硅衬底的有害失真效应的Si-SiGe-Si结构。
图1示出了根据本公开的一个实施例的由Si-SiGe-Si晶圆形成的示例性RF装置10(处理细节在以下段落中描述)。出于这种说明的目的,示例性RF装置10包含具有装置区域14和第一模制化合物16的模制装置管芯12,以及形成于模制装置管芯12之下的多层重新分布结构18。
具体地,装置区域14包含前段制程(FEOL)部分20和后段制程(BEOL)部分22,所述BEOL部分位于FEOL部分20之下。在一个实施例中,FEOL部分20被配置成提供开关场效应晶体管(FET),并且包含有源层24和接触层26。在本文中,有源层24具有源极28、漏极30以及介于源极28与漏极30之间的沟道32。源极28、漏极30和沟道32由相同的硅外延层形成。接触层26形成于有源层24之下,并且包含栅极结构34、源极触点36、漏极触点38和栅极触点40。栅极结构34可以由氧化硅形成,并且在沟道32之下水平延伸(从源极28之下延伸到漏极30之下)。源极触点36连接到源极28并位于所述源极之下,漏极触点38连接到漏极30并位于所述漏极之下,并且栅极触点40连接到栅极结构34并位于所述栅极结构之下。绝缘材料42可以在源极触点36、漏极触点38、栅极结构34和栅极触点40周围形成,以将源极28、漏极30和栅极结构34电分离。在不同的应用中,FEOL部分20可以具有不同的FET配置或提供不同的装置组件,如二极管、电容器、电阻器和/或电感器。
另外,FEOL部分20还包含隔离区段44,所述隔离区段位于接触层26的绝缘材料42之上并且围绕有源层24。隔离区段44被配置成将RF装置10尤其是有源层24与形成于公共晶圆中的其它装置电分离(未示出)。在本文中,隔离区段44可以从接触层26的顶表面延伸,并且竖直延伸超过有源层24的顶表面以在隔离区段44内和有源层24之上限定开口46。第一模制化合物16填充开口46,并且可以在隔离区段44之上延伸。隔离区段44可以由二氧化硅形成,所述二氧化硅可以抵抗蚀刻化学物质,如氢氧化钾(KOH)、氢氧化钠(NaOH)和乙酰胆碱(ACH)。
在一些应用中,RF装置10可以进一步包含钝化层48,所述钝化层可以由二氧化硅、氮化硅或两者的组合形成,直接位于有源层24的顶表面之上并且位于开口46内。如此,第一模制化合物16直接位于钝化层48之上。钝化层48被配置成终止有源层24的表面接合,这可能是不想要的泄漏的原因。钝化层也可以充当屏障,并且被配置成保护有源层24免受湿气或离子污染。如果省略了钝化层48,第一模制化合物16可以与有源层24的顶表面接触。在一些应用中,RF装置10可以进一步包含界面层(在以下段落中描述,并且本文未示出),所述界面层由SiGe形成,直接位于有源层24的顶表面之上并且位于开口46内。如此,第一模制化合物16可以直接位于界面层之上。界面层来自用于制造RF装置10的Si-SiGe-Si晶圆(处理细节在以下段落中描述)。如果省略了界面层,第一模制化合物18可以与有源层24的顶表面接触。应当注意,不管钝化层48或界面层如何,在第一模制化合物16与有源层24的顶表面之间不存在不具有锗含量的硅晶体。钝化层48和界面层两者都为硅合金。
进一步地,在一些应用中,每个隔离区段44的顶表面和有源层24的顶表面共面(未示出),并且省略了开口46。第一模制化合物16位于FEOL部分20的有源层24和隔离区段44两者之上。应当注意,有源层24从未竖直超过隔离区段44,否则隔离区段44可能不会将有源层24与由同一晶圆形成的其它装置完全分离。
BEOL部分22位于FEOL部分20之下,并且包含形成于介电层52内的多个连接层50。连接层50中的一些连接层由介电层52包封(未示出),而连接层50中的一些连接层具有未被介电层52覆盖的底部部分。某些连接层50电连接到FEOL部分20。出于这种说明的目的,连接层50之一连接到源极触点36,并且另一个连接层50连接到漏极触点38。
形成于模制装置管芯12的BEOL部分22之下的多层重新分布结构18包含多个重新分布互连件54、介电图案56和多个凸点结构58。在本文中,每个重新分布互连件54连接到BEOL部分22内的对应的连接层50,并且在BEOL部分22的底表面之上延伸。重新分布互连件54与连接层50之间的连接是无焊料的。介电图案56形成于每个重新分布互连件54的周围和之下。每个重新分布互连件54的底部部分通过介电图案56暴露。每个凸点结构58形成于多层重新分布结构18的底部处,并且通过介电图案56电耦接到对应的重新分布互连件54。因此,重新分布互连件54被配置成将凸点结构58连接到BEOL部分22中的连接层50中的电连接到FEOL部分20的某些连接层。如此,凸点结构58通过对应的重新分布互连件54和对应的连接层50电连接到FEOL部分20。另外,凸点结构58彼此分离,并且在介电图案56之下延伸。
在一些应用中,重新分布互连件54中的一些重新分布互连件可以被配置成将模制装置管芯12连接到由同一晶圆形成的其它装置组件(未示出)。在一些应用中,可以存在通过介电图案56电耦接到重新分布互连件54的额外的重新分布互连件(未示出),以及形成于介电图案56之下的额外的介电图案(未示出),使得每个额外的重新分布互连件的底部部分暴露。因此,每个凸点结构58通过额外的介电图案(未示出)耦接到对应的额外的重新分布互连件。不管重新分布互连件和/或介电图案的层数如何,多层重新分布结构18可以不含玻璃纤维或不含玻璃。在本文中,玻璃纤维是指扭曲成更大分组的单独的玻璃原丝。然后,这些玻璃原丝可以编织成织物。重新分布互连件54可以由铜或其它合适的金属形成。介电图案56可以由苯并环丁烯(BCB)、聚酰亚胺或其它介电材料形成。凸点结构58可以是焊料球或铜柱。多层重新分布结构18的厚度介于2μm与300μm之间。
在装置区域14中产生的热量可以向上行进到位于有源层24之上的第一模制化合物16的底部部分,并且然后将向下穿过装置区域14并朝向多层重新分布结构18,这将消散热量。因此,非常期望第一模制化合物16具有高热导率。第一模制化合物16的热导率可以大于1W/m·K或大于1 0W/m·K。另外,第一模制化合物16的低介电常数可以小于8或介于3与5之间,以产生低RF耦接。在一个实施例中,第一模制化合物16可以由如PPS(聚苯硫醚)、掺杂有氮化硼、氧化铝、碳纳米管或类金刚石热添加剂的包覆模制的环氧树脂等热塑性或热固性聚合物材料形成。第一模制化合物16的厚度基于RF装置10所需的热性能、装置布局、距多层重新分布结构18的距离以及封装体和组合件的细节。第一模制化合物16的厚度可以介于200μm与500μm之间。
图2示出了与RF装置10相比,进一步包含第二模制化合物60的替代性RF装置10A。在本文中,多层重新分布结构18水平延伸超过模制装置管芯12,并且第二模制化合物60位于多层重新分布结构18之上以包封模制装置管芯12。在此实施例中,多层重新分布结构18的重新分布互连件54可以水平延伸超过模制装置管芯12,并且多层重新分布结构18的凸点结构58可以不被限制在模制装置管芯12的***内。第二模制化合物60可以由与第一模制化合物16相同或不同的材料形成。与第一模制化合物16不同,第二模制化合物60可以没有热导率或介电常数要求。
图3-14提供了展示了制造图1所示的示例性RF装置10的步骤的示例性晶圆级封装工艺。尽管示例性步骤以系列展示,但是示例性步骤不一定取决于顺序。一些步骤可能会以不同于所呈现的顺序进行。进一步地,本公开范围内的过程可以包含比图3-14所展示的步骤更少或更多的步骤。
首先,如图3所展示的,提供Si-SiGe-Si晶圆62。Si-SiGe-Si晶圆62包含公共硅外延层64、位于公共硅外延层64之上的公共界面层66和位于公共界面层66之上的硅处理衬底68。在本文中,由SiGe形成的公共界面层66将公共硅外延层64与硅处理衬底68分离。
在本文中,公共硅外延层64由具有形成电子装置所期望的硅外延特性的装置级硅材料形成。公共界面层66由具有任何Si与Ge的摩尔比的合金形成。Ge浓度越高,硅处理衬底68与公共界面层66之间的蚀刻选择性越好,但公共硅外延层64的外延生长也变得越困难。在一个实施例中,公共界面层66的Ge浓度可以大于15%或大于25%。Ge浓度在整个公共界面层66中可以是均匀的。在一些应用中,Ge浓度可以是竖直分级的(介于1%与50%之间),以便为公共硅外延层64的生长产生必要的应变消除。硅处理衬底68可以由常规的低成本、低电阻率和高介电常数的硅组成。公共硅外延层64比硅处理衬底68具有更高的电阻率、更低的谐波产生和更低的介电常数。公共硅外延层64的厚度可以介于700nm与2000nm之间,公共界面层66的厚度可以介于100nm与1000nm之间,并且硅处理衬底68的厚度可以介于200μm与500μm之间。
接下来,对Si-SiGe-Si晶圆62执行互补金属氧化物半导体(CMOS)工艺,以提供具有多个装置区域14的前体晶圆70,如图4A所展示的。出于这种说明的目的,每个装置区域14的FEOL部分20被配置成提供开关FET。在不同的应用中,FEOL部分20可以具有不同的FET配置或提供不同的装置组件,如二极管、电容器、电阻器和/或电感器。
在此实施例中,每个装置区域14的隔离区段44延伸穿过公共硅外延层64和公共界面层66,并延伸到硅处理衬底68中。如此,公共界面层66分离成多个单独的界面层66I,并且公共硅外延层64分离成多个单独的硅外延层64I,每个硅外延层用于在一个装置区域14中形成对应的有源层24。隔离区段44可以通过浅沟槽隔离(STI)形成。
有源层24的顶表面与对应的界面层66I接触。硅处理衬底68位于每个单独的界面层66I之上,并且硅处理衬底68的一部分可以位于隔离区段44之上。装置区域14的至少包含所述多个连接层50和介电层52的BEOL部分22形成于FEOL部分20的接触层26之下。某些连接层50的底部部分通过位于BEOL部分22的底表面处的介电层52暴露。
在另一个实施例中,隔离区段44未延伸到硅处理衬底68中。相反,隔离区段44仅延伸穿过公共硅外延层64,并延伸到公共界面层66中,如图4B所展示的。在本文中,公共界面层66保持连续,并且单独的界面层66I彼此连接。公共界面层66直接位于每个有源层24的顶表面之上,并且直接位于每个隔离区段44的顶表面之上。硅处理衬底68仍位于公共界面层66之上。进一步地,隔离区段44可以延伸穿过公共硅外延层64,但是不延伸到公共界面层66中(未示出)。每个隔离区段44的顶表面和每个有源层24的顶表面可以共面(未示出)。公共界面层66和硅处理衬底68保持完整。公共界面层66位于每个隔离区段44和每个有源层24之上,并且硅处理衬底68位于公共界面层66之上。
在完成前体晶圆70后,前体晶圆70然后与临时载体72接合,如图5所展示的。前体晶圆70可以通过为临时载体72提供平坦化表面的接合层74与临时载体72接合。从成本和热膨胀的角度来看,临时载体72可以是厚的硅晶圆,但是也可以理解为玻璃、蓝宝石或其它合适的载体材料。接合层74可以是跨接式聚合粘合膜(span-on polymeric adhesive film),如布鲁尔科技公司(Brewer Science)WaferBOND临时粘合材料系列。
然后选择性地去除硅处理衬底68以提供蚀刻的晶圆76,其中在每个界面层66I上停止选择性去除,如图6所展示的。如果隔离区段44竖直延伸超过界面层66I,硅处理衬底68的去除将在每个有源层24之上和隔离区段44内提供开口46。去除硅处理衬底68可以通过化学机械研磨和使用湿/干蚀刻剂化学物质的蚀刻工艺来提供,所述湿/干蚀刻剂化学物质可以是TMAH、KOH、NaOH、ACH、或XeF2,或者通过蚀刻工艺本身来提供。作为实例,硅处理衬底68可以被研磨到更薄的厚度,以减少随后的蚀刻时间。然后执行蚀刻工艺以完全去除剩余的硅处理衬底68。由于硅处理衬底68和界面层66I具有不同的特性,其可能对相同的蚀刻技术具有不同的反应(例如:相同的蚀刻剂的不同蚀刻速度)。因此,蚀刻***能够标识界面层66I的存在,并且能够指示何时停止蚀刻工艺。
在去除工艺期间,不去除隔离区段44并且保护每个FEOL部分20的侧面。接合层74和临时载体72保护每个BEOL部分22的底表面。在本文中,每个隔离区段44的顶表面和每个界面层66I的顶表面在去除工艺之后暴露。如果隔离区段44仅延伸到公共界面层66中,而不穿过公共界面层66(如图3B所示),或者每个隔离区段44的顶表面和每个有源层24的顶表面共面(未示出),则仅公共界面层66的顶表面暴露(未示出)。
由于SiGe材料的窄间隙性质,界面层66I(或公共界面层66)可能是传导的。界面层66I可能在有源层24的源极28与漏极30之间导致明显的泄漏。因此,在如FET应用等一些应用中,也期望去除界面层66I(或公共界面层66),如图7所展示的。界面层66I可以通过用于去除硅处理衬底68的相同的蚀刻工艺来去除,或者可以通过如HCI干蚀刻***等另一种蚀刻工艺来去除。如果界面层66I足够薄,其可能完全耗尽并且可能不会在FEOL部分20的源极28与漏极30之间引起任何明显的泄漏。在所述情况下,界面层66I可以保持完整。
在一些应用中,可以由二氧化硅、氮化硅或两者的组合形成的钝化层48可以直接形成于每个FEOL部分20的有源层24之上,如图8所展示的。如果每个有源层24之上和隔离区段44内存在开口46,则钝化层48形成于开口46内。钝化层48被配置成终止有源层24的顶表面处的表面接合,这可能是不想要的泄漏的原因。可以通过CVD介电膜或钝化等离子体形成钝化层48。
接下来,在蚀刻的晶圆76之上施涂第一模制化合物16以提供模制装置晶圆78,如图9所展示的。模制装置晶圆78包含多个模制装置管芯12,所述模制装置管芯中的每个模制装置管芯包含装置区域14和第一模制化合物16的一部分。在本文中,第一模制化合物16填充每个开口46,并与开口46内的钝化层48接触。另外,第一模制化合物16的一部分可以在隔离区段44之上延伸。如果在每个开口46中没有形成钝化层48,则第一模制化合物16与每个有源层24的顶表面接触(未示出)。如果界面层66I仍位于每个有源层24的顶表面之上,则第一模制化合物16与界面层66I接触(未示出)。第一模制化合物16总是位于每个有源层24之上。
第一模制化合物16可以通过各种程序施涂,如压缩模制、片材模制、包覆模制、传递模制、围堰填充包封和丝网印刷包封。第一模制化合物16可以具有大于1W/m·K或大于10W/m·K的优异的热导率,并且可以具有小于8或介于3与5之间的介电常数。在第一模制化合物16的模制工艺期间,临时载体72为蚀刻的晶圆76提供机械强度和刚性。接着进行固化工艺(未示出)以使第一模制化合物16硬化。固化温度介于100℃与320℃之间,这取决于使用哪种材料作为第一模制化合物16。在固化工艺之后,第一模制化合物16可以变薄和/或平坦化(未示出)。
然后将临时载体72与模制装置晶圆78解除接合,并将接合层74从模制装置晶圆78清除,如图10所展示的。根据先前步骤中选择的临时载体72和接合层74的性质,可以应用多种解除接合工艺和清除工艺。例如,可以在堆叠件被加热到合适的温度的情况下使用侧刃工艺(lateral blade process)对临时载体72进行机械解除接合。如果临时载体72由透明材料形成,其它合适的工艺涉及穿过所述临时载体的UV光照射,或者使用合适的溶剂的化学解除接合。接合层74可以通过如专有溶剂和等离子体清洗等湿蚀刻工艺或干蚀刻工艺来去除。在解除接合和清除工艺之后,连接层50中的某些连接层的可以用作模制装置管芯12的输入/输出(I/O)端口的底部部分通过每个BEOL部分22的底表面处的介电层52暴露。如此,此时可以对模制装置晶圆78中的每个模制装置管芯12进行电气验证以确定所述模制装置管芯工作正常。
参考图11到13,根据本公开的一个实施例,多层重新分布结构18形成于模制装置晶圆78之下。尽管重新分布步骤以系列展示,但是重新分布步骤不一定取决于顺序。一些步骤可能会以不同于所呈现的顺序进行。进一步地,本公开范围内的重新分布步骤可以包含比图11-13所展示的步骤更少或更多的步骤。
首先多个重新分布互连件54形成于每个BEOL部分22之下,如图11所展示的。每个重新分布互连件54电耦接到BEOL部分22内的对应的连接层50的暴露的底部部分,并且可以在BEOL部分22的底表面之上延伸。重新分布互连件54与连接层50之间的连接是无焊料的。然后介电图案56形成于每个BEOL部分22之下以部分包封每个重新分布互连件54,如图12所展示的。如此,每个重新分布互连件54的底部部分通过介电图案56暴露。在不同的应用中,可以存在通过介电图案56电耦接到重新分布互连件54的额外的重新分布互连件(未示出),以及形成于介电图案56之下的额外的介电图案(未示出),使得每个额外的重新分布互连件的底部部分暴露。
接下来,形成多个凸点结构58以完成多层重新分布结构18,并且提供晶圆级扇出型(WLFO)封装体80,如图13所展示的。每个凸点结构58形成于多层重新分布结构18的底部处,并且通过介电图案56电耦接到对应的重新分布互连件54的暴露的底部部分。因此,重新分布互连件54被配置成将凸点结构58连接到BEOL部分22中的连接层50中的电连接到FEOL部分20的某些连接层。如此,凸点结构58通过对应的重新分布互连件54和对应的连接层50电连接到FEOL部分20。另外,凸点结构58彼此分离,并且在介电图案56之下延伸。
多层重新分布结构18可以不含玻璃纤维或不含玻璃。在本文中,玻璃纤维是指扭曲成更大分组的单独的玻璃原丝。然后,这些玻璃原丝可以编织成织物。重新分布互连件54可以由铜或其它合适的金属形成,介电图案56可以由BCB、聚酰亚胺或其它介电材料形成,并且凸点结构58可以是焊料球或铜柱。多层重新分布结构18的厚度介于2μm与300μm之间。图14示出了将WLFO封装体80单切成单独的RF装置10的最后步骤。可以通过在某些隔离区段44处进行探测和分割工艺来提供单切步骤。
在另一个实施例中,图15-20提供了展示了制造图2所示的替代性RF装置10A的步骤的替代性晶圆级封装工艺。尽管示例性步骤以系列展示,但是示例性步骤不一定取决于顺序。一些步骤可能会以不同于所呈现的顺序进行。进一步地,本公开范围内的过程可以包含比图15-20所展示的步骤更少或更多的步骤。
如图10所示,在解除接合工艺和清除工艺之后以提供干净的模制装置晶圆78,接着进行单切步骤以将模制装置晶圆78单切成单独的装置管芯12,如图15所展示的。每个模制装置管芯12可以具有相同的高度,并且包含具有FEOL部分20和BEOL部分22的装置区域14以及第一模制化合物16。
接下来,在模制装置管芯12周围和之上施涂第二模制化合物60,以提供双模制装置晶圆82,如图16所展示的。第二模制化合物60包封每个模制装置管芯12的顶表面和侧表面,而每个模制装置管芯12的底表面即BEOL部分22的底表面是暴露的。双模制装置晶圆82的底表面是每个模制装置管芯12的底表面和第二模制化合物60的底表面的组合。在本文中,连接层50中的某些连接层的底部部分保持在每个模制装置管芯12的底表面处暴露。第二模制化合物60可以通过各种程序施涂,如片材模制、包覆模制、压缩模制、传递模制、围堰填充包封或丝网印刷包封。第二模制化合物60可以由与第一模制化合物16相同或不同的材料形成。然而,与第一模制化合物16不同,第二模制化合物60没有热导率或电阻率要求。第二模制化合物60可以是有机环氧树脂体系等。然后使用固化工艺(未示出)来使第二模制化合物60硬化。固化温度介于100℃与320℃之间,这取决于使用哪种材料作为第二模制化合物60。接着可以进行研磨工艺(未示出)以提供第二模制化合物60的平坦化顶表面。
参考图17到19,根据本公开的一个实施例形成多层重新分布结构18。尽管重新分布步骤以系列展示,但是重新分布步骤不一定取决于顺序。一些步骤可能会以不同于所呈现的顺序进行。进一步地,本公开范围内的重新分布步骤可以包含比图17-19所展示的步骤更少或更多的步骤。
首先多个重新分布互连件54形成于双模制装置晶圆82之下,如图17所展示的。每个重新分布互连件54电耦接到BEOL部分22内的对应的连接层50,并且可以水平延伸超过对应的模制装置管芯12并且在第二模制化合物60之下水平延伸。重新分布互连件54与连接层50之间的连接是无焊料的。然后介电图案56形成于双模制装置晶圆82之下,以部分包封每个重新分布互连件54,如图18所展示的。如此,每个重新分布互连件54的底部部分通过介电图案56暴露。在不同的应用中,可以存在通过介电图案56电耦接到重新分布互连件54的额外的重新分布互连件(未示出),以及形成于介电图案56之下的额外的介电图案(未示出),使得每个额外的重新分布互连件的底部部分暴露。
接下来,形成多个凸点结构58以完成多层重新分布结构18,并且提供替代性WLFO封装体80A,如图19所展示的。每个凸点结构58形成于多层重新分布结构18的底部处,并且通过介电图案56电耦接到对应的重新分布互连件54的暴露的底部部分。因此,重新分布互连件54被配置成将凸点结构58连接到BEOL部分22中的连接层50中的电连接到FEOL部分20的某些连接层。如此,凸点结构58通过对应的重新分布互连件54和对应的连接层50电连接到FEOL部分20。在本文中,凸点结构58可以不被限制在对应的模制装置管芯12的***内。另外,凸点结构58彼此分离,并且在介电图案56之下延伸。
图20示出了将替代性WLFO封装体80A单切成单独的替代性RF装置10A的最后步骤。可以通过在第二模制化合物60的部分处进行探测和分割工艺来提供单切步骤,所述部分水平地位于相邻的模制装置管芯12之间。
本领域的技术人员将认识到对本公开的优选实施例的改进和修改。所有此类改进和修改都认为是在本文公开的概念和所附权利要求的范围内。
权利要求书(按照条约第19条的修改)
1.一种设备,其包括:
●模制装置管芯,所述模制装置管芯包括装置区域和第一模制化合物,其中:
●所述装置区域包含前段制程(FEOL)部分和后段制程(BEOL)部分,BEOL部分位于FEOL部分之下并且包括连接层;
●所述FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,所述隔离区段不位于所述有源层之上,并且所述隔离区段竖直延伸超过所述有源层的顶表面以在所述隔离区段内和所述有源层之上限定开口;并且
●所述第一模制化合物位于所述FEOL部分的所述有源层之上以填充所述开口,其中在所述第一模制化合物与所述有源层之间不存在不具有锗、氮或氧含量的硅晶体;以及
●多层重新分布结构,所述多层重新分布结构形成于所述模制装置管芯的所述BEOL部分之下,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分。
2.根据权利要求1所述的设备,其中所述第一模制化合物的一部分位于所述隔离区段之上。
3.根据权利要求1所述的设备,其进一步包括钝化层,所述钝化层直接位于所述有源层的所述顶表面之上并且位于所述开口内,其中:
●所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且
●所述第一模制化合物与所述钝化层接触。
4.根据权利要求1所述的设备,其进一步包括界面层,所述界面层直接位于所述FEOL部分的顶表面之上并且位于所述开口内,其中:
●所述界面层由硅锗(SiGe)形成;并且
●所述第一模制化合物与所述界面层接触。
5.根据权利要求1所述的设备,其中所述第一模制化合物与所述有源层的所述顶表面接触。
6.根据权利要求1所述的设备,其中所述第一模制化合物的热导率大于1W/m·K。
7.根据权利要求1所述的设备,其中所述第一模制化合物的介电常数小于8。
8.根据权利要求1所述的设备,其中所述第一模制化合物的介电常数介于3与5之间。
9.根据权利要求1所述的设备,其中所述FEOL部分被配置成提供开关场效应晶体管(FET)、二极管、电容器、电阻器和电感器中的至少一个。
10.一种设备,其包括:
●模制装置管芯,所述模制装置管芯包括装置区域和第一模制化合物,其中:
●所述装置区域包含前段制程(FEOL)部分和后段制程(BEOL)部分,BEOL部分位于FEOL部分之下并且包括连接层;
●所述FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,所述隔离区段不位于所述有源层之上,并且所述隔离区段竖直延伸超过所述有源层的顶表面以在所述隔离区段内和所述有源层之上限定开口;并且
●所述第一模制化合物位于所述FEOL部分的所述有源层之上以填充所述开口,其中在所述第一模制化合物与所述有源层之间不存在不具有锗、氮和氧含量的硅晶体;以及
●多层重新分布结构,所述多层重新分布结构形成于所述模制装置管芯的所述BEOL部分之下,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分;以及
●第二模制化合物,所述第二模制化合物位于所述多层重新分布结构之上并且包封所述模制装置管芯。
11.根据权利要求10所述的设备,其中所述第一模制化合物由与所述第二模制化合物相同的材料形成。
12.根据权利要求10所述的设备,其中所述第一模制化合物和所述第二模制化合物由不同的材料形成。
13.一种方法,其包括:
●提供具有多个装置区域的前体晶圆,其中:
●所述多个装置区域中的每个装置区域包含后段制程(BEOL)部分和位于BEOL部分之上的前段制程(FEOL)部分;
●FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段;
●由硅锗(SiGe)形成的界面层直接位于所述多个装置区域中的每个装置区域的所述有源层之上;并且
●硅处理衬底直接位于每个界面层之上;
●完全去除所述硅处理衬底;
●去除所述界面层以暴露所述多个装置区域中的每个装置区域的所述有源层;以及
●施涂第一模制化合物以提供包含多个模制装置管芯的模制装置晶圆;其中:
●所述第一模制化合物在所述界面层被去除之后施涂在所述多个装置区域的每个装置区域的所述有源层之上;
●在所述多个装置区域中的每个装置区域的所述有源层与所述第一模制化合物之间不存在不具有锗、氮或氧含量的硅晶体;并且
●所述多个模制装置管芯中的每个模制装置管芯包含对应的装置区域和所述第一模制化合物的位于所述对应的装置区域的所述有源层之上的一部分。
14.根据权利要求13所述的方法,其进一步包括:
●在去除所述硅处理衬底之前,通过接合层将所述前体晶圆与临时载体接合;以及
●在施涂所述第一模制化合物之后,将所述临时载体与所述前体晶圆解除接合并且将所述接合层从所述前体晶圆清除。
15.根据权利要求13所述的方法,其进一步包括在所述模制装置晶圆之下形成多层重新分布结构,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构中的每个凸点结构通过所述重新分布互连件和对应的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的模制装置管芯的一个有源层。
16.根据权利要求13所述的方法,其进一步包括:
●将所述模制装置晶圆单切成多个单独的模制装置管芯;
●在所述多个单独的模制装置管芯周围和之上施涂第二模制化合物,以提供双模制装置晶圆,其中:
●所述第二模制化合物包封所述多个单独的模制装置管芯中的每个模制装置管芯的顶表面和侧表面,而所述多个单独的模制装置管芯中的每个模制装置管芯的底表面暴露;并且
●所述双模制装置晶圆的底表面是所述多个单独的模制装置管芯中的每个模制装置管芯的所述底表面和所述第二模制化合物的底表面的组合;并且
●在所述双模制装置晶圆之下形成多层重新分布结构,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构中的每个凸点结构通过所述重新分布互连件和对应的单独的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的单独的模制装置管芯的一个有源层。
17.根据权利要求13所述的方法,其中在施涂所述第一模制化合物之后,所述多个装置区域中的每个装置区域的所述有源层与所述第一模制化合物接触。
18.根据权利要求13所述的方法,其进一步包括在施涂所述第一模制化合物之前,直接在所述多个装置区域中的每个装置区域的所述有源层之上施涂钝化层,其中:
●所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且
●在施涂所述第一模制化合物之后,所述钝化层与所述第一模制化合物接触。
19.根据权利要求13所述的方法,其中提供所述前体晶圆包括:
●提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底,其中所述界面层包括SiGe;以及
●执行互补金属氧化物半导体(CMOS)工艺以提供所述前体晶圆,其中:
●所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层并且延伸到所述硅处理衬底中,使得所述公共界面层分离成多个单独的界面层,并且所述公共硅外延层分离成多个单独的硅外延层,
●所述多个装置区域的每个有源层由对应的单独的硅外延层形成;并且
●所述多个单独的界面层中的每个界面层直接位于对应的有源层的顶表面之上,并且所述硅处理衬底直接位于所述多个单独的界面层之上。
20.根据权利要求13所述的方法,其中提供所述前体晶圆包括:
●提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底,其中:
●所述公共界面层由SiGe形成;并且
●所述公共界面层包含连接的多个界面层;以及
●执行CMOS工艺以提供所述前体晶圆,其中:
●所述隔离区段延伸穿过所述公共硅外延层并且延伸到所述公共界面层中,使得所述公共硅外延层分离成多个单独的硅外延层,并且所述多个界面层保持连接;
●所述多个装置区域的每个有源层由对应的单独的硅外延层形成;并且
●所述多个界面层中的每个界面层直接位于对应的有源层的顶表面之上,并且所述硅处理衬底仍直接位于所述公共界面层之上。
Claims (22)
1.一种设备,其包括:
●模制装置管芯,所述模制装置管芯包括装置区域和第一模制化合物,其中:
●所述装置区域包含前段制程(FEOL)部分和后段制程(BEOL)部分,BEOL部分位于FEOL部分之下并且包括连接层;
●所述FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段;并且
●所述第一模制化合物位于所述FEOL部分的所述有源层之上,而在所述第一模制化合物与所述有源层之间没有不具有锗含量的硅晶体;以及
●多层重新分布结构,所述多层重新分布结构形成于所述模制装置管芯的所述BEOL部分之下,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分。
2.根据权利要求1所述的设备,其中所述第一模制化合物的一部分位于所述隔离区段之上。
3.根据权利要求1所述的设备,其中所述隔离区段竖直延伸超过所述有源层的顶表面以在所述隔离区段内和所述有源层之上限定开口,其中所述第一模制化合物填充所述开口。
4.根据权利要求3所述的设备,其进一步包括钝化层,所述钝化层直接位于所述有源层的所述顶表面之上并且位于所述开口内,其中:
●所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且
●所述第一模制化合物与所述钝化层接触。
5.根据权利要求3所述的设备,其进一步包括界面层,所述界面层直接位于所述FEOL部分的顶表面之上并且位于所述开口内,其中:
●所述界面层由硅锗(SiGe)形成;并且
●所述第一模制化合物与所述界面层接触。
6.根据权利要求3所述的设备,其中所述第一模制化合物与所述有源层的所述顶表面接触。
7.根据权利要求1所述的设备,其中每个隔离区段的顶表面和所述有源层的顶表面共面,其中所述第一模制化合物位于所述有源层和所述隔离区段两者之上。
8.根据权利要求1所述的设备,其中所述第一模制化合物的热导率大于1W/m·K。
9.根据权利要求1所述的设备,其中所述第一模制化合物的介电常数小于8。
10.根据权利要求1所述的设备,其中所述第一模制化合物的介电常数介于3与5之间。
11.根据权利要求1所述的设备,其中所述FEOL部分被配置成提供开关场效应晶体管(FET)、二极管、电容器、电阻器和电感器中的至少一个。
12.一种设备,其包括:
●模制装置管芯,所述模制装置管芯包括装置区域和第一模制化合物,其中:
●所述装置区域包含前段制程(FEOL)部分和后段制程(BEOL)部分,BEOL部分位于FEOL部分之下并且包括连接层;
●所述FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段;并且
●所述第一模制化合物位于所述FEOL部分的所述有源层之上,而在所述第一模制化合物与所述有源层之间没有不具有锗含量的硅晶体;以及
●多层重新分布结构,所述多层重新分布结构形成于所述模制装置管芯的所述BEOL部分之下,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构通过所述重新分布互连件和所述BEOL部分内的所述连接层电耦接到所述模制装置管芯的所述FEOL部分;以及
●第二模制化合物,所述第二模制化合物位于所述多层重新分布结构之上并且包封所述模制装置管芯。
13.根据权利要求12所述的设备,其中所述第一模制化合物由与所述第二模制化合物相同的材料形成。
14.根据权利要求12所述的设备,其中所述第一模制化合物和所述第二模制化合物由不同的材料形成。
15.一种方法,其包括:
●提供具有多个装置区域的前体晶圆,其中:
●所述多个装置区域中的每个装置区域包含后段制程(BEOL)部分和位于BEOL部分之上的前段制程(FEOL)部分;
●FEOL部分包括有源层、接触层和隔离区段,其中所述有源层和所述隔离区段位于所述接触层之上,所述隔离区段围绕所述有源层,并且所述有源层未竖直延伸超过所述隔离区段;
●由硅锗(SiGe)形成的界面层直接位于所述多个装置区域中的每个装置区域的所述有源层之上;并且
●硅处理衬底直接位于每个界面层之上;
●完全去除所述硅处理衬底;以及
●施涂第一模制化合物以提供包含多个模制装置管芯的模制装置晶圆;其中:
●所述第一模制化合物从所述硅处理衬底被去除的位置施涂在所述多个装置区域的每个装置区域的所述有源层之上;
●在所述多个装置区域中的每个装置区域的所述有源层与所述第一模制化合物之间不存在不具有锗含量的硅晶体;并且
●所述多个模制装置管芯中的每个模制装置管芯包含对应的装置区域和所述第一模制化合物的位于所述对应的装置区域的所述有源层之上的一部分。
16.根据权利要求15所述的方法,其进一步包括:
●在去除所述硅处理衬底之前,通过接合层将所述前体晶圆与临时载体接合;以及
●在施涂所述第一模制化合物之后,将所述临时载体与所述前体晶圆解除接合并且将所述接合层从所述前体晶圆清除。
17.根据权利要求15所述的方法,其进一步包括在所述模制装置晶圆之下形成多层重新分布结构,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构中的每个凸点结构通过所述重新分布互连件和对应的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的模制装置管芯的一个有源层。
18.根据权利要求15所述的方法,其进一步包括:
●将所述模制装置晶圆单切成多个单独的模制装置管芯;
●在所述多个单独的模制装置管芯周围和之上施涂第二模制化合物,以提供双模制装置晶圆,其中:
●所述第二模制化合物包封所述多个单独的模制装置管芯中的每个模制装置管芯的顶表面和侧表面,而所述多个单独的模制装置管芯中的每个模制装置管芯的底表面暴露;并且
●所述双模制装置晶圆的底表面是所述多个单独的模制装置管芯中的每个模制装置管芯的所述底表面和所述第二模制化合物的底表面的组合;并且
●在所述双模制装置晶圆之下形成多层重新分布结构,其中所述多层重新分布结构包括所述多层重新分布结构的底表面上的多个凸点结构和所述多层重新分布结构内的重新分布互连件,其中所述多个凸点结构中的每个凸点结构通过所述重新分布互连件和对应的单独的模制装置管芯的所述BEOL部分内的连接层电耦接到所述对应的单独的模制装置管芯的一个有源层。
19.根据权利要求15所述的方法,其进一步包括在施涂所述第一模制化合物之前去除所述界面层,其中在施涂所述第一模制化合物之后,所述多个装置区域中的每个装置区域的所述有源层与所述第一模制化合物接触。
20.根据权利要求15所述的方法,其进一步包括在施涂所述第一模制化合物之前,去除所述界面层并且直接在所述多个装置区域中的每个装置区域的所述有源层之上施涂钝化层,其中:
●所述钝化层由二氧化硅、氮化硅或两者的组合形成;并且
●在施涂所述第一模制化合物之后,所述钝化层与所述第一模制化合物接触。
21.根据权利要求15所述的方法,其中提供所述前体晶圆包括:
●提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底,其中所述界面层包括SiGe;以及
●执行互补金属氧化物半导体(CMOS)工艺以提供所述前体晶圆,其中:
●所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层并且延伸到所述硅处理衬底中,使得所述公共界面层分离成多个单独的界面层,并且所述公共硅外延层分离成多个单独的硅外延层,
●所述多个装置区域的每个有源层由对应的单独的硅外延层形成;并且
●所述多个单独的界面层中的每个界面层直接位于对应的有源层的顶表面之上,并且所述硅处理衬底直接位于所述多个单独的界面层之上。
22.根据权利要求15所述的方法,其中提供所述前体晶圆包括:
●提供Si-SiGe-Si晶圆,所述Si-SiGe-Si晶圆包含公共硅外延层、位于所述公共硅外延层之上的公共界面层和位于所述公共界面层之上的所述硅处理衬底,其中:
●所述公共界面层由SiGe形成;并且
●所述公共界面层包含连接的多个界面层;以及
●执行CMOS工艺以提供所述前体晶圆,其中:
●所述隔离区段延伸穿过所述公共硅外延层并且延伸到所述公共界面层中,使得所述公共硅外延层分离成多个单独的硅外延层,并且所述多个界面层保持连接;
●所述多个装置区域的每个有源层由对应的单独的硅外延层形成;并且
●所述多个界面层中的每个界面层直接位于对应的有源层的顶表面之上,并且所述硅处理衬底仍直接位于所述公共界面层之上。
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2019
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- 2019-05-30 US US16/427,019 patent/US11923313B2/en active Active
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TW202101602A (zh) | 2021-01-01 |
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US11923313B2 (en) | 2024-03-05 |
US20230260921A1 (en) | 2023-08-17 |
TWI815993B (zh) | 2023-09-21 |
EP3915134A1 (en) | 2021-12-01 |
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