CN1674248A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1674248A CN1674248A CNA2005100560678A CN200510056067A CN1674248A CN 1674248 A CN1674248 A CN 1674248A CN A2005100560678 A CNA2005100560678 A CN A2005100560678A CN 200510056067 A CN200510056067 A CN 200510056067A CN 1674248 A CN1674248 A CN 1674248A
- Authority
- CN
- China
- Prior art keywords
- groove
- mentioned
- angle
- inclination
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004085051A JP4564272B2 (ja) | 2004-03-23 | 2004-03-23 | 半導体装置およびその製造方法 |
JP2004085051 | 2004-03-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1674248A true CN1674248A (zh) | 2005-09-28 |
CN100377332C CN100377332C (zh) | 2008-03-26 |
Family
ID=35046651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100560678A Active CN100377332C (zh) | 2004-03-23 | 2005-03-23 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20050221579A1 (zh) |
JP (1) | JP4564272B2 (zh) |
KR (1) | KR100707899B1 (zh) |
CN (1) | CN100377332C (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104217985A (zh) * | 2013-05-31 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件和浅沟槽的制作方法 |
CN105336696A (zh) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | 一种同时改善STI和FG Poly填充孔洞工艺窗口的方法 |
CN105470201A (zh) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | 一种同时改善STI和FG Poly填充空洞的闪存器件工艺方法 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4564272B2 (ja) | 2004-03-23 | 2010-10-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4533358B2 (ja) | 2005-10-18 | 2010-09-01 | キヤノン株式会社 | インプリント方法、インプリント装置およびチップの製造方法 |
US8936995B2 (en) * | 2006-03-01 | 2015-01-20 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
KR100801062B1 (ko) * | 2006-07-07 | 2008-02-04 | 삼성전자주식회사 | 트렌치 소자 분리 방법, 이를 이용한 게이트 구조물 형성방법 및 불 휘발성 메모리 소자 형성 방법 |
KR100800379B1 (ko) * | 2006-08-29 | 2008-02-01 | 삼성전자주식회사 | 비휘발성 메모리 소자의 게이트 제조방법 |
KR100913004B1 (ko) * | 2006-09-06 | 2009-08-20 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜치 형성 방법 |
JP4389229B2 (ja) * | 2006-12-20 | 2009-12-24 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US20080197378A1 (en) * | 2007-02-20 | 2008-08-21 | Hua-Shuang Kong | Group III Nitride Diodes on Low Index Carrier Substrates |
JP2009049230A (ja) * | 2007-08-21 | 2009-03-05 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
JP2010272758A (ja) * | 2009-05-22 | 2010-12-02 | Hitachi High-Technologies Corp | 被エッチング材のプラズマエッチング方法 |
US8138093B2 (en) * | 2009-08-12 | 2012-03-20 | International Business Machines Corporation | Method for forming trenches having different widths and the same depth |
KR101666645B1 (ko) * | 2010-08-05 | 2016-10-17 | 삼성전자주식회사 | 다양한 소자 분리 영역들을 갖는 반도체 소자의 제조 방법 |
WO2013177576A1 (en) * | 2012-05-25 | 2013-11-28 | The Regents Of The University Of California | Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom |
FR2999335B1 (fr) * | 2012-12-06 | 2016-03-11 | Commissariat Energie Atomique | Procede ameliore de realisation d'un composant a structure suspendue et d'un transistor co-integres sur un meme substrat. |
MX2018002975A (es) * | 2015-10-16 | 2018-06-11 | Ford Global Tech Llc | Sistema y metodo para asistencia de seudonavegacion en un vehículo. |
JP6591291B2 (ja) | 2016-01-07 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10896803B2 (en) | 2016-08-19 | 2021-01-19 | The Regents Of The University Of California | Ion beam mill etch depth monitoring with nanometer-scale resolution |
US10593678B1 (en) * | 2018-08-24 | 2020-03-17 | Micron Technology, Inc. | Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03196624A (ja) * | 1989-12-26 | 1991-08-28 | Sony Corp | ドライエッチング方法 |
JP3229058B2 (ja) | 1993-02-05 | 2001-11-12 | 株式会社リコー | 充填溝分離領域を有する半導体装置の製造方法 |
JP3309620B2 (ja) * | 1995-01-27 | 2002-07-29 | 富士電機株式会社 | ドライエッチングによる部品の製造方法 |
KR0176153B1 (ko) * | 1995-05-30 | 1999-04-15 | 김광호 | 반도체 장치의 소자분리막 및 그 형성방법 |
KR19980030859U (ko) * | 1996-11-29 | 1998-08-17 | 진호선 | 남자용 팬티 |
KR100192178B1 (ko) * | 1996-01-11 | 1999-06-15 | 김영환 | 반도체 소자의 아이솔레이션 방법 |
JPH09289313A (ja) * | 1996-04-19 | 1997-11-04 | Sony Corp | 半導体装置におけるしきい値電圧の設定方法 |
JPH11307627A (ja) * | 1997-08-01 | 1999-11-05 | Nippon Steel Corp | 半導体装置及びその製造方法 |
US6242788B1 (en) * | 1997-08-01 | 2001-06-05 | Nippon Steel Corporation | Semiconductor device and a method of manufacturing the same |
US6303460B1 (en) * | 2000-02-07 | 2001-10-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
KR19990055775A (ko) * | 1997-12-27 | 1999-07-15 | 김영환 | 트랜치를 이용한 반도체 소자의 소자분리 방법 |
US6060370A (en) * | 1998-06-16 | 2000-05-09 | Lsi Logic Corporation | Method for shallow trench isolations with chemical-mechanical polishing |
US6159801A (en) * | 1999-04-26 | 2000-12-12 | Taiwan Semiconductor Manufacturing Company | Method to increase coupling ratio of source to floating gate in split-gate flash |
JP4666700B2 (ja) * | 1999-08-30 | 2011-04-06 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
KR100555490B1 (ko) * | 1999-10-15 | 2006-03-03 | 삼성전자주식회사 | 반도체소자의 트렌치 아이솔레이션 형성 방법 |
JP3485081B2 (ja) * | 1999-10-28 | 2004-01-13 | 株式会社デンソー | 半導体基板の製造方法 |
US6303447B1 (en) * | 2000-02-11 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an extended metal gate using a damascene process |
JP4200626B2 (ja) * | 2000-02-28 | 2008-12-24 | 株式会社デンソー | 絶縁ゲート型パワー素子の製造方法 |
JP2002043413A (ja) | 2000-07-25 | 2002-02-08 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP3601439B2 (ja) * | 2000-10-31 | 2004-12-15 | セイコーエプソン株式会社 | 画像表示装置 |
US6667223B2 (en) * | 2001-07-13 | 2003-12-23 | Infineon Technologies Ag | High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern |
JP2003060024A (ja) * | 2001-08-13 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
JP4129189B2 (ja) * | 2002-02-07 | 2008-08-06 | 東京エレクトロン株式会社 | エッチング方法 |
US7018929B2 (en) * | 2002-07-02 | 2006-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for reducing a low volatility byproduct from a wafer surface following an etching process |
KR100466196B1 (ko) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | 플래시 메모리 제조방법 |
KR100443126B1 (ko) * | 2002-08-19 | 2004-08-04 | 삼성전자주식회사 | 트렌치 구조물 및 이의 형성 방법 |
JP2004087843A (ja) * | 2002-08-27 | 2004-03-18 | Toshiba Corp | 半導体装置 |
JP2004095886A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR100481558B1 (ko) * | 2002-09-09 | 2005-04-08 | 동부아남반도체 주식회사 | 에어 갭 특성을 이용한 반도체 sti 형성 방법 |
US6576558B1 (en) * | 2002-10-02 | 2003-06-10 | Taiwan Semiconductor Manufacturing Company | High aspect ratio shallow trench using silicon implanted oxide |
US7482178B2 (en) * | 2003-08-06 | 2009-01-27 | Applied Materials, Inc. | Chamber stability monitoring using an integrated metrology tool |
JP4564272B2 (ja) | 2004-03-23 | 2010-10-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
US20080166854A1 (en) * | 2005-09-09 | 2008-07-10 | Dong-Suk Shin | Semiconductor devices including trench isolation structures and methods of forming the same |
KR100772704B1 (ko) * | 2005-09-29 | 2007-11-02 | 주식회사 하이닉스반도체 | 테이퍼형태의 트렌치를 갖는 반도체소자의 제조 방법 |
-
2004
- 2004-03-23 JP JP2004085051A patent/JP4564272B2/ja not_active Expired - Lifetime
-
2005
- 2005-03-22 KR KR1020050023520A patent/KR100707899B1/ko active IP Right Grant
- 2005-03-22 US US11/085,112 patent/US20050221579A1/en not_active Abandoned
- 2005-03-23 CN CNB2005100560678A patent/CN100377332C/zh active Active
-
2006
- 2006-12-14 US US11/611,030 patent/US7781293B2/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104217985A (zh) * | 2013-05-31 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件和浅沟槽的制作方法 |
CN105336696A (zh) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | 一种同时改善STI和FG Poly填充孔洞工艺窗口的方法 |
CN105470201A (zh) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | 一种同时改善STI和FG Poly填充空洞的闪存器件工艺方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20060044527A (ko) | 2006-05-16 |
US20070082458A1 (en) | 2007-04-12 |
JP4564272B2 (ja) | 2010-10-20 |
CN100377332C (zh) | 2008-03-26 |
KR100707899B1 (ko) | 2007-04-16 |
US7781293B2 (en) | 2010-08-24 |
US20050221579A1 (en) | 2005-10-06 |
JP2005276930A (ja) | 2005-10-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1674248A (zh) | 半导体器件及其制造方法 | |
US11588032B2 (en) | Three-dimensional semiconductor memory devices and methods of fabricating the same | |
KR102416028B1 (ko) | 3차원 반도체 메모리 장치 및 그 제조 방법 | |
US7550363B2 (en) | Method of fabricating a semiconductor device having first and second trenches using non-concurrently formed hard mask patterns | |
US7999304B2 (en) | Semiconductor device | |
KR20190125811A (ko) | 3차원 반도체 메모리 장치 | |
US10734403B2 (en) | Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same | |
CN107611129B (zh) | 三维非易失性存储器及其制造方法 | |
CN1897255A (zh) | 具有垂直沟道的半导体器件及其制造方法 | |
CN1725515A (zh) | 具有重叠栅电极的半导体器件及其制造方法 | |
CN1812107A (zh) | 半导体器件和半导体器件的制造方法 | |
CN1518089A (zh) | 具有多栅极绝缘层的半导体装置及其制造方法 | |
CN108962973B (zh) | 包括形成有鳍结构的多栅极晶体管的半导体器件 | |
US20110129992A1 (en) | Method for fabricating vertical channel type non-volatile memory device | |
CN101047119A (zh) | 具有球形凹陷栅极的半导体器件的制造方法 | |
CN1873957A (zh) | 分离栅极快闪元件与其制造方法 | |
TWI404195B (zh) | 非揮發性記憶體 | |
JP2008098281A (ja) | 半導体装置の製造方法 | |
CN1941386A (zh) | 半导体器件 | |
CN112687524B (zh) | 一种晶圆弯曲度调整方法 | |
US20060094181A1 (en) | Method for fabricating semiconductor device having a trench structure | |
KR102522161B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
KR20120041523A (ko) | 3차원 반도체 기억 소자의 형성 방법 | |
CN101064284A (zh) | 非易失性存储器的制造方法 | |
KR20120028147A (ko) | 3차원 반도체 장치의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170728 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
|
TR01 | Transfer of patent right | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20211119 Address after: Tokyo Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right |