CN109994550A - 一种低压槽栅超结mos器件 - Google Patents

一种低压槽栅超结mos器件 Download PDF

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CN109994550A
CN109994550A CN201711490285.1A CN201711490285A CN109994550A CN 109994550 A CN109994550 A CN 109994550A CN 201711490285 A CN201711490285 A CN 201711490285A CN 109994550 A CN109994550 A CN 109994550A
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李泽宏
王为
谢驰
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Guizhou Hengxin Microelectronics Technology Co Ltd
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Abstract

本发明提出的一种低压槽栅超结MOS器件，通过第一次外延后的离子注入和第二次外延后离子反扩形成埋层，并与槽栅刻蚀后的离子注入掺杂层相连形成P柱，从而与外延层形成P/N柱交替的超结结构。本发明提出的器件结构相较传统Trench MOS器件具有更高的击穿电压、更低的比导通电阻，且深槽刻蚀后的离子注入掺杂层对沟槽栅氧化层具有缓解电场作用，提高栅氧化层可靠性。本发明超结MOS结构制造工艺简便，与传统Trench MOS器件工艺兼容，只增加两次离子注入，克服了当前超结器件制造流程繁琐，成本高昂的缺点。

Description

一种低压槽栅超结MOS器件
技术领域
本发明属于功率半导体器件技术领域，具体涉及一种低压槽栅超结MOS 器件。
背景技术
超结MOS器件通过在其漂移区中引入P型和N型交替排列的结型耐压层提供横向电场，获得了击穿电压与导通电阻Ron∝BV1.33的新关系，打破了硅基MOS器件极限，大大提高了MOS器件的击穿电压，降低了正向导通损耗。
当前超结MOS器件主要有两种制造方法：一是通过多次外延注入形成超结结构，该方法工艺简单，但流程较繁琐，时间成本较高；二是通过深槽刻蚀和填充完成，该方法较简便，但是需要引入高深宽比刻蚀设备，成本较高。
本发明提出一种低压槽栅超结MOS器件，其可在当前传统Trench MOS工艺设备的基础上完成超结的制造，在保证器件高击穿电压、低导通电阻参数的条件下，显著简化工艺流程、节省生产成本。
发明内容
本发明所要解决的技术问题为提出一种低压槽栅超结MOS器件，以克服当前主流超结制造方法工艺复杂、成本较高等缺点。
为解决当前制造超结MOS器件的两种方法：多次外延注入和深沟槽刻蚀填充技术工艺复杂、成本较高的缺点，本发明提出一种新型低压槽栅超结MOS 器件的制造方法。在生产功率MOS外延片时做一次与外延材料掺杂类型相反的杂质离子注入，之后继续外延至所需的外延层厚度。在挖完深槽后再做一次离子注入，掺杂与外延时注入的离子相同类型的杂质，使得两次注入的掺杂离子相连形成交替排列的P/N柱，之后生长栅氧化层，按传统Trench MOS 的工艺流程制造完毕，即完成超结MOS器件制造。该结构可显著提高器件的击穿电压，降低了器件的比导通电阻，且对于N沟道超结MOS器件，Trench 下的P柱有利于缓解槽栅拐角处的电场，提高栅氧化层可靠性。
本发明的技术方案是，一种低压槽栅超结MOS器件，包括金属化漏端电极1、N+衬底2、位于N+衬底2上方的N-外延层5，外延时通过一次离子注入并反扩形成埋层3，刻蚀完深槽后离子注入形成的掺杂层4，热生长的栅氧化层6，淀积的重掺杂多晶硅7，所述N-外延层上部两侧为P型体区8，所述P 型体区8中设置有相互独立的N+源区9，淀积的硼磷硅玻璃10，上表面金属化源极11。
离子注入外延反扩形成的埋层3和离子注入形成的掺杂层4相连并与外延层5组成P/N柱交替的超结结构。
本发明的有益效果为，一种低压槽栅超结MOS器件，P/N柱交替排列的结型耐压层与深沟槽形成的纵向场板给器件漂移区提供了一个横向电场，显著提高了器件的击穿电压，并减小器件的导通电阻，降低了器件正向导通时的功耗。本发明通过利用外延时离子注入反扩与沟槽刻蚀完后做的离子注入形成超结结构中的P柱，大大简化了超结MOS器件的制造流程、工艺复杂程度并降低了成本。同时深槽刻蚀后离子注入形成的掺杂层能对栅氧化层起到保护作用，提高器件栅氧化层的可靠性。
附图说明
图1是实施例1的结构示意图；
图2-1是本实施例的关键步骤制造流程中在N+衬底上第一次外延N-层的成型图；
图2-2是本实施例的关键步骤制造流程中掩膜版做一次P型离子注入成型图；
图2-3是本实施例的关键步骤制造流程中成埋层成型图；
图2-4是本实施例的关键步骤制造流程中在刻蚀完深槽后再作一次或多次P型离子注入成型图；
图2-5本实施例的关键步骤制造流程中一次或多次离子注入后与P型埋层成型图。
具体实施方式
本发明提出的一种低压槽栅超结MOS器，在传统Trench MOS结构基础上，只增加两次离子注入，可获得高击穿电压、低比导通电阻的超结MOS器件。
实施例：
如图1所示，是本发明提出的一种低压槽栅超结MOS器件的结构示意图。包括金属化漏端电极1、N+衬底2、位于N+衬底2上方的N-外延层5，外延时通过一次离子注入并反扩形成埋层3，刻蚀完深槽后离子注入形成的掺杂层4，热生长的栅氧化层6，淀积的重掺杂多晶硅7，所述N-外延层上部两侧为P型体区8，所述P型体区8中设置有相互独立的N+源区9，淀积的硼磷硅玻璃 10，上表面金属化源极11。
本发明具有与传统TrenchMOS器件相兼容的制造工艺，增加的工艺步骤实现较为简单可靠，但具有比传统Trench MOS器件更高的击穿电压，更低的比导通电阻和更坚固的栅氧化层可靠性。
图2-1至2-5是本实施例的关键步骤制造流程图。图2-1为在N+衬底上第一次外延N-层，图2-2为使用掩膜版做一次P型离子注入，图2-3为继续外延N-层至所需厚度，离子注入的P型杂质反扩形成埋层3，图2-4为在刻蚀完深槽后再作一次或多次P型离子注入，图2-5为一次或多次离子注入后与P型埋层相连形成超结P柱。之后该器件按传统Trench MOS流程制造。
本发明的方案同时适用于P沟道低压槽栅超结MOS器件。所述半导体材料可采用体硅、碳化硅、砷化镓、磷化铟或锗硅。
尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种低压槽栅超结MOS器件，其特征在于：包括金属化漏端电极（1）、N+衬底（2）、位于N+衬底（2）上方的N-外延层（5），外延时通过一次离子注入并反扩形成埋层（3），刻蚀完深槽后离子注入形成的掺杂层（4），热生长的栅氧化层（6）和淀积的重掺杂多晶硅（7），所述N-外延层上部两侧为P型体区（8），所述P型体区（8）中设置有相互独立的N+源区（9），淀积的硼磷硅玻璃（10）和上表面金属化源极（11）。
2.根据权利要求1所述的低压槽栅超结MOS器件，其特征在于：离子注入外延反扩形成的埋层3和离子注入形成的掺杂层4相连并与外延层5组成P/N柱交替的超结结构。
3.根据权利要求1或2所述的低压槽栅超结MOS器件，其特征在于：所述半导体材料可采用体硅、碳化硅、砷化镓、磷化铟或锗硅。
CN201711490285.1A 2017-12-30 2017-12-30 一种低压槽栅超结mos器件 Pending CN109994550A (zh)

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CN114242768A (zh) * 2021-11-18 2022-03-25 深圳真茂佳半导体有限公司 栅底电荷平衡改善的碳化硅mosfet器件及制造方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

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CN207993871U (zh) * 2017-12-30 2018-10-19 贵州恒芯微电子科技有限公司 一种低压槽栅超结mos器件

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CN207993871U (zh) * 2017-12-30 2018-10-19 贵州恒芯微电子科技有限公司 一种低压槽栅超结mos器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242768A (zh) * 2021-11-18 2022-03-25 深圳真茂佳半导体有限公司 栅底电荷平衡改善的碳化硅mosfet器件及制造方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

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