CN114005877A - 一种超薄超结igbt器件及制备方法 - Google Patents
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Abstract
本发明公开了一种超薄超结IGBT器件及制备方法，包括：金属化集电极；位于所述金属化集电极上的P型集电区；位于所述P型集电区上方的N型FS层；位于所述N型FS层上方的N型FS隔离层；位于所述N型FS隔离层上方的第一N型外延层及位于所述第一N型外延层上方的第二N型外延层；位于所述第二N型外延层中的MOS结构。根据本发明，减薄芯片厚度，降低器件正向导通压降和开关损耗，同时降低器件热阻，提升导通电流能力。
Description
技术领域
本发明涉及功率半导体技术领域，特别涉及一种超薄超结IGBT器件及制备方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)器件因具有与功率MOS器件类似的输入电阻高、击穿电压高、安全工作区宽、易驱动等优点，同时具有双极型器件导通电压低等优势，广泛应用于太阳能逆变器、新能源汽车、高压直流输电***、高速铁路等领域，是当今中大功率电力电子***的核心器件。当前英飞凌IGBT技术已发展至第七代，采用精细化图形沟槽栅(Micro Pattern Trench,MPT)、场阻止(Field Stop,FS)、载流子存储(Carrier Storage,CS)、注入增强(Injection Enhanced，IE)等技术，获得导通压降、开关损耗和安全工作区较好的折中。但受限于硅极限，650V级IGBT承受电压时耐压层的厚度在60μm左右，如图1所示，这使得器件难以进一步减薄降低导通电阻和开关损耗，并提升其电流能力。
超结IGBT器件是最近几年学术界与工业界研究的热门器件，其是在传统IGBT器件结构基础上在外延层增加重复排列的PN柱的新型功率半导体器件。PN柱形成的超结结构对器件耐压和正向导通压降等参数的优化与超结MOS器件有类似的效果。PN柱的引入使得超结IGBT器件在正向耐压时，除了Pbody-N-Drift结的纵向电场外，PN柱的相互耗尽产生横向电场，将传统IGBT器件三角形电场分布调制成近似于矩形分布，大大提高了超结IGBT器件的耐压能力。在保证器件一定击穿电压的前提下，就可以显著增大N-Drift层的浓度，从而显著降低正向导通压降，帮助超结IGBT器件在应用时显著降低导通损耗。同等电流规格下，超结IGBT器件的面积能大大减小，降低芯片成本。当前，深槽刻蚀和填充工艺是制造超结IGBT器件的两种制造方法之一。深槽刻蚀和填充方式工艺流程较为简单，但对刻蚀设备要求较高。受制于刻蚀设备的原因，在深槽刻蚀时，槽不是完美的矩形结构，随着反应离子刻蚀的深入，槽宽会逐渐减小，形成上宽下窄的锥形结构。填充P型硅单晶后，P柱狭窄的底部与N-Drift区在耐压时容易形成电场聚集，因此对于650V常规SJ-IGBT，如图2所示，整个P柱的长度一般不低于45μm以保证器件的耐压能力，外加正面MOS结构和背面集电极结构，总厚度一般也不低于60μm。这些都限制了IGBT器件的导通电压和开关损耗的进一步降低。
发明内容
针对现有技术中存在的不足之处，本发明的目的是提供一种超薄超结IGBT器件及制备方法，减薄芯片厚度，降低器件正向导通压降和开关损耗，同时降低器件热阻，提升导通电流能力。为了实现根据本发明的上述目的和其他优点，提供了一种超薄超结IGBT器件，包括：
金属化集电极；
位于所述金属化集电极上的P型集电区；
位于所述P型集电区上方的N型FS层；
位于所述N型FS层上方的N型FS隔离层；
位于所述N型FS隔离层上方的第一N型外延层及位于所述第一N型外延层上方的第二N型外延层；位于所述第二N型外延层中的MOS结构。
优选的，所述第一N型外延层中一相对的两侧通过深槽刻蚀回填工艺形成P柱。
优选的，所述第二N型外延层中包括通过反应离子刻蚀形成的沟槽、位于所述沟槽内设置的热生长的栅氧化层、位于所述栅氧化层内淀积的重掺杂多晶硅及通过自对准工艺形成的P型体区，所述P柱与P型体区不连接。
优选的，还包括位于所述沟槽两侧且位于P型体区内设置的相互独立的N型发射区，所述第二N型外延层上方淀积的硼磷硅玻璃及位于所述硼磷硅玻璃上方的金属化发射极。
优选的，还包括衬底，所述衬底为N型任意掺杂浓度或为P型任意掺杂浓度，且IGBT器件还可以适用P型沟道超结IGBT、碳化硅或氮化镓的半导体材料。
优选的，不包括衬底，通过采用区融单晶硅为所述第一N型外延层。
优选的，且IGBT器件背面的N型FS隔离层可注入或者不注入，注入时的离子为磷、砷、氢或氦。
优选的，所述第二N型外延层通过外延形成或者通过在第一N型外延层结构上由深槽刻蚀和回填形成P柱，再通过N型高能注入将第一N型外延层中顶部的P柱部分补偿为N型形成。
优选的，所述IGBT器件的背面研磨至P柱底端后继续研磨数微米，之后进行N型FS层和P型集电区的注入。
一种超薄超结IGBT器件的制备方法，包括以下步骤：
S1、通过在任意的衬底片形成第一N型外延层，且在所述第一N型外延层上采用反应离子刻蚀工艺形成深槽，并采用回填P型硅单晶形成P柱；
S2、位于所述第一N型外延层上方形成第二N型外延层，且在所述第二N型外延层上通过反应离子刻蚀形成的沟槽，进而位于所述沟槽内通过干法氧化方式热生长的栅氧化层，位于所述栅氧化层内淀积重掺杂多晶硅并反刻形成多晶硅栅极；
S3、通过自对准工艺、采用离子注入和高温推阱形成P型体区，位于P型体区内设置通过光刻注入形成N型发射区；
S4、位于第二N型外延层上方淀积的硼磷硅玻璃，进行高温回流，且位于所述硼磷硅玻璃上方的进行接触孔光刻，并刻蚀3000-5000A厚度的硅，并淀积上表面金属形成金属化发射极；
S5、将衬底翻转后进行减薄，研磨至P柱底部后继续研磨数微米，进行第一次N型FS层注入；
S6、继续进行第二次N型FS隔离层注入和杂质激活；
S7、位于P型集电区的一面上进行P型集电区注入并退火；
S8、位于P型集电区的一面上金属层淀积，形成金属化集电极。
本发明与现有技术相比，其有益效果是：采用在衬底硅片上外延第一N型外延层并通过深槽刻蚀和回填工艺形成超结结构，通过第二次外延形成表面MOS结构，并形成浮空P柱。背面减薄将器件研磨至P柱底部，并再减薄数微米去除P柱部分窄的底部，降低器件耐压时此处的电场聚集。背面注入N型杂质形成FS层，背注P型杂质形成集电区，再次注入氢离子形成FS隔离层，补偿P柱至N型。背面溅射金属完成器件的制造。浮空P柱保证器件工作在电导调制模式，降低器件正向导通压降。氢离子注入形成的N型FS隔离层在关断时可降低开关损耗。减薄至去除P柱部分底部区域可降低器件耐压时的电场聚集，保证器件足够的击穿电压的同时也减小了N-Drift区的厚度，可降低器件正向导通压降，减小开关损耗。更薄的芯片厚度降低了器件的热阻，提升了器件的电流能力。本发明提供的一种650V级超薄超结IGBT芯片厚度可减薄至45μm，击穿电压大于700V，正向导通压降比同类型常规超结IGBT降低至少0.1V，开关损耗及热阻均降低10％以上，显著提升了超结IGBT器件的电流能力。
附图说明
图1为常规Trench FS-IGBT器件结构示意图；
图2为常规超结IGBT器件结构示意图；
图3为根据本发明的超薄超结IGBT器件及制备方法的结构示意图；
图4为根据本发明的超薄超结IGBT器件及制备方法的一实施例结构示意图；
图5-1-15为根据本发明的超薄超结IGBT器件及制备方法的制备步骤结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参照图1-5，一种超薄超结IGBT器件，包括：金属化集电极1；
位于所述金属化集电极1上的P型集电区2；
位于所述P型集电区2上方的N型FS层3；
位于所述N型FS层3上方的N型FS隔离层4；
位于所述N型FS隔离层4上方的第一N型外延层5及位于所述第一N型外延层5上方的第二N型外延层6，位于所述第二N型外延层中的MOS结构，氢离子注入形成的N型FS隔离层在关断时可降低开关损耗。
进一步的，所述第一N型外延层5中一相对的两侧通过深槽刻蚀回填工艺形成P柱101，P柱保证器件工作在电导调制模式，降低器件正向导通压降。
进一步的，所述第二N型外延层6中包括通过反应离子刻蚀形成的沟槽7、位于所述沟槽7内设置的热生长的栅氧化层8、位于所述栅氧化层8内淀积的重掺杂多晶硅9及通过自对准工艺形成的P型体区10，所述P柱101与P型体区10不连接。
进一步的，还包括位于所述沟槽7两侧且位于P型体区10内设置的相互独立的N型发射区11，所述第二N型外延层6上方淀积的硼磷硅玻璃12及位于所述硼磷硅玻璃12上方的金属化发射极13。
进一步的，还包括衬底，所述衬底为N型任意掺杂浓度或为P型任意掺杂浓度，且IGBT器件还可以适用P型沟道超结IGBT、碳化硅或氮化镓的半导体材料。
进一步的，不包括衬底，通过采用区融单晶硅为所述第一N型外延层5。
进一步的，且IGBT器件背面的N型FS隔离层4可注入或者不注入，注入时的离子为磷、砷、氢或氦，所述IGBT器件背面为设置有N型FS隔离层4的一面。
进一步的，所述第二N型外延层6通过外延形成或者通过在第一N型外延层5结构上由深槽刻蚀和回填形成P柱101，再通过N型高能注入将第一N型外延层5中顶部的P柱部分补偿为N型形成。
进一步的，所述IGBT器件的背面研磨至P柱101底端后继续研磨数微米，之后进行N型FS层3和P型集电区2的注入，IGBT器件背面减薄后，只做一次N型FS层注入，就可达到P型集电区2与P柱101的隔离，而且减薄至去除P柱部分底部区域可降低器件耐压时的电场聚集，保证器件足够的击穿电压的同时也减小了N-Drift区的厚度，可降低器件正向导通压降，减小开关损耗。更薄的芯片厚度降低了器件的热阻，提升了器件的电流能力。
参照图5-1-15一种超薄超结IGBT器件的制备方法，包括以下步骤：
S1、通过在任意的衬底片形成第一N型外延层5，且在所述第一N型外延层5上采用反应离子刻蚀工艺形成深槽，并采用回填P型硅单晶形成P柱101；
S2、位于所述第一N型外延层5上方形成第二N型外延层6，且在所述第二N型外延层6上通过反应离子刻蚀形成的沟槽7，进而位于所述沟槽7内通过干法氧化方式热生长的栅氧化层8，位于所述栅氧化层8内淀积重掺杂多晶硅并反刻形成多晶硅栅极9；
S3、通过自对准工艺、采用离子注入和高温推阱形成P型体区10，位于P型体区10内设置通过光刻注入形成N型发射区11；
S4、位于第二N型外延层6上方淀积的硼磷硅玻璃12，进行高温回流，且位于所述硼磷硅玻璃12上方的进行接触孔光刻，并刻蚀3000-5000A厚度的硅，并淀积上表面金属形成金属化发射极13；
S5、将衬底翻转后进行减薄，研磨至P柱101底部后继续研磨数微米，进行第一次N型FS层3注入；
S6、继续进行第二次N型FS隔离层4注入和杂质激活；
S7、位于P型集电区2的一面上进行P型集电区2注入并退火；
S8、位于P型集电区2的一面上金属层淀积，形成金属化集电极1。
这里说明的设备数量和处理规模是用来简化本发明的说明的，对本发明的应用、修改和变化对本领域的技术人员来说是显而易见的。
尽管本发明的实施方案已公开如上，但其并不仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。
Claims (10)
1.一种超薄超结IGBT器件，其特征在于，包括：
金属化集电极(1)；
位于所述金属化集电极(1)上的P型集电区(2)；
位于所述P型集电区(2)上方的N型FS层(3)；
位于所述N型FS层(3)上方的N型FS隔离层(4)；
位于所述N型FS隔离层(4)上方的第一N型外延层(5)及位于所述第一N型外延层(5)上方的第二N型外延层(6)；位于所述第二N型外延层中的MOS结构。
2.如权利要求1所述的一种超薄超结IGBT器件，其特征在于，所述第一N型外延层(5)中一相对的两侧通过深槽刻蚀回填工艺形成P柱(101)。
3.如权利要求2所述的一种超薄超结IGBT器件，其特征在于，所述第二N型外延层(6)中包括通过反应离子刻蚀形成的沟槽(7)、位于所述沟槽(7)内设置的热生长的栅氧化层(8)、位于所述栅氧化层(8)内淀积的重掺杂多晶硅(9)及通过自对准工艺形成的P型体区(10),所述P柱(101)与P型体区(10)不连接。
4.如权利要求3所述的一种超薄超结IGBT器件，其特征在于，还包括位于所述沟槽(7)两侧且位于P型体区(10)内设置的相互独立的N型发射区(11)，所述第二N型外延层(6)上方淀积的硼磷硅玻璃(12)及位于所述硼磷硅玻璃(12)上方的金属化发射极(13)。
5.如权利要求4所述的一种超薄超结IGBT器件，其特征在于，还包括衬底，所述衬底为N型任意掺杂浓度或为P型任意掺杂浓度，且IGBT器件还可以适用P型沟道超结IGBT、碳化硅或氮化镓的半导体材料。
6.如权利要求1所述的一种超薄超结IGBT器件，其特征在于，不包括衬底，通过采用区融单晶硅为所述第一N型外延层(5)。
7.如权利要求6所述的一种超薄超结IGBT器件，其特征在于，IGBT器件背面的N型FS隔离层(4)可注入或者不注入，注入时的离子为磷、砷、氢或氦。
8.如权利要求7所述的一种超薄超结IGBT器件，其特征在于，所述第二N型外延层(6)通过外延形成或者通过在第一N型外延层(5)结构上由深槽刻蚀和回填形成P柱(101)，再通过N型高能注入将第一N型外延层(5)中顶部的P柱部分补偿为N型形成。
9.如权利要求8所述的一种超薄超结IGBT器件，其特征在于，所述IGBT器件的背面研磨至P柱(101)底端后继续研磨数微米，之后进行N型FS层(3)和P型集电区(2)的注入。
10.如权利要求9所述的一种超薄超结IGBT器件的制备方法，其特征在于，包括以下步骤：
S1、通过在任意的衬底片形成第一N型外延层(5)，且在所述第一N型外延层(5)上采用反应离子刻蚀工艺形成深槽，并采用回填P型硅单晶形成P柱(101)；
S2、位于所述第一N型外延层(5)上方形成第二N型外延层(6)，且在所述第二N型外延层(6)上通过反应离子刻蚀形成的沟槽(7)，进而位于所述沟槽(7)内通过干法氧化方式热生长的栅氧化层(8)，位于所述栅氧化层(8)内淀积重掺杂多晶硅并反刻形成多晶硅栅极(9)；
S3、通过自对准工艺、采用离子注入和高温推阱形成P型体区(10)，位于P型体区(10)内设置通过光刻注入形成N型发射区(11)；
S4、位于第二N型外延层(6)上方淀积的硼磷硅玻璃(12)，进行高温回流，且位于所述硼磷硅玻璃(12)上方的进行接触孔光刻，并刻蚀3000-5000A厚度的硅，并淀积上表面金属形成金属化发射极(13)；
S5、将衬底翻转后进行减薄，研磨至P柱(101)底部后继续研磨数微米，进行第一次N型FS层(3)注入；
S6、继续进行第二次N型FS隔离层(4)注入和杂质激活；
S7、位于P型集电区(2)的一面上进行P型集电区(2)注入并退火；
S8、位于P型集电区(2)的一面上金属层淀积，形成金属化集电极(1)。
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| CN116469911A (zh) * | 2022-09-09 | 2023-07-21 | 苏州华太电子技术股份有限公司 | 一种igbt器件 |
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| CN116364772A (zh) * | 2023-04-11 | 2023-06-30 | 上海超致半导体科技有限公司 | 一种超结igbt功率器件及制备方法 |
| CN116364772B (zh) * | 2023-04-11 | 2024-01-30 | 上海超致半导体科技有限公司 | 一种超结igbt功率器件及制备方法 |
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