CN104979404A - 一种具有阶梯场氧的横向双扩散金属氧化物半导体场效应管 - Google Patents
一种具有阶梯场氧的横向双扩散金属氧化物半导体场效应管 Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 13
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 title abstract description 5
- 239000001301 oxygen Substances 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000009826 distribution Methods 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 25
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
本发明提出了一种新型超结横向双扩散金属氧化物半导体场效应管(SJ-LDMOS),包括在LDMOS漂移区的表面形成SJ层,并利用两步浅槽隔离(STI)技术在Super Junction上方形成阶梯场氧化层的新型半导体器件,一方面利用电场调制效应使器件表面的电场分布更加均匀,从而增加器件的击穿电压;另一方面由于阶梯场氧化层靠近器件沟道处的较薄氧化层厚度较小,在开启状态下场板下方的漂移区表面存在更多的多数载流子积累,并且在薄阶梯氧化层下方器件纵向的电流通道变宽从而大幅度地降低了器件的导通电阻。
Description
技术领域
本发明涉及半导体器件领域,特别是涉及一种横向双扩散金属氧化物半导体场效应管。
背景技术
将超结SJ(Super Junction)技术应用于LDMOS(Lateral Double-diffusedMOSFET)形成SJ-LDMOS结构是LDMOS器件研究的热点。由于SJ-LDMOS在一定的击穿电压BV(Breakdown Voltage)条件下具有非常低的导通电阻RON,打破了传统功率MOS器件的极限关系,已被广泛应用于超低功耗PIC(Power Integrated Circuit)设计中。然而在SJ-LDMOS实现的过程中遇到了许多问题,包括衬底辅助耗尽效应SAD(Substrate Assisted Depletion),即在P型硅衬底上实现的SJ-LDMOS,由于N柱漂移区同时被相邻P柱和P型衬底辅助耗尽,导致Super Junction的电荷不能完全补偿,造成BV大幅度降低。
具有缓冲层(Buffer)SJ-LDMOS结构能够有效地减少衬底辅助耗尽的影响,并且该结构与传统BCD(Bipolar-CMOS-DMOS)工艺兼容。在传统的BCD工艺中,制造Buffer SJ-LDMOS漂移区场氧和器件之间隔离氧化层时采用硅的局部氧化LOCOS(Local Oxidation of Silicon)技术。由于LOCOS的高温工艺一方面会使超结的N柱与P柱相互扩散严重增加,另一方面由于场氧化层生长的过程中吸硼排磷的效应使超结的N柱与P柱浓度不相同,导致电荷不能完全补偿,从而使得器件的电学特性较差。
浅槽隔离STI(Shallow Trench Isolation)技术与LOCOS技术相比工作温度较低,可以很好地解决以上问题。然而在采用STI BCD工艺制造SJ-LDMOS过程中,为了降低工艺成本,在漂移区上场氧化层的厚度是由器件之间的隔离深度决定的,SJ-LDMOS的性能受到了器件BCD工艺的限制。虽然器件之间的厚场氧化层满足隔离的条件,但是器件的性能并没有得到很好的优化,在提高器件耐压的同时比导通电阻也大幅度增加。
发明内容
本发明提出了一种横向双扩散金属氧化物半导体场效应管,旨在有效优化SJ-LDMOS击穿电压与比导通电阻的矛盾。
本发明的技术方案如下:
横向双扩散金属氧化物半导体场效应晶体管,包括:
半导体材料的衬底;
在所述衬底上生长的外延层,作为缓冲层;
在所述外延层上形成相邻接的基区和漂移区,漂移区注入N柱和P柱相间排列形成超结漂移区;
位于超结漂移区上相邻接的场氧化层和漏区,其中场氧化层与沟道保持间距;
在所述基区上利用双扩散技术形成的沟道,在所述基区上形成沟道衬底接触并与靠近沟道一侧短接形成源区;
位于沟道上方的栅绝缘层以及栅极;
分别在源区和漏区上形成的源极和漏极;
在以上与现有技术相同的结构基础上,本发明的结构改变主要是:
所述场氧化层为阶梯型,即其中靠近沟道的区域为深度较浅的薄场氧化层,靠近以及邻接漏区的区域为深度较深的厚场氧化层;所述栅绝缘层以及栅极自沟道上方延展覆盖至薄场氧化层的部分。
基于上述基本方案,本发明还进一步做如下优化限定和改进:
薄场氧化层的厚度约为厚场氧化层的厚度的1/2时,器件的特性为最优。
阶梯场氧化层的厚场氧化层根据器件的具体耐压要求设计特定的厚度,例如:当器件耐压为100~300V时,厚场氧化层的厚度约为1μm;当器件耐压为300~700V时,厚场氧化层的厚度约为1.5μm。
当阶梯场氧化层的阶梯拐角位置为器件漂移区的中间位置附近时,器件的性能最优。
相应的,制作本发明的场效应管器件的方法的特别之处就在于:在形成有源区时,首先在超结漂移区表面靠近沟道的区域利用STI技术形成深度较浅的薄场氧化层,保证栅绝缘层以及栅极自沟道上方延展覆盖至薄场氧化层的部分;然后在超结漂移区表面靠近漏端的区域以及多个所述横向双扩散金属氧化物半导体场效应管(注:通常制作此类器件都是多个器件共同制作)之间的相互隔离处利用STI技术形成深度较深的厚场氧化层,即在超结漂移区的表面形成阶梯状的场氧化层。
本发明技术方案的有益效果如下:
本发明在LDMOS的漂移区表面形成Super Junction,一方面降低了漂移区的导通电阻;另一方面消除了衬底辅助耗尽效应,使得器件具有很高的击穿电压。在器件漂移区上方,形成阶梯场氧化层,是对传统漂移区上具有单层厚氧化层SJ-LDMOS的改进和创新。
在SJ-LDMOS漂移区的表面通过两步STI技术形成阶梯场氧化层。一方面,阶梯场氧化层对器件漂移区的表面电场进行调制,使得漂移区的表面电场分布更加均匀,从而有效的提高了器件击穿电压。另一方面,由于靠近沟道处的场氧化层变薄,在开启状态下场板下方的漂移区表面存在更高浓度的多数载流子积累,并且在较薄阶氧化层下方器件纵向方向上的电流通道变宽,从而大幅度地降低了器件的导通电阻,使得器件的整体性能得到优化。
附图说明
图1为本发明实施例的结构示意图(正视图);
图2为本发明实施例的三维剖视示意图(为了便于标注,对超结、漂移区绝缘层以及阶梯场氧化层等作了部分立体断面);
附图标号说明:
1-源极;2-栅极,包括延伸到场氧化层上方部分形成的场板;3-栅绝缘层;4-阶梯场氧化层;5-漏电极;6-漏区;7-N柱与P柱相间形成的超结漂移区;8-缓冲层;9-衬底;10-基区;11-源区;12-沟道;
具体实施方式
如图1所示,本发明具有阶梯场氧的横向双扩散金属氧化物半导体场效应管结构包括:
半导体材料的衬底9;
位于衬底上的外延层作为器件的缓冲层8;
分别位于缓冲层8上两端的基区10和漏区6,漏区上面为漏极5;
位于基区表面的源区11和沟道12;
源区表面形成源极1,沟道12上面为栅绝缘层3位于栅极2下方;
沟道与漏区之间漂移区表面形成N柱和P柱相间排列的超结漂移区7;
超结漂移区7上方为阶梯场氧化层4;
薄场氧化层的厚度为41,厚场氧化层的厚度为42。
在LDMOS漂移区的表面形成Super Junction层,可以有效降低漂移区的导通电阻。又由于Super Junction下方为缓冲层,可以有效解决衬底辅助耗尽效应,使得器件具有很高的击穿电压。为了进一步优化器件的特性,解决场氧化层厚度受到器件之间隔离氧化层厚度限制的问题,利用两步STI技术在超结漂移区上形成阶梯场氧化层。根据电场调制原理,阶梯场氧化层对漂移区表面的电场进行调制,使其电场分布更加均匀,进一步提高了器件的击穿电压。又由于靠近沟道的薄场氧化层厚度较小,在漂移区表面场板下方区域多数载流积累的浓度增加,并且在薄场氧化层下方电流的导通路径变宽,从而大幅度地降低了器件的导通电阻。
以N沟道LDMOS为例,具体可以通过以下步骤进行制备:
1)半绝缘材料(包括Si、SiC和GaAs等)的衬底上外延N型缓冲层;
2)在缓冲层上左端形成P型基区;
3)自基区至漏区注入若干相间排列的高浓度的N柱和P柱,形成超结漂移区;
4)利用两步STI技术,形成有源区同时在超结漂移区上形成阶梯场氧化层;场氧化层的阶梯拐角位置为超结漂移区的中点位置;其中,薄场氧化层的厚度为厚场氧化层的厚度的1/2;耐压要求为100~300V时,厚场氧化层的厚度为1μm;耐压要求为300~700V时,厚场氧化层的厚度为1.5μm;
5)在沟道上面形成栅氧化层并淀积多晶硅、刻蚀多晶硅和栅氧化层,形成栅极;
6)在基区利用双扩散技术注入形成沟道,同时在右端注入形成漏区;
7)在基区左端形成沟道衬底接触;
8)在器件表面淀积钝化层,并刻蚀接触孔;
9)淀积金属并刻蚀形成漏极和源极。
经实验,该器件的性能较之于传统器件大幅度提升,在两种器件漂移区长度相同的情况下该器件的击穿电压提高约25%;在两种器件击穿电压相同的情况下比导通电阻下降约30%。
当然,本发明中的LDMOS也可以为P型沟道,其结构与N沟道LDMOS等同,亦应属于本申请权利要求的保护范围,在此不再赘述。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和替换,这些改进和替换的方案也落入本发明的保护范围。
Claims (5)
1.一种横向双扩散金属氧化物半导体场效应晶体管,包括:
半导体材料的衬底;
在所述衬底上生长的外延层,作为缓冲层;
在所述外延层上形成相邻接的基区和漂移区,漂移区注入N柱和P柱相间排列形成超结漂移区;
位于超结漂移区上相邻接的场氧化层和漏区,其中场氧化层与沟道保持间距;
在所述基区上利用双扩散技术形成的沟道,在所述基区上形成沟道衬底接触并与靠近沟道一侧短接形成源区;
位于沟道上方的栅绝缘层以及栅极;
分别在源区和漏区上形成的源极和漏极;
其特征在于:
所述场氧化层为阶梯型,即其中靠近沟道的区域为深度较浅的薄场氧化层,靠近以及邻接漏区的区域为深度较深的厚场氧化层;所述栅绝缘层以及栅极自沟道上方延展覆盖至薄场氧化层的部分。
2.根据权利要求1所述的横向双扩散金属氧化物半导体场效应管,其特征在于:薄场氧化层的厚度为厚场氧化层的厚度的1/2。
3.根据权利要求1所述的横向双扩散金属氧化物半导体场效应管,其特征在于:耐压要求为100~300V时,厚场氧化层的厚度为1μm;耐压要求为300~700V时,厚场氧化层的厚度为1.5μm。
4.根据权利要求1所述的横向双扩散金属氧化物半导体场效应管,其特征在于:所述场氧化层的阶梯拐角位置为超结漂移区的中点位置。
5.一种制作权利要求1所述的横向双扩散金属氧化物半导体场效应管的方法,包括以下步骤:
1)在半导体材料的衬底上外延缓冲层;
2)在缓冲层上左端形成基区;
3)从基区到右端生成超结漂移区,即交替注入高浓度的N柱和P柱;
4)形成有源区同时在超结漂移区上形成场氧化层;
5)在沟道上面形成栅氧化层并淀积多晶硅、刻蚀多晶硅和栅氧化层,形成栅极;
6)在基区利用双扩散技术注入形成沟道,同时在超结漂移区的右端注入形成漏区;
7)在基区左端形成沟道衬底接触;
8)在整个表面淀积钝化层,并刻蚀接触孔;
9)淀积金属并刻蚀形成漏极和源极;
其特征在于:
在形成有源区时,首先在超结漂移区表面靠近沟道的区域利用STI技术形成深度较浅的薄场氧化层,保证栅绝缘层以及栅极自沟道上方延展覆盖至薄场氧化层的部分;然后在超结漂移区表面靠近漏端的区域以及多个所述横向双扩散金属氧化物半导体场效应管之间的相互隔离处利用STI技术形成深度较深的厚场氧化层,即在超结漂移区的表面形成阶梯状的场氧化层。
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100163992A1 (en) * | 2008-12-31 | 2010-07-01 | Kim Mi-Young | Semiconductor device and method for fabricating the same |
US20100270616A1 (en) * | 2009-04-24 | 2010-10-28 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
CN101916779A (zh) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | 可完全消除衬底辅助耗尽效应的soi超结ldmos结构 |
CN102244092A (zh) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | 一种横向高压功率半导体器件的结终端结构 |
CN102254946A (zh) * | 2011-01-11 | 2011-11-23 | 苏州英诺迅科技有限公司 | 一种射频横向扩散n型mos管及其制造方法 |
CN102361031A (zh) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | 一种用于soi高压集成电路的半导体器件 |
-
2015
- 2015-05-22 CN CN201510267184.2A patent/CN104979404A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100163992A1 (en) * | 2008-12-31 | 2010-07-01 | Kim Mi-Young | Semiconductor device and method for fabricating the same |
US20100270616A1 (en) * | 2009-04-24 | 2010-10-28 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
CN101916779A (zh) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | 可完全消除衬底辅助耗尽效应的soi超结ldmos结构 |
CN102254946A (zh) * | 2011-01-11 | 2011-11-23 | 苏州英诺迅科技有限公司 | 一种射频横向扩散n型mos管及其制造方法 |
CN102244092A (zh) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | 一种横向高压功率半导体器件的结终端结构 |
CN102361031A (zh) * | 2011-10-19 | 2012-02-22 | 电子科技大学 | 一种用于soi高压集成电路的半导体器件 |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US12040396B2 (en) * | 2020-10-29 | 2024-07-16 | United Microelectronics Corp. | High voltage semiconductor device including buried oxide layer |
US20230207692A1 (en) * | 2020-10-29 | 2023-06-29 | United Microelectronics Corp. | High voltage semiconductor device including buried oxide layer |
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