CN109686781B - 一种多次外延的超结器件制作方法 - Google Patents
一种多次外延的超结器件制作方法 Download PDFInfo
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- CN109686781B CN109686781B CN201811529741.3A CN201811529741A CN109686781B CN 109686781 B CN109686781 B CN 109686781B CN 201811529741 A CN201811529741 A CN 201811529741A CN 109686781 B CN109686781 B CN 109686781B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000407 epitaxy Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 39
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 10
- 210000000746 body region Anatomy 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 238000011084 recovery Methods 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
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Priority Applications (1)
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CN201811529741.3A CN109686781B (zh) | 2018-12-14 | 2018-12-14 | 一种多次外延的超结器件制作方法 |
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CN201811529741.3A CN109686781B (zh) | 2018-12-14 | 2018-12-14 | 一种多次外延的超结器件制作方法 |
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CN109686781A CN109686781A (zh) | 2019-04-26 |
CN109686781B true CN109686781B (zh) | 2021-08-03 |
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110010694B (zh) * | 2019-05-07 | 2024-03-12 | 无锡紫光微电子有限公司 | 一种高压多次外延型超结mosfet的结构及制造方法 |
CN110010693B (zh) * | 2019-05-07 | 2024-03-12 | 无锡紫光微电子有限公司 | 一种高压深沟槽型超结mosfet的结构及其制作方法 |
CN110299402A (zh) * | 2019-07-25 | 2019-10-01 | 无锡昌德微电子股份有限公司 | 一种vdmos及其制造方法 |
CN111223915B (zh) * | 2020-01-16 | 2024-07-05 | 无锡新洁能股份有限公司 | 多次外延超结器件结构及其制造方法 |
CN112038236B (zh) * | 2020-09-10 | 2022-03-15 | 深圳市芯电元科技有限公司 | 一种沟槽mosfet的制造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP5659558B2 (ja) * | 2010-05-20 | 2015-01-28 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
JP5560931B2 (ja) * | 2010-06-14 | 2014-07-30 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
US8785306B2 (en) * | 2011-09-27 | 2014-07-22 | Alpha And Omega Semiconductor Incorporated | Manufacturing methods for accurately aligned and self-balanced superjunction devices |
US20140001514A1 (en) * | 2012-07-02 | 2014-01-02 | Infineon Technologies Ag | Semiconductor Device and Method for Producing a Doped Semiconductor Layer |
JP6375743B2 (ja) * | 2014-07-15 | 2018-08-22 | 富士電機株式会社 | 半導体装置の製造方法 |
CN107799419A (zh) * | 2016-08-31 | 2018-03-13 | 无锡华润华晶微电子有限公司 | 超级结功率器件及其制备方法 |
CN207587736U (zh) * | 2017-09-14 | 2018-07-06 | 中航(重庆)微电子有限公司 | 一种超结器件 |
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Effective date of registration: 20240613 Address after: 100000 106A, Floor 1, B-1, Zhongguancun Dongsheng Science Park, 66 Xixiaokou Road, Haidian District, Northern Territory, Beijing Patentee after: ZIGUANG TONGXIN MICROELECTRONICS CO.,LTD. Country or region after: China Address before: 214135 Jiangsu Wuxi New District, 200, Linghu Road, China, four floor, D2 International Innovation Park, China sensor network. Patentee before: WUXI UNIGROUP MICROELECTRONICS CO.,LTD. Country or region before: China |