CN105376512A - Signal conversion device based on programmable logic device - Google Patents
Signal conversion device based on programmable logic device Download PDFInfo
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- CN105376512A CN105376512A CN201510796032.1A CN201510796032A CN105376512A CN 105376512 A CN105376512 A CN 105376512A CN 201510796032 A CN201510796032 A CN 201510796032A CN 105376512 A CN105376512 A CN 105376512A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Chemical & Material Sciences (AREA)
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Abstract
The invention discloses a signal conversion device based on a programmable logic device, which achieves conversion from a LVDS signal to a DP signal. The signal conversion device based on the programmable logic device comprises a signal processing unit, a LVDS signal input interface and a DP signal output interface, wherein the signal processing unit is integrated in the programmable logic device; the programmable logic device is provided with a LVDS input terminal coupled with the LVDS signal input interface and a DP output terminal coupled with the DP signal output interface; the signal processing unit is used for converting the LVDS signal into the DP signal. The signal conversion device based on the programmable logic device, which is provided by the invention, supports the DP1.2 protocol, solves a problem that the current LVDS-signal-to-DP-signal transmission protocol is over low in support, and can meet a requirement that the current video needs to support high resolution.
Description
Technical field
The invention belongs to signal processing technology field, more specifically, relate to a kind of chromacoder based on programmable logic device.
Background technology
Along with the development of video display technology, screen resolution has brought up to present 4k*2K, 8K*4K from initial 720P, 1080P, and picture refreshing rate has also risen to present 120Hz, 240Hz from initial 30Hz, 60Hz.In order to meet high-resolution display requirement, display transmission technology is in continuous renewal, support that the LVDS transmission technology of low resolution develops into and can support the transmission technologys such as high-resolution DP, MIPI and V-BY-ONE from early stage, and the host-host protocol of various transmission technology is also constantly being upgraded, the host-host protocol as DP transmission technology has been upgraded to DP1.2 from original DP1.1.
Liquid crystal module due to legacy interfaces such as LVDS also continues in production; its testing apparatus do not enter the replacement cycle will continue use; although module manufacturer also produces DP1.2 liquid crystal module; but in order to protect investment, reduce production cost, need effectively to utilize existing LVDS signal-testing apparatus to avoid large batch of purchase DP1.2 signal professional test equipment.In order to can within short-term low cost production in enormous quantities DP1.2 liquid crystal module and ensure its yields, need a kind of DP1.2 signal that the LVDS signal that existing LVDS signal-testing apparatus exports can be converted to DP1.2 liquid crystal module and can identify.
Current, the technical scheme that LVDS signal turns DP signal realizes based on DP bridge sheet mostly, and its host-host protocol only supports DP1.1, and its single-channel data transfers speed is maximum can only support 2.7Gbps, can not meet the testing requirement of DP1.2 liquid crystal module.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of chromacoder based on programmable logic device, its object is to solve the technical scheme host-host protocol that current LVDS signal turns DP signal and support too low problem.
For achieving the above object, according to one aspect of the present invention, provide a kind of chromacoder based on programmable logic device, comprise signal processing unit, LVDS signal input interface and DP signal output interface, this signal processing unit is integrated in a programmable logic device; This programmable logic device has the LVDS input terminal coupling LVDS signal input interface and the DP lead-out terminal coupling DP signal output interface; This signal processing unit is used for converting LVDS signal to DP signal.
Preferably, the above-mentioned chromacoder based on programmable logic device, its signal processing unit has LVDS decoder module, this LVDS decoder module couples LVDS signal input interface by LVDS input terminal, and the LVDS signal resolution that LVDS decoder module is used for LVDS signal input interface inputs becomes view data and time sequence information.
Preferably, the above-mentioned chromacoder based on programmable logic device, its signal processing unit has DP coding module, this DP coding module couples DP signal output interface by DP lead-out terminal, and described view data is carried out coding according to described time sequence information according to DP1.2 agreement and generated DP1.1 signal or DP1.2 signal by DP coding module.
Preferably, the above-mentioned chromacoder based on programmable logic device, also comprises the first cache chip, and described programmable logic device has buffer memory terminal, and described signal processing unit has buffer control module; This buffer control module connects above-mentioned first cache chip by above-mentioned buffer memory connecting terminals.
Preferably, the above-mentioned chromacoder based on programmable logic device, described programmable logic device has control terminal, and described signal processing unit has main control module, and control signal inputs above-mentioned main control module by this control terminal; This main control module controls the read-write of above-mentioned buffer control module to above-mentioned first cache chip according to above-mentioned control signal; Above-mentioned main control module can arrange according to external schema setting command direct mode operation or the overtone mode that LVDS signal turns DP signal.
Preferably, the above-mentioned chromacoder based on programmable logic device, also comprises the second cache chip, and above-mentioned DP lead-out terminal couples described DP signal output interface by this second cache chip.
Preferably, above-mentioned signal processing unit has first-in first-out series processing module, and above-mentioned DP coding module comprises multiple DP encoding submodule; The view data read from buffer control module is written to respectively in described multiple DP encoding submodule by this first-in first-out series processing module after caching process.
Preferably, the number of above-mentioned DP signal output interface is all identical with the number of described DP encoding submodule with the number of described DP lead-out terminal, and each DP encoding submodule couples respectively by a DP lead-out terminal and a DP signal output interface.
Preferably, the above-mentioned chromacoder based on programmable logic device, also comprise multiple second cache chip, the number of the second cache chip is identical with the number of DP encoding submodule, and each DP encoding submodule couples respectively by second cache chip and a DP signal output interface.
Preferably, each DP lead-out terminal includes 4 high-speed transceivers, and the message transmission rate of each high-speed transceiver is greater than 3Gbps, and can the message transmission rate of backward compatible 2.7Gbps, 1.62Gbps.
Chromacoder based on programmable logic device provided by the invention, its LVDS signal input interface can support the LVDS access of 1,2,4 and/or 8LINK; Its DP output interface can support that two-way DP signal exports; This chromacoder supports that the straight-through of image and frequency-doubled conversion export.
In general, the above technical scheme conceived by the present invention compared with prior art, can obtain following beneficial effect:
(1) chromacoder provided by the invention, realize the function switching signal of LVDS signal to DP1.2 or DP1.1 host-host protocol, and DP1.2 host-host protocol compatible old edition DP1.1 host-host protocol, forms data passage supports the transmission rate of 5.4Gbps/3.24Gbps/2.7Gbps/1.62Gbps, supports the resolution of 4K*2K@60Hz; Compared with prior art, solve the host-host protocol that current LVDS signal turns DP signal and support too low problem, the large resolution requirements of current video support can be met;
(2) chromacoder provided by the invention, its main control module is arranged according to the pattern of outside, configuration LVDS signal turns the straight-through of DP signal and/or overtone mode, realize the signal input of the low refresh rate of LVDS, the DP signal realizing high refresh rate exports, and breaches LVDS and transmits high-resolution bottleneck.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of a kind of chromacoder based on programmable logic device that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
As shown in Figure 1, a kind of chromacoder based on programmable logic device (exporting for two-way DP signal) that the embodiment of the present invention provides, FPGA is adopted to add the technical scheme of peripheral interface cooperation buffer memory, its FPGA inside embeds LVDS decoder module, main control module, buffer control module and DP coding module, forms signal processing unit; There are 1 road LVDS signal input interface and 2 road DP signal output interfaces; This chromacoder based on programmable logic device that embodiment provides, also embedded in fifo queue processing module (FIFO) in its FPGA; Its DP coding module has two-way encoding submodule, is respectively a DP encoding submodule and the 2nd DP encoding submodule.
In work, LVDS decoder module, to the LVDS signal decoding received, obtains time sequence information and the view data of LVDS signal;
Above-mentioned view data is stored in the first cache chip by buffer control module, and meanwhile main control module arranges acquisition configuration parameter according to external schema; Buffer control module reads corresponding view data according to above-mentioned time sequence information and configuration parameter and sends FIFO from the first cache chip, via FIFO, view data is sent to DP coding module, according to DP1.2 agreement, above-mentioned view data is carried out coding according to above-mentioned time sequence information by DP coding module and generate DP1.1 signal or DP1.2 signal;
Wherein, LVDS decoder module supports the access of 1link, 2link, 4link and 8link signal, output timing information and view data; First cache chip is used for caching image data; Buffer control module is for controlling the read-write operation of the first cache chip; Main control module is used for controlling buffer control module according to external schema configuration information and above-mentioned clock signal; The road view data received is converted to two-way and exports by FIFO; One DP encoding submodule and the 2nd DP encoding submodule are used for the two-way view data exported according to configuration process FIFO, obtain two-way DP signal; Two-way DP1.2 or DP1.1 signal is exported by DP signal output interface; Support the straight-through of image or frequency-doubled conversion;
Wherein, LVDS decoder module, to the LVDS signal receiving and decoding of 1link, 2link, 4link, 8link, decodes time sequence information and the view data of LVDS; Time sequence information is sent to main control module, and view data is sent to buffer control module; This view data is stored in the first buffer memory by buffer control module, and what main control module was synchronous arranges acquisition configuration parameter according to external schema; Buffer control module then reads corresponding view data according to above-mentioned time sequence information and configuration parameter and sends FIFO from the first buffer memory, via FIFO, one tunnel view data is converted to two-way, be sent to a DP encoding submodule and the 2nd DP encoding submodule respectively, convert two-way view data to DP two paths of signals by above-mentioned two DP encoding submodule according to configuration.
Below in conjunction with the chromacoder that embodiment provides, turn DP1.2 signal for the LVDS input signal of 4link, the signal conversion process of LVDS to the DP1.2 signal under concrete elaboration direct mode operation and under overtone mode;
Under direct mode operation, the picture signal of the 4K*2K@60Hz that the LVDS that chromacoder receives 4link sends, is decoded to LVDS picture signal by LVDS decoder module, obtains the view data of RGB and the pixel time series data of RGB; Wherein, the pixel time series data of RGB is sent to main control module, and the view data of RGB is sent to buffer control module;
Buffer control module receives the rgb image data that LVDS decoder module exports, and is saved in the first buffer memory, and records storage information;
After main control module receives the pixel time series data of RGB image, according to the direct mode operation of outer setting, time sequence configuration information is sent to respectively buffer control module and two DP encoding submodule, the speed that buffer control module fetches data from the first cache read is set; The rgb image data read from the first buffer memory is sent to FIFO by buffer control module, and rgb image data is sent to two DP encoding submodule by FIFO automatically;
Each DP encoding submodule carries out functional status configuration according to the sequential configuration parameter order of main control module; The view data exported by FIFO according to this configuration arranges according to the pixel of 4K*2K@60Hz the signal format converting DP1.2 to and is sent to DP signal output interface by a DP lead-out terminal, wherein DP lead-out terminal comprises 4 high-speed transceivers, i.e. 4 data channel, the message transmission rate of each passage is 5.4Gbps; For improving the quality of signal, conversion is generated the signal of DP1.2 through re-sending to DP signal output interface after the second cache chip buffer memory;
For direct mode operation, chromacoder provided by the invention also supports that the LVDS signal of 1link, 2link and 8link turns the application of DP1.2 signal.
Under overtone mode, the picture signal of the 4K*2K@30Hz that the LVDS that chromacoder receives 4link sends, is decoded to LVDS picture signal by LVDS decoder module, obtains the view data of RGB and the pixel time series data of RGB; Wherein, the pixel time series data of RGB is sent to main control module, and the view data of RGB is sent to buffer control module;
Buffer control module receives the rgb image data that LVDS decoder module exports, and is saved in the first buffer memory, and records storage information;
After main control module receives the pixel time series data of RGB image, an overtone mode according to outer setting is arranged, 4K*2K@60Hz time sequence configuration information is sent to buffer control module and two DP encoding submodule respectively, the speed that buffer control module fetches data from the first cache read is set; The rgb image data read from the first buffer memory is sent to FIFO by buffer control module, and rgb image data is sent to two DP encoding submodule by FIFO automatically;
Each DP coding module carries out functional status configuration according to the sequential configuration parameter order of main control module; The view data exported by FIFO arranges according to the pixel of 4K*2K@60Hz the signal format converting DP1.2 to and is sent to DP signal output interface by a DP lead-out terminal, wherein DP lead-out terminal comprises 4 high-speed transceivers, i.e. 4 data channel, the message transmission rate of each passage is 5.4Gbps; For improving the quality of signal, through re-sending to DP signal output interface after the second cache chip buffer memory;
For the conversion to DP1.2 signal of the LVDS signal of 4link, the ultimate resolution of the LVDS signal of 4link supports 4K*2K@60Hz, but when the output image resolution limitations of LVDS signal source, only can export 4K*2K@30Hz, and when exporting DP signal, need the image exporting 4K*2K@60Hz, under this application, adopt the setting of a frequency multiplication;
For overtone mode, chromacoder provided by the invention also supports that the LVDS signal of 1link, 2link and 8link turns the frequency multiplication applied environment of DP1.2 signal, and frequency multiplication multiple can need to arrange according to application.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. based on a chromacoder for programmable logic device, comprise signal processing unit, LVDS signal input interface and DP signal output interface, it is characterized in that, described signal processing unit is integrated in a programmable logic device; Described programmable logic device has the LVDS input terminal coupling described LVDS signal input interface and the DP lead-out terminal coupling described DP signal output interface; Described signal processing unit is used for converting LVDS signal to DP signal.
2. as claimed in claim 1 based on the chromacoder of programmable logic device, it is characterized in that, described signal processing unit has LVDS decoder module, described LVDS decoder module couples described LVDS signal input interface by described LVDS input terminal, and the LVDS signal resolution that LVDS signal input interface inputs is become view data and time sequence information by described LVDS decoder module.
3. as claimed in claim 2 based on the chromacoder of programmable logic device, it is characterized in that, described signal processing unit has DP coding module, described DP coding module couples described DP signal output interface by described DP lead-out terminal, and described view data is carried out coding according to described time sequence information according to DP1.2 agreement and generated DP1.1 signal or DP1.2 signal by described DP coding module.
4., as claimed in claim 3 based on the chromacoder of programmable logic device, it is characterized in that, also comprise the first cache chip, described programmable logic device has buffer memory terminal, and described signal processing unit has buffer control module; Described buffer control module receives described view data and by described buffer memory terminal, described view data is write described first cache chip.
5. as claimed in claim 4 based on the chromacoder of programmable logic device, it is characterized in that, described programmable logic device has control terminal, and described signal processing unit has main control module, and control signal inputs described main control module by described control terminal; Described main control module controls the read-write of described buffer control module to described first cache chip according to described control signal.
6., as claimed in claim 5 based on the chromacoder of programmable logic device, it is characterized in that, also comprise the second cache chip, described DP lead-out terminal couples described DP signal output interface by described second cache chip.
7. as claimed in claim 5 based on the chromacoder of programmable logic device, it is characterized in that, described signal processing unit has first-in first-out series processing module, described DP coding module comprises multiple DP encoding submodule, and the described first-in first-out series processing module view data read in described buffer control module is written to respectively in described multiple DP encoding submodule after caching process.
8. as claimed in claim 7 based on the chromacoder of programmable logic device, it is characterized in that, the number of described DP signal output interface is all identical with the number of described DP encoding submodule with the number of described DP lead-out terminal, and each described DP encoding submodule couples respectively by a described DP lead-out terminal and a DP signal output interface.
9. as claimed in claim 8 based on the chromacoder of programmable logic device, it is characterized in that, also comprise multiple second cache chip, the number of described second cache chip is identical with the number of described DP encoding submodule, and each DP encoding submodule described couples respectively by second cache chip and a DP signal output interface.
10. the chromacoder based on programmable logic device as described in any one of claim 1 to 9, is characterized in that, each described DP lead-out terminal includes 4 high-speed transceivers, and the message transmission rate of described each high-speed transceiver is greater than 3Gbps.
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| CN108319560A (en) * | 2018-03-07 | 2018-07-24 | 中国科学院西安光学精密机械研究所 | A kind of conversion circuit of TLK2711 coffrets and Camera-Link coffrets |
| CN109194889A (en) * | 2018-08-16 | 2019-01-11 | 长芯盛（武汉）科技有限公司 | Low speed signal conversion module for DP interface |
| CN109448614A (en) * | 2018-09-14 | 2019-03-08 | 武汉帆茂电子科技有限公司 | A kind of Displayport signal generation device and method based on FPGA |
| CN109547712A (en) * | 2019-01-18 | 2019-03-29 | 深圳市巨潮科技股份有限公司 | DP signal distribution system based on FPGA |
| CN109753013A (en) * | 2017-11-02 | 2019-05-14 | 上海复旦微电子集团股份有限公司 | Novel programmable chip circuit |
| CN110557581A (en) * | 2019-09-04 | 2019-12-10 | 南京图格医疗科技有限公司 | system for converting multiple interfaces into multiple interfaces under ultrahigh definition resolution and compatible method thereof |
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| CN109547712A (en) * | 2019-01-18 | 2019-03-29 | 深圳市巨潮科技股份有限公司 | DP signal distribution system based on FPGA |
| CN111984577A (en) * | 2019-05-21 | 2020-11-24 | 南宁富桂精密工业有限公司 | Burning control system and burning control method |
| CN110557581A (en) * | 2019-09-04 | 2019-12-10 | 南京图格医疗科技有限公司 | system for converting multiple interfaces into multiple interfaces under ultrahigh definition resolution and compatible method thereof |
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Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the four floor, No. Applicant after: Wuhan fine test electronics group Limited by Share Ltd Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the four floor, No. Applicant before: Wuhan Jingce Electronic Technology Co., Ltd. |
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Application publication date: 20160302 |