CN203574772U - Device for converting single-LINK LVDS video signal into MIPI video signal - Google Patents

Abstract

The utility model discloses a device for converting a single-LINK LVDS video signal into an MIPI video signal. The device comprises a single-LINK LVDS video signal receiving unit, which is used for receiving the single-LINK LVDS video signal and generating LVDS parallel demodulation data and an LVDS pixel clock; a single-LINK LVDS video signal decoding unit, which is used for demodulating data bus video decoding in a parallel manner, generating an LVDS video source signal, which comprises video source data and a video source synchronization signal; an RGB video signal conversion unit, which is used for converting a video source signal into an RGB video signal, which comprises RGB video source data, a synchronization signal, and an RGB video clock; an MIPI video signal conversion unit, which is used for converting the RGB video signal into MIPI video signal to transmit the MIPI video signal to an MIPI display module; and a video conversion and configuration unit, which is used for generating an LVDS video signal decoding signal and an LVDS synchronization mode control signal, and for carrying out configuration operation of the MIPI conversion processing and an initialization operation of the MIPI display module.

Description

The LVDS vision signal of single LINK is converted to MIPI video signal device

Technical field

The utility model relates to demonstration field and the field tests of liquid crystal module, refers to that particularly the LVDS vision signal of a kind of single LINK is converted to MIPI video signal device.

Background technology

Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.

Along with people constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment, therefore common liquid crystals module cannot meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, object is that handle is mobile, inner each assembly of portable equipment is as nuclear interface standardizings such as camera, display screen, processors and opens each other, thereby improved performance, reduced cost and power consumption.MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with MIPI interface has become development trend.

Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although module manufacturer also produces MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.

Therefore, need a kind of conversion equipment the LVDS signal of single LINK can be converted to MIPI signal, common liquid crystals module testing apparatus can be tested MIPI module by this conversion equipment.This conversion equipment is not only wanted dependable performance, integrated efficient but also is wanted low price, easy and simple to handle simultaneously.

Summary of the invention

The purpose of this utility model is to provide the LVDS vision signal of a kind of single LINK to be converted to MIPI video signal device, and it has feature simple to operate, that detection efficiency is high, cost is low.

For achieving the above object, the LVDS vision signal of single LINK that the utility model is designed is converted to MIPI video signal device, and its special character is, comprising:

The LVDS video reception unit of single LINK, for the LVDS vision signal of receiving demodulation list LINK, produces LVDS parallel demodulation data and LVDS pixel clock;

The LVDS video signal decoding unit of single LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to LVDS coding standard control signal, LVDS video color range bit wide control signal, described LVDS parallel demodulation data are carried out to video decode, produce LVDS video source signal, described LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal;

Rgb video signal converting unit, for converting described LVDS video source signal to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit, described rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock;

MIPI vision signal converting unit, for described rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit, send MIPI demonstration module to, described MIPI vision signal shows module for the MIPI of 4LANE type;

Video conversion configurations unit, be used for according to the characteristic of the LVDS vision signal of single LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal send the LVDS video signal decoding unit of described single LINK to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send rgb video signal converting unit to; Receive the MIPI video conversion configurations parameter in the LVDS vision signal of single LINK, carry out the configuration operation of MIPI conversion process, produce the order of MIPI conversion configurations, MIPI shows that module initialization command sends described MIPI vision signal converting unit to; From described rgb video signal converting unit receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described MIPI vision signal converting unit to.

Further, the LVDS video reception unit of described single LINK comprises:

LVDS video signal interface, for receiving the LVDS vision signal of single LINK, the LVDS vision signal of described single LINK comprises LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type;

The LVDS clock signal demodulation module of single LINK is used for: the described LVDS receive clock receiving is carried out to demodulation, produce demodulation clock and demodulation enable signal;

The LVDS demodulated data signal module of single LINK is used for: by described demodulation clock and demodulation enable signal, described LVDS vision signal is demodulated to LVDS parallel demodulation data, described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously.

Further, the LVDS video signal decoding unit of described single LINK comprises:

The LVDS video data decoding module of single LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to the LVDS video decode control signal receiving from described video conversion configurations unit to described LVDS parallel demodulation decoding data, decode LVDS video source data signal.

LVDS video synchronization signal decoder module, the LVDS video decode control signal receiving from described video conversion configurations unit for basis, to described LVDS parallel demodulation decoding data, decodes LVDS video source synchronizing signal.

Further, described rgb video signal converting unit comprises:

Rgb video clock generating module, for generation of rgb video clock;

Rgb video modular converter, for converting described LVDS video source synchronizing signal and LVDS video source data signal to rgb video synchronizing signal and rgb video source data signals with described rgb video clock;

Rgb video clock output adjusting module, for the phase place of described rgb video clock is adjusted, makes its effective edge along center that can be in rgb video source data, then carries out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Rgb video signal output module, be used for receiving described RGB output clock, rgb video source data signals and rgb video synchronizing signal, contrast effective edge of described RGB output clock and the phase place between described rgb video source data center, utilize time delay to do trim process so that effective edge of described RGB output clock and rgb video source data center-aligned, by described rgb video source data signals, rgb video synchronizing signal and the output of described rgb video clock, when having described rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit to.

Further, described MIPI vision signal converting unit comprises:

MIPI register module, for control configuration and the operation that MIPI vision signal modular converter carries out MIPI conversion according to the MIPI register command writing, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter, be used for receiving described rgb video signal, execution is by configuration and the conversion operations of described rgb video signal conversion MIPI vision signal, when receiving the order of MIPI conversion configurations from described MIPI register module, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module, by MIPI liquid crystal display module connector, be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module, start conversion operations;

MIPI liquid crystal display module connector, for receiving described MIPI vision signal, and shows that with MIPI module is connected, and sends described MIPI vision signal to described MIPI and shows module.

Further, described video conversion configurations unit comprises:

Manual toggle switch, for arranging LVDS vision signal decoding parametric;

Jtag interface, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described MIPI vision signal converting unit is sent to MIPI conversion initialization command and MIPI module initialization command, when receiving MIPI video changeover control signal from described rgb video signal converting unit, produce MIPI video conversion starting command and send described MIPI vision signal converting unit to.

Further, the LVDS video reception unit of described single LINK also comprises:

LVDS video reception termination module, be used for the operation that is terminated of received LVDS vision signal, then respectively by described LVDS receive clock with LVDS data send the LVDS clock signal demodulation module of single LINK to and the LVDS of single LINK is subject to signal demodulation module, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, signal buffering with rebuild, compensation is because of long signal distortion that Distance Transmission causes, decay, reduce transmission and disturb, guarantee received LVDS signal quality;

LVDS demodulation dynamic calibration module, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

The beneficial effects of the utility model are:

(1) the utility model can convert the LVDS vision signal of single LINK to MIPI vision signal.By arranging, to different qualities such as the multiple color range of LVDS vision signal, transmission means, coded systems, all can well mate.

(2) the LVDS vision signal of convertible 6,8,10 color ranges of the utility model, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can change the LVDS transmission mode of single LINK, is applicable to the MIPI liquid crystal module of 4LANE type.

(3) the utility model is before use only by manually changing toggle switch state applicable to different LVDS vision signals; Before applying MIP I liquid crystal module, need to receive this module running parameter by jtag interface.

(4) single FPGA(field programmable logic array for the utility model) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.

(5) video resolution that the utility model is supported is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.

Accompanying drawing explanation

Fig. 1 is the utility model block diagram;

Fig. 2 a is the circuit block diagram of LVDS video reception unit and LVDS video signal decoding unit in Fig. 1;

Fig. 2 b is the circuit block diagram of rgb video signal converting unit in Fig. 1, MIPI vision signal converting unit and video conversion configurations unit;

Fig. 3 is the circuit diagram of rgb video modular converter in Fig. 2 b;

Fig. 4 is the signal graph that the LVDS vision signal of single LINK is converted to rgb video signal;

In figure: 1. the LVDS video reception unit of single LINK, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, 1-3.LVDS clock signal demodulation module, 1-4.LVDS demodulated data signal module, 1-5.LVDS demodulation dynamic calibration module;

2. the LVDS video signal decoding unit of single LINK, 2-1.LVDS video data decoding module, 2-2.LVDS video synchronization signal decoder module;

3.RGB vision signal converting unit, 3-1.RGB video clock generation module, 3-2.RGB video conversion module, 3-2-1.LVDS signal sampling, 3-2-2.DC-FIFO buffer memory, 3-2-3.RGB signal sampling, 3-3.RGB video clock output adjusting module, 3-4.RGB vision signal output module;

4.MIPI vision signal converting unit, 4-1.MIPI register module, 4-2.MIPI vision signal modular converter, 4-3.MIPI liquid crystal display module connector;

5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;

6.MIPI shows module.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

As shown in Figures 1 to 4, the LVDS vision signal of a kind of single LINK of the utility model is converted to MIPI video signal device, comprising:

Single LVDS video reception unit 1 of LINK is, the LVDS video signal decoding unit 2 of single LINK, rgb video signal converting unit 3, MIPI vision signal converting unit 4 and video conversion configurations unit 5.

The LVDS video reception unit 1 of single LINK comprises:

The LVDS video reception unit 1 of single LINK, for the LVDS vision signal of receiving demodulation list LINK, produces LVDS parallel demodulation data and LVDS pixel clock; The LVDS vision signal of single LINK comprises LVDS receive clock and LVDS data, and LVDS data are transmitted by LVDS data/address bus, and LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; MIPI vision signal shows module for the MIPI of 4LANE type.LVDS video signal interface 1-1 inputs LVDS vision signal by connecting the LVDS transmission line interface of single LINK, interface comprises two kinds of input pads: industrial standard ox horn seat connector and Miniature high-density business connector, to guarantee that the present invention all can be suitable in industrial environment and business environment, when some connectors have the LVDS signal input of single LINK, interface can be automatically from this connector output, when two connectors have signal input, interface acquiescence is exported from Miniature high-density business connector.

LVDS video reception termination module 1-2, for processing that the LVDS vision signal of the single LINK receiving is terminated, guarantee that LVDS signal quality to be demodulated is high, noiseless, then send LVDS receive clock and LVDS data to the LVDS clock signal demodulation module 1-3 of single LINK and the LVDS signal demodulation module 1-4 of single LINK respectively.The process of termination comprises: before receiving the LVDS signal of single LINK, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs to eliminate the strong discharge impact of moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion causing with erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal, to eliminate the signal attenuation being caused because of loss simultaneously.Afterwards again to signal Hyblid Buffer Amplifier, and through the judgement of reference level, reconstruct the LVDS vision signal of high-quality single LINK.

LVDS clock signal demodulation module 1-3 is used for: the LVDS receive clock after terminated operation is carried out respectively to demodulation, produce LVDS demodulation clock and demodulation enable signal, the LVDS data of this LINK are carried out to demodulation; Demodulating process comprises: LVDS receive clock is input to PLL(Phase Locked Loop phase-locked loop through High Speed I/O buffering) its frequency multiplication is arrived to LVDS frequency data signal, and carry out high-frequency clock conversion process, produce the LVDS demodulation clock with LVDS data same frequency, with LVDS pixel clock and the LVDS demodulation gating signal of LVDS receive clock with frequency, and output in high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable LVDS data to be carried out to demodulation.When LVDS receive clock being carried out to frequency multiplication operation with PLL, from the moving calibrating signal of clock jitter removing of LVDS demodulation dynamic calibration module 1-5, also sending into PLL simultaneously controls this operating process is carried out to anti-shake, it is produced and be not subject to that input jiffer affects, stable frequency-doubled signal, guarantee that demodulation operation can not make mistakes without interruption.

LVDS demodulated data signal module 1-4 is used for: by demodulation clock and demodulation enable signal, LVDS vision signal is demodulated to LVDS parallel demodulation data, LVDS receive clock is demodulated into LVDS pixel clock simultaneously.Its process comprises: to each data demodulation independently respectively in LVDS serial data bus.Each LVDS data-signal is first buffered in the high speed signal network of low delay, low jitter, postponed again data bit bit period half, make this data value that samples that LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to demodulation gating signal, it is periodically blocked to bunchiness data, with LVDS pixel clock, doing string again turns and processes the parallel demodulation data that obtain this LVDS signal, each LVDS demodulating data is merged into LVDS demodulating data bus, by trigger Buffer output to guarantee signal stabilization, reliable.The demodulation that each LVDS holding wire is all run simultaneously, makes each holding wire no matter how data all can phase mutual interference not cause demodulation mistake.

When the bit value by LVDS demodulation clock sampling LVDS data, from the data dithering removal calibrating signal of LVDS demodulation dynamic calibration module 1-5, also this operating process is carried out to anti-shake simultaneously and control, it is produced and be not subject to that input jiffer affects, reliable and stable demodulating data.

In the phase delay process of data input, be subject to all the time the LVDS data flow phase alignment signal controlling of LVDS demodulation dynamic calibration module 1-5, when the phase place between demodulation clock and LVDS data has deviation, phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, data center is alignd along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.

When demodulation gating signal is blocked serial data, also the bit for demodulation byte-aligned that is subject to LVDS demodulation dynamic calibration module 1-5 moves calibrating signal and controls, and makes it the start bit of the parallel data of cutting apart move on next serial data position.

LVDS demodulation dynamic calibration module 1-5, for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

The LVDS video signal decoding unit 2 of single LINK, for LVDS parallel demodulation data being carried out to video decode according to LVDS coding standard control signal, LVDS video color range bit wide control signal, produce LVDS video source signal, LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal.

The LVDS video signal decoding unit 2 of single LINK, comprising:

LVDS video data decoding module 2-1, converts LVDS pixel clock to LVDS video source pixel clock by global clock path.According to the pixel color component level of the VESA the LVDS video decode control signal receiving from video conversion configurations unit 5 and JEIDA transfer encoding standard and LVDS video source is wide, LVDS demodulating data is decoded with sequential logic mode of operation with LVDS video source pixel clock, recover LVDS video source data signal output.

LVDS video synchronization signal decoder module 2-2, for LVDS demodulating data being decoded and recovered LVDS video source synchronizing signal output with sequential logic mode of operation with LVDS video source pixel clock according to the VESA of the 5 LVDS video decode control signals that receive from video conversion configurations unit and JEIDA transfer encoding standard, synchronizing signal comprises: video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).

Rgb video signal converting unit 3 is for converting LVDS video source signal to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit 5, rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock.

Rgb video signal converting unit 3 comprises:

Rgb video clock generating module 3-1, for generation of rgb video clock; By PLL configuration parameter, ordered pair PLL carries out reconfiguration operation during according to its dynamic recognition, the frequency of LVDS video source pixel clock is become to twice, the frequency-doubled signal producing is adjusted its phase place again and is made it to keep phase place strictly identical with LVDS pixel clock, (to guarantee to sample correctly, reliably LVDS data in the follow-up operation of the sequential logic in conversion process), after de-jitter, enter again global clock path stable, that nothing swings, thereby produce the frequency rgb video clock identical with LVDS video source pixel clock.

Rgb video modular converter 3-2, for converting LVDS video source synchronizing signal and LVDS video source data signal to rgb video synchronizing signal and rgb video source data signals with rgb video clock.Rgb video modular converter 3-2 is combined into the parallel data of a link by the LVDS video source synchronizing signal of single LINK and LVDS data according to the form of " data, synchronizing signal ", with LVDS video source pixel clock, in LVDS signal sampling 3-2-1, sample, and write buffer memory in DC-FIFO buffer memory 3-2-2; Rgb signal sampling 3-2-3 reads parallel data with rgb video clock, and isolates rgb video source data and rgb video synchronizing signal, thereby completes conversion process.

Rgb video clock output adjusting module 3-3, due to rgb video source data signals and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as RGB clock signal, make it effectively along center that can be in rgb video source data, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and by high speed signal Buffer Unit, RGB output clock is exported, to guarantee that this output clock has higher stability and good signal quality.

Rgb video signal output module 3-4, be used for receiving RGB output clock, rgb video source data signals and rgb video synchronizing signal, effective edge of contrast RGB output clock and the phase place between rgb video source data center, utilize time delay to do trim process so that effective edge of RGB output clock and rgb video source data center-aligned, by rgb video source data signals and the output of rgb video synchronizing signal, when having rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send video conversion configurations unit 5 to.

MIPI vision signal converting unit 4, for rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit 5, send MIPI demonstration module 6 to, MIPI vision signal shows module 6 for the MIPI of 4LANE type;

MIPI vision signal converting unit 4, comprise: MIPI register module 4-1, for control MIPI vision signal modular converter 4-2 according to the MIPI register command writing, carry out configuration and the operation of MIPI conversion, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter 4-2, be used for receiving rgb video signal, configuration and the conversion operations of MIPI vision signal are changed rgb video signal in execution, when receiving the order of MIPI conversion configurations from MIPI register module 4-1, complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from MIPI register module 4-1, by MIPI liquid crystal display module connector 4-3, be transferred to MIPI and show module, when receiving MIPI conversion starting command from MIPI register module 4-1, start conversion operations.

MIPI liquid crystal display module connector 4-3, for receiving MIPI vision signal, and shows that with MIPI module 6 is connected, and sends MIPI vision signal to MIPI and shows module 6.

Video conversion configurations unit 5, be used for according to the characteristic of the LVDS vision signal of single LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal send the LVDS video signal decoding unit 2 of single LINK to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send rgb video signal converting unit 3 to; Receive the MIPI video conversion configurations parameter in the LVDS vision signal of single LINK, produce the order of MIPI conversion configurations, MIPI shows that module initialization command sends MIPI vision signal converting unit 4 to; From rgb video signal converting unit 3 receives MIPI video conversion starting signal, send MIPI video conversion starting command and send MIPI vision signal converting unit 4 to.

Video conversion configurations unit 5 comprises:

Manual toggle switch 5-1, for arranging LVDS vision signal decoding parametric;

Jtag interface 5-2, for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module 5-3, for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter MIPI vision signal converting unit 4 is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when produce MIPI video conversion starting command from rgb video signal converting unit 3 receives MIPI video changeover control signals, send MIPI vision signal converting unit 4 to.

Before powering on, the configuration of LVDS video decode and conversion is first manually set to toggle switch 5-1, after powering on, by MIPI video conversion configurations module 5-3, according to its dial-up state, produce LVDS video decode control signal and LVDS video changeover control signal, from jtag interface 5-2, read MIPI video conversion configurations parameter afterwards, and its mode with register command is written in MIPI vision signal converting unit 4 one by one, first write the order of MIPI conversion configurations, when confirming that writing MIPI after MIPI vision signal converting unit 4 completes configuration beginning normal work shows module initialization command again, after often writing an order, read the state value of its register, to guarantee that command execution completes, ought receive that afterwards MIPI video changeover control signal changes starting command by MIPI and write register, make MIPI video conversion operations start to carry out.

Each functional module of the present utility model all can realize by FPGA, for MIPI video conversion configurations module, 5-3 also can realize its function with common MCU, also can be by realize respectively the conversion of single MIPI signal with two special-purpose MIPI bridging chips for MIPI vision signal converting unit 4.

The utility model is not limited to above-mentioned execution mode; for those skilled in the art, be also considered as the protection range of the utility model patent according to know-why of the present utility model and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present utility model within.

The content not being described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.

Claims (7)

1. the LVDS vision signal of single LINK is converted to a MIPI video signal device, it is characterized in that: comprising:

The LVDS video reception unit (1) of single LINK, for the LVDS vision signal of receiving demodulation list LINK, produces LVDS parallel demodulation data and LVDS pixel clock;

The LVDS video signal decoding unit (2) of single LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to LVDS coding standard control signal, LVDS video color range bit wide control signal, described LVDS parallel demodulation data are carried out to video decode, produce LVDS video source signal, described LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal;

Rgb video signal converting unit (3), for converting described LVDS video source signal to rgb video signal according to LVDS synchronous mode control signal, after converting, send MIPI video conversion starting signal to video conversion configurations unit (5), described rgb video signal comprises rgb video source data, rgb video synchronizing signal and rgb video clock;

MIPI vision signal converting unit (4), for described rgb video signal being converted to MIPI vision signal when receive MIPI video conversion starting command from video conversion configurations unit (5), send MIPI demonstration module (6) to, described MIPI vision signal shows module (6) for the MIPI of 4LANE type;

Video conversion configurations unit (5), be used for according to the characteristic of the LVDS vision signal of single LINK that will receive, LVDS vision signal decoding parametric is set, and generation LVDS coding standard control signal, LVDS video color range bit wide control signal send the LVDS video signal decoding unit (2) of described single LINK to; LVDS audio video synchronization pattern is set and controls parameter, produce LVDS synchronous mode control signal and send rgb video signal converting unit (3) to; Receive the MIPI video conversion configurations parameter in the LVDS vision signal of single LINK, produce the order of MIPI conversion configurations, MIPI shows that module initialization command sends described MIPI vision signal converting unit (4) to; From described rgb video signal converting unit (3) receives MIPI video conversion starting signal, send MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.

2. the LVDS vision signal of single LINK according to claim 1 is converted to MIPI video signal device, it is characterized in that: the LVDS video reception unit (1) of described single LINK comprising:

LVDS video signal interface (1-1), for receiving the LVDS vision signal of single LINK, the LVDS vision signal of described single LINK comprises LVDS receive clock and LVDS data, described LVDS data are transmitted by LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type;

The LVDS clock signal demodulation module (1-3) of single LINK for: the described LVDS receive clock receiving is carried out to demodulation, produces demodulation clock and demodulation enable signal;

The LVDS demodulated data signal module (1-4) of single LINK for: by described demodulation clock and demodulation enable signal, described LVDS vision signal is demodulated to LVDS parallel demodulation data, described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously.

3. the LVDS vision signal of single LINK according to claim 1 is converted to MIPI video signal device, it is characterized in that: the LVDS video signal decoding unit (2) of described single LINK comprising:

The LVDS video data decoding module (2-1) of single LINK, for described LVDS pixel clock is converted to LVDS video source pixel clock, and according to the LVDS video decode control signal receiving from described video conversion configurations unit (5) to described LVDS parallel demodulation decoding data, decode LVDS video source data signal;

LVDS video synchronization signal decoder module (2-2), the LVDS video decode control signal receiving from described video conversion configurations unit (5) for basis, to described LVDS parallel demodulation decoding data, decodes LVDS video source synchronizing signal.

4. the LVDS vision signal of single LINK according to claim 1 is converted to MIPI video signal device, it is characterized in that: described rgb video signal converting unit (3) comprising:

Rgb video clock generating module (3-1), for generation of rgb video clock;

Rgb video modular converter (3-2), for converting described LVDS video source synchronizing signal and LVDS video source data signal to rgb video synchronizing signal and rgb video source data signals with described rgb video clock;

Rgb video clock output adjusting module (3-3), for the phase place of described rgb video clock is adjusted, make its effective edge along center that can be in rgb video source data, then carry out de-jitter, and described rgb video clock is adjusted into RGB output clock;

Rgb video signal output module (3-4), be used for receiving described RGB output clock, rgb video source data signals and rgb video synchronizing signal, contrast effective edge of described RGB output clock and the phase place between described rgb video source data center, utilize time delay to do trim process so that effective edge of described RGB output clock and rgb video source data center-aligned, by described rgb video source data signals, rgb video synchronizing signal and the output of described rgb video clock, when having described rgb video source data signals and the output of rgb video synchronizing signal, postpone to produce MIPI video conversion starting signal and send described video conversion configurations unit (5) to.

5. the LVDS vision signal of single LINK according to claim 1 is converted to MIPI video signal device, it is characterized in that: described MIPI vision signal converting unit (4) comprising:

MIPI register module (4-1), for controlling according to the MIPI register command writing configuration and the operation that MIPI vision signal modular converter (4-2) carries out MIPI conversion, these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show that module initialization command, MIPI change starting command;

MIPI vision signal modular converter (4-2), be used for receiving described rgb video signal, execution is by configuration and the conversion operations of described rgb video signal conversion MIPI vision signal, when receiving the order of MIPI conversion configurations from described MIPI register module (4-1), complete corresponding configuration, conversion operations, when receiving MIPI demonstration module initialization command from described MIPI register module (4-1), by MIPI liquid crystal display module connector (4-3), be transferred to MIPI and show module, when receiving MIPI conversion starting command from described MIPI register module (4-1), start conversion operations,

MIPI liquid crystal display module connector (4-3), for receiving described MIPI vision signal, and shows that with MIPI module (6) is connected, and sends described MIPI vision signal to described MIPI and shows module (6).

6. the LVDS vision signal of single LINK according to claim 1 is converted to MIPI video signal device, it is characterized in that: described video conversion configurations unit (5) comprising:

Manual toggle switch (5-1), for arranging LVDS vision signal decoding parametric;

Jtag interface (5-2), for receiving MIPI video conversion configurations parameter;

MIPI video conversion configurations module (5-3), for LVDS vision signal decoding parametric is converted to LVDS video decode control signal, read MIPI video conversion configurations parameter described MIPI vision signal converting unit (4) is sent to the order of MIPI conversion configurations, MIPI demonstration module initialization command, when receiving MIPI video changeover control signal from described rgb video signal converting unit (3), produce MIPI video conversion starting command and send described MIPI vision signal converting unit (4) to.

7. the LVDS vision signal of single LINK according to claim 2 is converted to MIPI video signal device, it is characterized in that: the LVDS video reception unit (1) of described single LINK also comprises:

LVDS video reception termination module (1-2), be used for the operation that is terminated of received LVDS vision signal, then send described LVDS receive clock and LVDS data to the LVDS clock signal demodulation module (1-3) of single LINK and the LVDS signal demodulation module (1-4) of single LINK respectively, described terminated operation comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization with postemphasis, signal buffering and reconstruction, compensation is because of long signal distortion that Distance Transmission causes, decay, reducing transmission disturbs, guarantee received LVDS signal quality,

LVDS demodulation dynamic calibration module (1-5), for carrying out in real time respectively dynamic calibration to the string signal of LVDS receive clock and LVDS data at demodulating process respectively.

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