CN209928941U - 8K4K video/image signal machine - Google Patents
8K4K video/image signal machine Download PDFInfo
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- CN209928941U CN209928941U CN201920003612.4U CN201920003612U CN209928941U CN 209928941 U CN209928941 U CN 209928941U CN 201920003612 U CN201920003612 U CN 201920003612U CN 209928941 U CN209928941 U CN 209928941U
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Abstract
The utility model relates to an 8K4K video/image signal machine, including sg607 signal mainboard, 4 pieces of sg245 signal boards, sg607 signal mainboard passes through the HDMI cable with 4 pieces of sg245 signal boards and is connected, sg607 signal mainboard still passes through rs485 interface connection with 1 piece of sg245 signal board wherein, connect through four electronic lines with cascaded mode between 4 pieces of sg245 signal boards, sg607 signal mainboard passes through UDP protocol and PC communication, downloads picture information, parameter and control command to sg607 signal mainboard. The utility model discloses 8K4K video image signal machine can light the 8K LCD screen of multiple specification vbyone interface, can be used to liquid crystal manufacturing enterprise detects the liquid crystal defect.
Description
Technical Field
The utility model relates to an annunciator field, concretely relates to 8K4K video/image annunciator.
Background
The signal in the prior art is almost designed for a liquid crystal screen with a specific design, for example, a field division screen (a screen is divided into four parts, namely, an upper left part, an upper right part, a lower left part and a lower right part), the signal lacks compatibility, can only be used for the specific liquid crystal screen, and the application range is very narrow.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an 8K4K video/image semaphore for solve the narrow problem of semaphore application scope among the prior art.
The utility model provides an 8K4K video/image signal machine, including sg607 signal mainboard, 4 pieces of sg245 signal boards, sg607 signal mainboard passes through the HDMI cable with 4 pieces of sg245 signal boards and is connected, sg607 signal mainboard still passes through rs485 interface connection with 1 piece of sg245 signal board wherein, connect through four electronic lines with cascaded mode between 4 pieces of sg245 signal boards, sg607 signal mainboard passes through UDP protocol and PC communication, downloads picture information, parameter and control command to sg607 signal mainboard.
Furthermore, a main control chip of the sg607 signal main board is an FPGA, and the FPGA mounts 4 DDR chips, a DP analysis module and a gigabit ethernet.
Furthermore, a main control chip of the sg245 signal board is an FPGA, and the FPGA mounts 4 DDR chips, a DP analysis module, and a gigabit ethernet.
Furthermore, the sg607 signal main board is connected with a PC through a DP interface to play video in a screen projection manner.
Adopt above-mentioned the utility model discloses technical scheme's beneficial effect is:
the utility model discloses 8K4K video/image semaphore can light the 8K LCD screen of multiple specification vbyone interface, can be used to liquid crystal manufacturing enterprise and detect the liquid crystal defect;
the liquid crystal display supports 32lane output (8K @60HZ) and 64lane output (8K @120HZ), and is compatible with a liquid crystal screen with lower resolution downwards;
the sg607 signal main board and the sg245 signal board are connected through an HDMI cable to transmit high-resolution and low-frame-rate vbyone video streams, and the low-frame-rate video is subjected to frequency doubling through DDR chip buffering of the sg245 signal board.
Drawings
Fig. 1 is a schematic structural diagram of the 8K4K video/image signal apparatus of the present invention;
fig. 2 is a flow chart of the operation of the 8K4K video/image signal device of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
As shown in fig. 1, the 8K4K video/image signal apparatus of this embodiment includes an sg607 signal main board and 4 sg245 signal boards, the sg607 signal main board is connected to the 4 sg245 signal boards through an HDMI cable, the sg607 signal main board is further connected to 1 sg245 signal board through an rs485 interface, the 4 sg245 signal boards are connected through four electronic lines in a cascade connection manner, the sg607 signal main board communicates with a PC through a UDP protocol, and downloads picture information, parameters and control instructions to the sg607 signal main board.
Specifically, a main control chip of the sg607 signal main board is an FPGA, and the FPGA mounts 4 DDR chips, a DP analysis module, and a gigabit ethernet.
Specifically, the main control chip of the sg245 signal board is an FPGA, and the FPGA mounts 4 DDR chips, a DP analysis module, and a gigabit ethernet.
Specifically, the sg607 signal main board is further connected with a PC through a DP interface to play a video in a screen projection manner.
As shown in fig. 2, the method for operating an 8K4K video/image signal in this embodiment specifically includes:
s1: the PC transmits the picture information and the parameters to the sg607 signal mainboard;
s2: the sg607 signal main board analyzes the parameters, configures an internal time sequence and sends the internal time sequence to the sg245 signal board, and the sg245 signal board receives picture information and parameters;
s3: the sg245 signal board connected with the sg607 signal main board through the rs485 interface sends a synchronization signal at the beginning of each frame of picture, the sg245 signal board automatically transmits the next frame at the end of the frame, the other sg245 signal boards start to transmit one frame of picture after receiving the frame synchronization signal, and the frame end waits for the next synchronization signal to start a new transmission.
The PC transmits the picture information and the parameters to the sg607 signal mainboard, which specifically comprises the following steps: the PC transmits the picture information and the parameters to a DP analysis module in the sg607 signal mainboard, the DP analysis module analyzes the picture information and the parameters into original RGB data, 4-frame space is opened up in a DDR chip in the sg607 signal mainboard, and the pictures transmitted by the DP analysis module are written into the DDR chip in a frame unit in a rotating mode.
The sg607 signal main board analyzes the parameters, configures an internal time sequence, and issues the internal time sequence to the sg245 signal board, specifically: the sg607 signal mainboard configures an FPGA internal line and field time sequence generation module according to parameters issued by a PC, the FPGA reads image data in a DDR chip in line units according to the time sequence generated by the module, caches the image data to internal 16 high-speed dual-port rams according to a screen splitting mode in the parameters, reads ram data according to the time sequence of the line and field generation module, packs the data into a format specified by a vbyone protocol through a vbyone ip, and sends the packed data to the sg245 signal board.
The sg245 signal board receives picture information and parameters, specifically: a DP analysis module in the sg245 signal board receives a vbyone signal transmitted by the sg607 signal main board, the vbyone signal is analyzed into original RGB data, 4-frame space is opened up in a DDR chip in the sg245 signal main board, and a picture transmitted by the DP analysis module is written into the DDR chip in a frame unit in a rotating mode.
The sg245 signal board transmission picture specifically includes: the sg245 signal board configures an FPGA (field programmable gate array) internal line field time sequence generation module in the sg245 signal board according to parameters issued by an sg607 signal main board or a superior sg245 signal board, the FPGA reads image data in DDR (double data rate) chips in line units according to the time sequence generated by the module, caches the image data to 16 internal high-speed double-port rams according to a screen splitting mode in the parameters, reads ram data according to the time sequence of the line field generation module, and packs the data into a format specified by a vbyone protocol through a vbyone ip for transmission and output.
The sg607 signal main board and the sg245 signal board adopt a ping-pong-like mode in reading and writing frame addresses of DP pictures, and when a picture is written into a first frame, a picture of a third frame is read; reading a fourth frame when a picture is written to the second frame; when writing a picture to the third frame, the first frame is read, thus ensuring uninterrupted data flow.
Only 2 sg245 signal plates are needed for the 32lane liquid crystal screen, and the sg607 can be directly used for lighting the lower-resolution liquid crystal screen. Meanwhile, different screen splitting modes can be set according to parameters set by the PC, including field division screen, 2 screen splitting, 4 screen splitting and the like. Each sg245 signal plate has 16lane vbyone output signals, is connected with a screen end by using 2 jae terminals, and each terminal contains 8lane vbyone signals and a pair of htpdn and lockn signals.
To sum up, the utility model discloses 8K4K video/image semaphore can light the 8K LCD screen of multiple specification vbyone interface, can be used to the liquid crystal manufacturing enterprise and detect the liquid crystal defect; the liquid crystal display supports 32lane output (8K @60HZ) and 64lane output (8K @120HZ), and is compatible with a liquid crystal screen with lower resolution downwards; the sg607 signal board and the sg245 signal board are connected by using an HDMI cable to transmit high-resolution and low-frame-rate vbyone video streams, and the low-frame-rate video is frequency-doubled by using DDR chip buffering of the sg 245.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (4)
1. The utility model provides an 8K4K video/image semaphore which characterized in that, includes sg607 signal mainboard, 4 blocks of sg245 signal boards, sg607 signal mainboard passes through the HDMI cable with 4 blocks of sg245 signal boards and is connected, sg607 signal mainboard still passes through rs485 interface connection with 1 block of sg245 signal board wherein, connect through four electronic lines with cascaded mode between the 4 blocks of sg245 signal boards, sg607 signal mainboard passes through UDP protocol and PC communication, downloads picture information, parameter and control command to sg607 signal mainboard.
2. The 8K4K video/image signal machine according to claim 1, wherein the main control chip of the sg607 signal main board is an FPGA, and the FPGA mounts 4 DDR chips, a DP resolution module and a gigabit ethernet.
3. The 8K4K video/image signal machine according to claim 1, wherein the main control chip of the sg245 signal board is an FPGA, and the FPGA mounts 4 DDR chips, a DP resolution module and a gigabit ethernet.
4. The 8K4K video/image signal according to claim 1, wherein the sg607 signal motherboard is further connected to a PC through a DP interface for playing video in a screen projection manner.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920003612.4U CN209928941U (en) | 2019-01-02 | 2019-01-02 | 8K4K video/image signal machine |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920003612.4U CN209928941U (en) | 2019-01-02 | 2019-01-02 | 8K4K video/image signal machine |
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| CN209928941U true CN209928941U (en) | 2020-01-10 |
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| CN201920003612.4U Active CN209928941U (en) | 2019-01-02 | 2019-01-02 | 8K4K video/image signal machine |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113573111A (en) * | 2021-07-15 | 2021-10-29 | 康佳集团股份有限公司 | 8K ultra-high-definition video conversion point screen system and method |
| CN115190330A (en) * | 2022-07-02 | 2022-10-14 | 海的电子科技(苏州)有限公司 | Image signal processing method and device |
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2019
- 2019-01-02 CN CN201920003612.4U patent/CN209928941U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113573111A (en) * | 2021-07-15 | 2021-10-29 | 康佳集团股份有限公司 | 8K ultra-high-definition video conversion point screen system and method |
| CN113573111B (en) * | 2021-07-15 | 2024-05-17 | 康佳集团股份有限公司 | 8K ultra-high definition video conversion screen pointing system and screen pointing method |
| CN115190330A (en) * | 2022-07-02 | 2022-10-14 | 海的电子科技(苏州)有限公司 | Image signal processing method and device |
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