CN113573111B - 8K ultra-high definition video conversion screen pointing system and screen pointing method - Google Patents
8K ultra-high definition video conversion screen pointing system and screen pointing method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4122—Peripherals receiving signals from specially adapted client devices additional display device, e.g. video projector
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/4104—Peripherals receiving signals from specially adapted client devices
- H04N21/4112—Peripherals receiving signals from specially adapted client devices having fewer capabilities than the client, e.g. thin client having less processing power or no tuning capabilities
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/43615—Interfacing a Home Network, e.g. for connecting the client to a plurality of peripherals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
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Abstract
The invention discloses an 8K ultra-high definition video conversion point screen system and a point screen method, wherein the system comprises the following steps: the device comprises a video control module, a storage module in communication connection with the video control module and external terminal equipment in communication connection with the video control module; wherein, the video control module includes: the video processing system comprises two paths of video input interfaces, a video processing module which is in communication connection with the two paths of video input interfaces, and a video output interface which is in communication connection with the video processing module, wherein the video output interface is in communication connection with the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to an 8K ultra-high definition video conversion point screen system and a point screen method.
Background
With the development of 5G communication technology and the commercial use of 8K display products, the country is actively pushing a '5G+8K' video live program, thereby promoting the high-speed development of an ultra-high definition industry chain and enabling a plurality of audience friends who cannot be in close contact to actually feel the hot atmosphere on site.
However, when the existing video terminal plays 8K video resources, the 8K video resources need to be converted, and although the existing video conversion software in the market can also support arbitrary video segmentation/merging and other processes, the existing video terminal cannot light 8K60Hz or 8K120Hz display equipment, so that the existing video terminal cannot adapt to more application scenes.
Accordingly, there is a need for improvement and advancement in the art.
Disclosure of Invention
The invention aims to solve the technical problems that aiming at the defects in the prior art, an 8K ultra-high definition video conversion point screen system and a point screen method are provided, and the problem that the prior art cannot light 8K60Hz or 8K120Hz display equipment, so that the system cannot adapt to more application scenes is solved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
In a first aspect, the present invention provides an 8K ultra-high definition video conversion point screen system, the system comprising: the device comprises a video control module, a storage module in communication connection with the video control module and external terminal equipment in communication connection with the video control module;
Wherein, the video control module includes: the video processing system comprises two paths of video input interfaces, video processing modules which are respectively in communication connection with the two paths of video input interfaces, and video output interfaces which are in communication connection with the video processing modules, wherein the video output interfaces are in communication connection with the external terminal equipment.
In one implementation, the two paths of video input interfaces are respectively in communication connection with a preset 8K set top box.
In one implementation, the two paths of video input interfaces are all HDMI2.1 input interfaces, and each path of HDMI2.1 input interface is communicatively connected to the 8K set-top box through a high-speed transceiver.
In one implementation manner, the video output interfaces are provided with multiple paths, and each path of video output interface is respectively in communication connection with one external terminal device.
In one implementation manner, the video output interface is an HDMI2.0 output interface, and each path of HDMI2.0 output interface is connected to the external terminal device through a high-speed transceiver.
In one implementation, the memory module is a high bandwidth DDR4 memory.
In one implementation, the video processing module includes: the dual-port RAM comprises a dual-port RAM, a video data channel selection unit connected with the dual-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit and a plurality of sub dual-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; each sub dual-port RAM is respectively connected with one external terminal device.
In one implementation, two dual-port RAMs are provided, and the two dual-port RAMs are respectively connected with the two paths of video input interfaces.
In one implementation, the number of sub dual port RAMs is the same as the number of video output interfaces.
In a second aspect, an embodiment of the present invention further provides an 8K ultra-high definition video conversion point screen method, where the method includes:
Acquiring a video signal source through a high-speed video interface, and performing protocol decoding on the video signal source to obtain an 8K video signal;
caching the image corresponding to the 8K video signal through a memory, and segmenting the cached image frame according to a preset segmentation mode to obtain a segmented image;
And carrying out protocol coding on the segmented image through a video output interface to obtain coded image data, and converting the coded image data into a high-speed serial video signal and transmitting the high-speed serial video signal to external terminal equipment.
The beneficial effects are that: compared with the prior art, the invention provides an 8K ultra-high definition video conversion point screen system, which comprises: the device comprises a video control module, a storage module in communication connection with the video control module and external terminal equipment in communication connection with the video control module; wherein, the video control module includes: the video processing system comprises two paths of video input interfaces, a video processing module which is in communication connection with the two paths of video input interfaces, and a video output interface which is in communication connection with the video processing module, wherein the video output interface is in communication connection with the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Drawings
Fig. 1 is a schematic diagram of an 8K ultra-high definition video conversion point screen system according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a video processing module in an 8K ultra-high definition video conversion point screen system according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a video segmentation mode in an 8K ultra-high definition video conversion point screen system according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of video conversion under different modes in an 8K ultra-high definition video conversion point screen system according to an embodiment of the present invention.
Fig. 5 is a flowchart of a specific implementation of an 8K ultra-high definition video conversion point screen according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and more specific, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The embodiment of the invention provides an 8K ultra-high definition video conversion point screen system, which is specifically shown in fig. 1, and specifically comprises: the system comprises a video control module, a storage module in communication connection with the video control module and an external terminal device in communication connection with the video control module. In particular, the video control module in this embodiment is an FPGA (Field-Programmable GATE ARRAY, i.e., field-Programmable gate array) or an ASIC chip (an integrated circuit chip). The video control module in this embodiment includes: the video processing system comprises two paths of video input interfaces, a video processing module which is in communication connection with the two paths of video input interfaces, and a video output interface which is in communication connection with the video processing module, wherein the video output interface is in communication connection with the external terminal equipment. In this embodiment, by using two paths of video input interfaces, an 8K120Hz video signal can be transmitted, so as to be suitable for more usage scenarios. In a specific application, the two paths of video input interfaces in the embodiment are respectively in communication connection with a preset 8K set top box so as to receive 8K video data of the 8K set top box. In this embodiment, the device connected to the two paths of video input interfaces is not limited to an 8K set top box, but may be other ultra-high definition devices.
Specifically, in this embodiment, as shown in fig. 1, the two paths of video input interfaces in this embodiment are HDMI2.1 input interfaces (i.e., HDMI2.1 input IP), and each path of HDMI2.1 input interface is communicatively connected to the 8K set-top box through a high-speed transceiver. Correspondingly, the video output interfaces are provided with multiple paths, and each path of video output interface is respectively in communication connection with one external terminal device. In this embodiment, the video output interface is an HDMI2.0 output interface (i.e., HDMI2.0 output IP), and each path of HDMI2.0 output interface is connected to the external terminal device through a high-speed transceiver. In this embodiment, the external device includes an external screen system and a sound box system, each screen system corresponds to an HDMI2.0 output interface, so that the HDMI2.0 output interface can package HDMI2.0 (and the following versions) protocols and then transmit data to the high-speed transceiver, and the high-speed transceiver converts the low-speed parallel signal into a high-speed serial signal and transmits the high-speed serial signal to the corresponding external terminal device (e.g., a 1/n screen system).
In one implementation, the memory module in this embodiment is a high bandwidth DDR4 memory. As shown in fig. 2, the video processing module includes: the dual-port RAM comprises a dual-port RAM, a video data channel selection unit connected with the dual-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit and a plurality of sub dual-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; each sub dual-port RAM is respectively connected with one external terminal device. In this embodiment, the high-bandwidth DDR4 memory may be replaced with any one of a DDR3 memory, a DDR4 memory, and a DDR5 memory.
Specifically, two dual-port RAMs in this embodiment are provided, corresponding to dual-port RAM-1 and dual-port RAM-2 in fig. 2, respectively, and the two dual-port RAMs are connected to two paths of the video input interfaces, respectively. In this embodiment, the number of the sub dual-port RAMs is the same as the number of the video output interfaces, that is, the number of the dual-port RAMs is the same as the number of the HDMI2.0 output interfaces, so that the video signals output from any one of the sub dual-port RAMs (e.g., 1/n dual-port RAM) are transmitted to the corresponding external terminal device (e.g., 1/n screen system) through the corresponding HDMI2.0 output interface and the high-speed transceiver.
In a specific application, when one path of video image data from the HDMI2.1 input IP is "written" into a dual-port RAM, the dual-port RAM is used as a first-level input buffer (with smaller capacity, for example, 1 line 7680 pixel points of the input image), and the purpose of the dual-port RAM is to switch the pixel clock domain, from a slow clock (for example, 148.5 MHz) for video image input to a fast clock (for example, 300 MHz) for DDR4 processing. The video data channel selection module triggers a read operation after the buffer memory of the dual-port RAM is full of one line, continuously reads one line of pixel points from the specific dual-port RAM (namely, the current mode 1/2 is used by using the dual-port RAM-1 or the dual-port RAM-2 according to the setting, the current mode 3 is used by both the dual-port RAM-1 and the RAM-2), and sends the pixel points to the DDR4 read-write control module at the rear end. And then waiting for the next line to buffer the full mark and then reading again, so as to repeat. The DDR4 read-write control module adopts a time-sharing multiplexing control read-write mode (DDR 4 can only operate read or operate write at the same time). Therefore, the control logic of DDR4 performs a write operation first, and "writes" a row of pixels (e.g., 7680 pixels) of the current frame, and then "reads" a row of pixels (e.g., 7680 pixels) of the previous frame. Then, the control logic will write the pixel point read from DDR4 into the next 1/n dual port RAM (i.e., sub dual port RAM) according to a specific division manner (such as SQD division manner or horizontal quarter division manner in fig. 3), which matches the number of sub dual port RAMs. The purpose of the 1/n dual port RAM is to switch the pixel clock domain from the DDR4 processing fast clock (e.g., 300 MHz) to the video image output slow clock (e.g., 74.25 MHz), which automatically triggers pushing of data to the back end (HDMI 2.0 (and versions below) output IP) after the 1/n dual port RAM is cached full of one line (e.g., 3840 pixels).
In this embodiment, the number of sub dual port RAMs, the number of HDMI2.0 output interfaces, and the number of external terminal devices may be set as needed. An 8K ultra high definition television, i.e., a television having a pixel number up to 7680x4320 (hereinafter referred to as 8K), has a 16-fold increase in pixel number over the pixel number of 1920x1080 (hereinafter referred to as 2K) of a full high definition television, and a 4-fold increase in pixel number over the 4-fold full high definition television 4320x2160 (hereinafter referred to as 4K). So that the image is very clear and fine. Therefore, in a specific application, the embodiment can also select whether to use one path of video input interface or two paths of video input interfaces according to the number of the external terminal devices. For example, mode 1 when n in fig. 1 and 2 is 4, when the FPGA receives one path of HDMI2.1 signal source (8K 60 Hz) from the front end (including but not limited to 8K set top box, PC graphic card), the high speed transceiver of the FPGA converts the high speed serial signal into a low speed parallel signal, and then the signal is subjected to protocol decoding via HDMI2.1 input IP, and the decoded 8K video signal is provided to the video processing module. The processing module caches 1 whole frame of the input image by means of an external high-bandwidth DDR4 cache function, and reads the image of the previous frame from DDR4 according to a specific segmentation mode (including but not limited to SQD segmentation and horizontal 4 equal segmentation (shown in the third drawing)) in the time of the second frame. Finally, the module directly outputs the image to the back-end HDMI2.0 (and the following versions) output IP for protocol coding. The output IP packages the image data (4K 60 Hz) according to the HDMI2.0 (and versions below) protocol and transmits the data to the high-speed transceiver, which converts the low-speed parallel signal into a high-speed serial signal and transmits the high-speed serial signal to the external terminal device (1/4 sub-screen system), as shown in mode one of fig. 4. In this mode, only one HDMI2.1 input needs to be responded to, supporting flexible switching from two HDMI2.1 sources. Although there is a delay of 1 frame (16.6 ms) from the input to the output image, which is affected by the DDR4 buffer of 1 frame, this mode can support any split-splice approach.
Mode 2: n in fig. 1 and 2 is equal to 16, and the data processing flow is basically the same as the mode one, except that the HDMI2.0 (and the following versions) output IP packages the image data (2K 60 Hz) according to the protocol, and transmits the packaged image data to the high-speed transceiver, and transmits the packaged image data to the external terminal device (1/16 sub-screen system), and the effect is shown as the mode two in fig. 4.
Mode 3: n in fig. 1 and 2 is equal to 16, and the data processing flow is basically the same as the mode one described above, except that the mode supports two HDMI2.1 simultaneous inputs (one with a resolution of 3840x4320x120Hz, and the two spells are 8K120 Hz). The output part, the HDMI2.0 (and the following version) output IP packages the image data (2K 120 Hz), transmits to the high-speed transceiver, and transmits to the external terminal device (1/16 sub-screen system), the effect is as shown in mode three in fig. 4. In the third mode, one path of HDMI2.1 supports transmission of 8K60Hz video at the highest, and therefore two paths of HDMI2.1 are required to meet the 8K120Hz requirement. The high refresh rate of 120Hz can bring better picture ornamental effect. The three modes support the audio signal to be de-embedded from the HDMI2.1 signal and transmitted to a sound system through an S/PDIF digital audio interface, so that the synchronous presentation of video and audio effects is completed.
Therefore, an HDMI2.1 input interface is added in the 8K ultra high definition video conversion point screen system in the embodiment, a single cable (one path) can transmit 8K60Hz video signals, and two cables (two paths) can transmit 8K120Hz video signals. The output end of the system supports the highest 16-channel HDMI2.0 (and the following versions) output, and the HDMI interface has wide application range, so the system can adapt to more application scenes (including but not limited to an 8K outdoor LED display screen, an 8K indoor LED display screen and an 8K television). In addition, the system has the DDR4 one-frame buffering function, so that the system can flexibly divide and output the highest 16 paths of HDMI2.0 (and the following versions) signal point screens. In the video processing module, a dual-port RAM is used for primary buffering and cross-pixel clock domain, so that high-bandwidth DDR4 data throughput is guaranteed, and the transmission efficiency of DDR4 is fully utilized as far as possible by adopting a read/write time-sharing multiplexing mode (for example, writing one row and reading one row, namely, the read/write respectively occupies 1/2 time). The system is realized based on the FPGA chip, has high flexibility, and can change the logic design of the FPGA so as to support a screen with higher resolution, such as a 10K60Hz screen in the future.
Based on the above embodiment, the embodiment of the present invention further provides an 8K ultra-high definition video conversion point screen method, as shown in fig. 5, including the following steps:
Step S100, obtaining a video signal source through a video input interface, and performing protocol decoding on the video signal source to obtain an 8K video signal;
Step 200, caching the image corresponding to the 8K video signal through a memory, and carrying out segmentation processing on the cached image frame according to a preset segmentation mode to obtain a segmented image;
And step S300, carrying out protocol coding on the segmented image through a video output interface to obtain coded image data, and converting the coded image data into a high-speed serial video signal and transmitting the high-speed serial video signal to external terminal equipment.
The specific implementation process has been described in the above embodiments, and will not be described here. This embodiment
In summary, the invention discloses an 8K ultra-high definition video conversion point screen system and a point screen method, wherein the system comprises the following steps: the device comprises a video control module, a storage module in communication connection with the video control module and external terminal equipment in communication connection with the video control module; wherein, the video control module includes: the video processing system comprises two paths of video input interfaces, a video processing module which is in communication connection with the two paths of video input interfaces, and a video output interface which is in communication connection with the video processing module, wherein the video output interface is in communication connection with the external terminal equipment. The invention can transmit 8K120Hz video signals by using two paths of video input interfaces, and can adapt to more application scenes.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. An 8K ultra high definition video conversion point screen system, the system comprising: the device comprises a video control module, a storage module in communication connection with the video control module and external terminal equipment in communication connection with the video control module;
Wherein, the video control module includes: the video processing system comprises two paths of video input interfaces, a video processing module and a video output interface, wherein the video processing module is respectively in communication connection with the two paths of video input interfaces, the video output interface is in communication connection with the video processing module, and the video output interface is in communication connection with the external terminal equipment;
The memory module is a high-bandwidth DDR4 memory;
The video processing module comprises: a dual port RAM; the two dual-port RAMs are respectively connected with the two paths of video input interfaces;
the video processing module further includes: the dual-port RAM comprises a video data channel selection unit connected with the dual-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit and a plurality of sub dual-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; each sub dual-port RAM is respectively connected with one external terminal device;
The DDR4 read-write control unit adopts a time division multiplexing control read-write mode;
The high-bandwidth DDR4 memory is used for caching an input image, and the control logic of the high-bandwidth DDR4 memory writes pixels read from the high-bandwidth DDR4 memory into a next-stage sub-dual-port RAM according to a specific division mode, wherein the specific division mode comprises an SQD division mode and a horizontal quarter division mode, and the SQD division mode and the horizontal quarter division mode are matched with the number of the sub-dual-port RAMs.
2. The 8K ultra-high definition video conversion point screen system according to claim 1, wherein the two paths of video input interfaces are respectively in communication connection with a preset 8K set top box.
3. The 8K ultra high definition video conversion point screen system of claim 2, wherein both of the video input interfaces are HDMI2.1 input interfaces, and each of the HDMI2.1 input interfaces is communicatively coupled to the 8K set top box via a high speed transceiver.
4. The 8K ultra-high definition video conversion point screen system according to claim 1, wherein the video output interfaces are provided with a plurality of paths, and each path of video output interface is respectively in communication connection with one external terminal device.
5. The 8K ultra high definition video conversion point screen system according to claim 4, wherein the video output interface is an HDMI2.0 output interface, and each path of the HDMI2.0 output interface is connected to the external terminal device through a high-speed transceiver.
6. The 8K ultra high definition video conversion point screen system of claim 1, wherein the number of sub dual port RAMs is the same as the number of video output interfaces.
7. An 8K ultra-high definition video conversion point screen method, comprising:
Acquiring a video signal source through a high-speed video interface, and performing protocol decoding on the video signal source to obtain an 8K video signal;
caching the image corresponding to the 8K video signal through a memory, and segmenting the cached image frame according to a preset segmentation mode to obtain a segmented image;
Performing protocol coding on the segmented image through a video output interface to obtain coded image data, converting the coded image data into a high-speed serial video signal and transmitting the high-speed serial video signal to external terminal equipment;
the memory is a high-bandwidth DDR4 memory;
the 8K video signal is transmitted to a video processing module, and the video processing module comprises: a dual port RAM; the two dual-port RAMs are respectively connected with two paths of video input interfaces;
the video processing module further includes: the dual-port RAM comprises a video data channel selection unit connected with the dual-port RAM, a DDR4 read-write control unit connected with the video data channel selection unit and a plurality of sub dual-port RAMs connected with the DDR4 read-write control unit; the DDR4 read-write control unit is in communication connection with the high-bandwidth DDR4 memory; each sub dual-port RAM is respectively connected with one external terminal device;
The DDR4 read-write control unit adopts a time division multiplexing control read-write mode; and writing the pixel points read from the high-bandwidth DDR4 memory into a sub dual-port RAM of the next stage according to the preset dividing mode by control logic of the high-bandwidth DDR4 memory, wherein the preset dividing mode comprises an SQD dividing mode and a horizontal quarter dividing mode, and the SQD dividing mode and the horizontal quarter dividing mode are matched with the number of the sub dual-port RAMs.
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