CN104900531A - 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置 - Google Patents

一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置 Download PDF

Info

Publication number
CN104900531A
CN104900531A CN201510308733.6A CN201510308733A CN104900531A CN 104900531 A CN104900531 A CN 104900531A CN 201510308733 A CN201510308733 A CN 201510308733A CN 104900531 A CN104900531 A CN 104900531A
Authority
CN
China
Prior art keywords
layer
film transistor
oxide semiconductor
semiconductor layer
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510308733.6A
Other languages
English (en)
Inventor
王珂
宁策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510308733.6A priority Critical patent/CN104900531A/zh
Publication of CN104900531A publication Critical patent/CN104900531A/zh
Priority to US15/156,858 priority patent/US10141444B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置，该氧化物薄膜晶体管的制作方法包括：在衬底基板上形成氧化物半导体层图形；采用预定光源照射所述氧化物半导体层的两侧区域，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层；形成源电极和漏电极，所述源电极和漏电极分别通过所述欧姆接触层与所述半导体有源层连接。采用本发明的方案，在形成欧姆接触层的同时，可以消除现有的等离子体处理工艺对薄膜晶体管各膜层的损伤，且通过光照方式形成的导体性能稳定。

Description

一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置。
背景技术
氧化物薄膜晶体管主要包括：栅电极、氧化物半导体层、源电极和漏电极，其中，为增强源电极、漏电极与氧化物半导体层的欧姆接触，可以采用等离子体(plasma)处理工艺，将氧化物半导体层的与源电极和漏电极接触的两侧区域处理成导体。等离子体处理工艺主要是利用PECVD(等离子体增强化学气相沉积法)设备或者Dry Etch(干法刻蚀)设备的等离子体环境，采用如He(氦)、Ar(氩)、SF6(六氟化硫)等气体的等离子体，将氧化物半导体层的与源电极和漏电极接触的两侧区域处理成导体。
然而，等离子体处理会对薄膜晶体管的其他各层造成损伤，影响薄膜晶体管性能。且，经过等离子体处理的导体容易在后续的工艺中产生可逆变化，由导体恢复成半导体，从而导致器件失效。
发明内容
有鉴于此，本发明提供一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置，用于解决等离子体处理工艺容易对薄膜晶体管各膜层造成损伤的问题。
为解决上述技术问题，本发明提供一种氧化物薄膜晶体管的制作方法，
在衬底基板上形成氧化物半导体层图形；
采用预定光源照射所述氧化物半导体层的两侧区域，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层；
形成源电极和漏电极，所述源电极和漏电极分别通过所述欧姆接触层与所述半导体有源层连接。
优选地，所述氧化物薄膜晶体管为顶栅结构的薄膜晶体管；
所述衬底基板上形成氧化物半导体层图形的步骤之前还包括：
在衬底基板上形成遮光层的图形，所述遮光层的图形在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；
其中，所述采用预定光源照射所述氧化物半导体层图形的两侧区域的步骤具体为：
采用预定光源在所述衬底基板的远离所述遮光层的一侧，对所述氧化物半导体层图形的未被所述遮光层遮挡的两侧区域进行照射。
优选地，在衬底基板上形成遮光层的图形之后，形成氧化物半导体层图形之前还包括：
形成无机绝缘介质层。
优选地，所述无机绝缘介质层采用二氧化硅材料制成。
优选地，所述采用预定光源照射所述氧化物半导体层图形的两侧区域的步骤具体为：
提供一遮光板，所述遮光板在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；
以所述遮光板作为遮挡，采用预定光源对所述氧化物半导体层图形的未被所述遮光板遮挡的两侧区域进行照射。
优选地，所述预定光源为紫外光源。
优选地，所述紫外光源的波长范围为173nm～365nm，照射持续时间为1～30秒。
优选地，所述氧化物半导体层采用IGZO或ITZO材料制成。
本发明还提供一种氧化物薄膜晶体管阵列基板的制作方法，包括采用上述方法形成氧化物薄膜晶体管的步骤。
本发明还提供一种显示装置，包括上述氧化物薄膜晶体管阵列基板。
本发明还提供一种氧化物薄膜晶体管，包括：欧姆接触层、半导体有源层、源极和漏极，所述源极和漏极通过所述欧姆接触层与所述半导体有源层连接，所述欧姆接触层和所述半导体有源层是采用预定光源对一氧化物半导体层图形照射形成，其中，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层。
本发明还提供一种氧化物薄膜晶体管阵列基板，包括上述氧化物薄膜晶体管。
本发明的上述技术方案的有益效果如下：
通过预定光源照射氧化物半导体的用于与源电极和漏电极接触的两侧区域，形成导体(即欧姆接触层)，以增强源电极、漏电极与氧化物半导体层的欧姆接触，同时可以消除现有的等离子体处理工艺对薄膜晶体管各膜层的损伤，且通过光照方式形成的导体性能稳定。
附图说明
图1为本发明实施例的采用光源照射氧化物半导体使其转变为导体的原理图；
图2为IGZO薄膜晶体管NBS(负偏压压力测试)测试结果示意图；
图3为IGZO薄膜晶体管NBIS(负偏压光照压力测试)测试结果示意图；
图4A-4E为本发明实施例的底栅结构的氧化物薄膜晶体管的形成方法示意图；
图5为本发明实施例的顶栅结构的氧化物薄膜晶体管的一形成方法示意图；
图6A-6G为本发明实施例的顶栅结构的氧化物薄膜晶体管的另一形成方法示意图；
图7为本发明实施例的采用光照方式形成的氧化物薄膜晶体管的I-V曲线，以及采用等离子体处理工艺形成的氧化物薄膜晶体管产生可逆变化后的I-V曲线；
附图标记说明：
101衬底基板；102栅电极；103栅绝缘层；104氧化物半导体层；1041欧姆接触层；1042半导体有源层；1051源电极；1052漏电极；106遮光层；107无机绝缘介质层；108中间绝缘层；1081过孔；201预定光源；202遮光板。
具体实施方式
下面将结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
氧化物半导体(如IGZO(铟镓锌氧化物)、ITZO(铟锡锌氧化物)等)是一种带隙较窄的半导体材料，在绝对零度时，如图1所示，价带是满带，导带是空带，不能导电。由于氧化物半导体的禁带宽度较小，当被预定光源(如紫外光)照射时，价带顶的电子吸收预定光源的能量可以被激发到导带，而价带顶形成空穴层，导带底形成电子层，氧化物半导体就可以转变为导体。
请参考图2和图3，图2为IGZO薄膜晶体管NBS测试结果示意图，图3为IGZO薄膜晶体管NBIS测试结果示意图。图中，Vgs为栅电极与源电极之间的电压，Vds为源电极和漏电极之间的电压，Id为漏极电流。
从图2中可以看出，在对IGZO薄膜晶体管施加Vgs＝-30V，Vds＝10.1V的电压条件下，3600s后，Vth(阈值电压，为Id＝10-8A时对应的Vg(栅电极)电压)变化不大，仍维持半导体的特性。而，请参考图3，在对IGZO薄膜晶体管施加Vgs＝-30V，Vds＝10.1V的电压，并在10000lux亮度的紫外光照射情况下，Vth负偏约15V，即呈现出导体化的趋势。
从上述实验数据可以证实，氧化物半导体能够在预定光源的照射下变为导体。
基于上述原理，本发明实施例提供一种氧化物薄膜晶体管的制作方法，包括以下步骤：
步骤S11：在衬底基板上形成氧化物半导体层图形；
步骤S12：采用预定光源照射所述氧化物半导体层的两侧区域，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层；
步骤S12：形成源电极和漏电极，所述源电极和漏电极分别通过所述欧姆接触层与所述半导体有源层连接。
通过上述方法，通过预定光源照射氧化物半导体的用于与源电极和漏电极接触的两侧区域，形成导体(即欧姆接触层)，以增强源电极、漏电极与氧化物半导体层的欧姆接触，同时可以消除现有的等离子体处理工艺对薄膜晶体管各膜层的损伤，且通过光照方式形成的导体性能稳定。
上述实施例中的氧化物薄膜晶体管可以为顶栅结构的薄膜晶体管(即栅电极位于半导体有源层和源漏电极之间)，也可以为底栅结构的薄膜晶体管(即半导体有源层位于栅电极和源漏电极之间)。
当所述氧化物薄膜晶体管为底栅结构的薄膜晶体管时，可以采用以下方法形成欧姆接触层：
步骤S121：提供一遮光板，所述遮光板在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；即，遮光板的尺寸小于氧化物半导体层图形的尺寸。
步骤S122：以所述遮光板作为遮挡，采用预定光源对所述氧化物半导体层图形的未被所述遮光板遮挡的两侧区域进行照射，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层。
请参考图4A-4E，图4A-4E为本发明实施例的底栅结构的氧化物薄膜晶体管的形成方法示意图，所述方法包括以下步骤：
步骤S21：在衬底基板101上形成栅电极102；
栅电极102可采用Mo、Al、Cu等金属材料制成，厚度为200-300nm。
步骤S22：形成栅绝缘层103(Gate insulator)；
栅绝缘层103可使用单层结构(如SiO2单层结构)、双层结构(如SiO2/SiNx双层结构)或三层结构(SiO2/SiON/SiNx)。优选地，与氧化物半导体层图形接触的一层为SiO2层，这样可以确保氧化物半导体层中含氢量最小化。栅绝缘层层的厚度为200-300nm。
步骤S23：形成氧化物半导体层104的图形；
氧化物半导体层104的厚度为40-70nm，可使用单层结构的氧化物半导体，也可使用多层结构，每一层氧化物的氧含量不同。
步骤S24：提供一遮光板201，以所述遮光板201作为遮挡，采用预定光源202对所述氧化物半导体层104的未被所述遮光板201遮挡的两侧区域进行照射，所述氧化物半导体层104的被照射的两侧区域形成欧姆接触层1041，未被照射的区域形成半导体有源层1042。
步骤S25：形成源电极1051和漏电极1052，所述源电极1051和漏电极1052分别通过所述欧姆接触层1041与所述半导体有源层1042连接。
其中，源电极1051和漏电极1052可采用Mo、Al、Cu等金属材料制成，厚度为200-300nm。
本实施例的采用遮光板的方式简单易行，成本较低。
当所述氧化物薄膜晶体管为顶栅结构的薄膜晶体管时，也可以采用上述遮光板的方法形成欧姆接触层，请参考图5，具体实现方法在此不再详细说明。
此外，当所述氧化物薄膜晶体管为顶栅结构的薄膜晶体管时，还可以采用以下方法形成欧姆接触层：
具体的，在所述衬底基板上形成氧化物半导体层图形的步骤之前还包括：
在衬底基板上形成遮光层的图形，所述遮光层的图形在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；即，遮光层的尺寸小于化物半导体层图形的尺寸。
其中，采用预定光源照射所述氧化物半导体层的两侧区域的步骤具体为：
采用预定光源在所述衬底基板的远离所述遮光层的一侧，对所述氧化物半导体层图形的未被所述遮光层遮挡的两侧区域进行照射，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层。
请参考图6A-6G，图6A-6G为本发明实施例的顶栅结构的氧化物薄膜晶体管的形成方法示意图，所述方法包括以下步骤：
步骤S31：在衬底基板101上形成遮光层106；
该遮光层106可以采用金属材料制成，如Mo、Al等金属，也可以采用有机材料制成。该遮光层106的厚度为200-300nm。
步骤S32：形成无机绝缘介质层107；
形成无机绝缘介质层107的作用是为了避免遮光层106对氧化物半导体层的影响，保证薄膜晶体管的性能。优选地，所述无机绝缘介质层107采用二氧化硅材料制成，厚度为200-400nm。
步骤S33：形成氧化物半导体层104的图形；其中，所述遮光层106的图形在所述衬底基板101上的正投影完全落入所述氧化物半导体层104图形在所述衬底基板101上的正投影区域之内；
氧化物半导体层104的厚度为40-70nm，可使用单层结构的氧化物半导体，也可使用多层结构，每一层氧化物的氧含量不同。
步骤S34：采用预定光源202在所述衬底基板101的远离所述遮光层106的一侧，对所述氧化物半导体层104的未被所述遮光层106遮挡的两侧区域进行照射，所述氧化物半导体层104的被照射的两侧区域形成欧姆接触1041，未被照射的区域形成半导体有源层1042；
上述遮光层106除了可以作为形成欧姆接触层1041时的遮光部件之外，还可以保护半导体有源层1042不受背光或其他外界自然光的照射，提高薄膜晶体管的稳定性。
步骤S35：形成栅绝缘层103和栅电极102的图形；
栅绝缘层103可使用单层结构(如SiO2单层结构)、双层结构(如SiO2/SiNx双层结构)或三层结构(SiO2/SiON/SiNx)。优选地，与氧化物半导体层图形接触的一层为SiO2层，这样可以确保氧化物半导体层中含氢量最小化。栅绝缘层103的厚度为200-300nm。
栅电极102可采用Mo、Al、Cu等金属材料制成，厚度为200-300nm。
在本发明的其他实施例中，栅绝缘层103也可以为整层结构。
步骤S36：形成中间绝缘层108，并形成贯通所述中间绝缘层108的过孔1081，所述过孔1081对应所述欧姆接触层1041位置。
中间绝缘层108可以为SiNx单层结构，厚度为200-400nm。
步骤S37：形成源电极1051和漏电极1052，所述源电极1051和漏电极1052通过所述过孔1081与所述欧姆接触层1041接触，并借由所述欧姆接触层1041与所述半导体有源层1042连接。
其中，源电极1051和漏电极1052可采用Mo、Al、Cu等金属材料制成，厚度为200-300nm。
上述各实施例中的氧化物半导体层可以采用IGZO或ITZO等氧化物半导体材料制成。
用于照射氧化物半导体层的预定光源可以为紫外光源，或者其他类型的光源，例如X射线等。当采用紫外光源于照射氧化物半导体层时，优选地，采用波长范围为173nm～365nm的紫外光源，且照射持续时间为1～30秒。
请参考图7，图7为本发明实施例的采用光照方式形成的氧化物薄膜晶体管的I-V曲线(图7(1))，以及采用等离子体处理工艺形成的氧化物薄膜晶体管产生可逆变化后的I-V曲线(图7(2))。从图中可以看出，采用等离子体处理工艺得到的欧姆接触层如产生可逆变化，由导体恢复成半导体后，欧姆接触层的电阻率如大于1KΩ/□(Ω/□为方块电阻，是评价薄膜电阻特性的单位)会导致开态电流降低，如果电阻大到一定程度会导致器件失去开关特性而失效。
本发明还提供一种氧化物薄膜晶体管阵列基板的制作方法，包括形成氧化物薄膜晶体管的步骤，其中，形成氧化物薄膜晶体管的方法可采用上述任一实施例中采用的方法，在此不再一一描述。
本发明实施例的氧化物薄膜晶体管阵列基板的形成方法可以包括以下步骤：
步骤S41-47：在衬底基板上形成遮光层、无机绝缘介质层、欧姆接触层、半导体有源层、栅绝缘层、栅电极、中间绝缘层、源电极和漏电极。上述步骤请参考图6A-图6G所示的方法，在此不再一一说明。
步骤S48：形成钝化层。
步骤S49：形成像素电极。
像素电极可以采用ITO或IZO等透明导电材料制成，厚度为40-70nm。
在阵列基板为包括公共电极的阵列基板时，所述方法还包括：在像素电极之上形成第二层钝化层，以及在第二层钝化层上形成公共电极的步骤。
其中，第二层钝化层可以为单层结构(如SiO2单层结构)或者为双层结构(如SiO2/SiNx双层结构)，厚度为200-300nm。公共电极可以采用ITO或IZO等透明导电材料制成，厚度为40-70nm。
为了提高氧化物薄膜晶体管的稳定性，并降低像素电极和公共电极的电阻率，需要在器件完成后进行最终退火处理，退火温度一般在200-300℃之间。
本发明还提供一种氧化物薄膜晶体管，包括：欧姆接触层、半导体有源层、源极和漏极，所述源极和漏极通过所述欧姆接触层与所述半导体有源层连接，所述欧姆接触层和所述半导体有源层是采用预定光源对一氧化物半导体层图形照射形成，其中，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层。
本发明还提供一种氧化物薄膜晶体管阵列基板，包括上述实施例中所述的氧化物薄膜晶体管。
本发明还提供一种显示装置，包括上述实施例中所述的氧化物薄膜晶体管阵列基板。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种氧化物薄膜晶体管的制作方法，其特征在于，包括：
在衬底基板上形成氧化物半导体层图形；
采用预定光源照射所述氧化物半导体层的两侧区域，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层；
形成源电极和漏电极，所述源电极和漏电极分别通过所述欧姆接触层与所述半导体有源层连接。
2.根据权利要求1所述的氧化物薄膜晶体管的制作方法，其特征在于，所述氧化物薄膜晶体管为顶栅结构的薄膜晶体管；
所述衬底基板上形成氧化物半导体层图形的步骤之前还包括：
在衬底基板上形成遮光层的图形，所述遮光层的图形在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；
其中，所述采用预定光源照射所述氧化物半导体层图形的两侧区域的步骤具体为：
采用预定光源在所述衬底基板的远离所述遮光层的一侧，对所述氧化物半导体层图形的未被所述遮光层遮挡的两侧区域进行照射。
3.根据权利要求2所述的氧化物薄膜晶体管的制作方法，其特征在于，在衬底基板上形成遮光层的图形之后，形成氧化物半导体层图形之前还包括：
形成无机绝缘介质层。
4.根据权利要求3所述的氧化物薄膜晶体管的制作方法，其特征在于，所述无机绝缘介质层采用二氧化硅材料制成。
5.根据权利要求1所述的氧化物薄膜晶体管的制作方法，其特征在于，所述采用预定光源照射所述氧化物半导体层图形的两侧区域的步骤具体为：
提供一遮光板，所述遮光板在所述衬底基板上的正投影完全落入所述氧化物半导体层图形在所述衬底基板上的正投影区域之内；
以所述遮光板作为遮挡，采用预定光源对所述氧化物半导体层图形的未被所述遮光板遮挡的两侧区域进行照射。
6.根据权利要求1-5任一项所述的氧化物薄膜晶体管的制作方法，其特征在于，所述预定光源为紫外光源。
7.根据权利要求6所述的氧化物薄膜晶体管的制作方法，其特征在于，所述紫外光源的波长范围为173nm～365nm，照射持续时间为1～30秒。
8.根据权利要求1所述的氧化物薄膜晶体管的制作方法，其特征在于，所述氧化物半导体层采用IGZO或ITZO材料制成。
9.一种氧化物薄膜晶体管阵列基板的制作方法，其特征在于，包括采用如权利要求1-8所述的方法形成氧化物薄膜晶体管的步骤。
10.一种氧化物薄膜晶体管，包括：欧姆接触层、半导体有源层、源极和漏极，所述源极和漏极通过所述欧姆接触层与所述半导体有源层连接，其特征在于，所述欧姆接触层和所述半导体有源层是采用预定光源对一氧化物半导体层图形照射形成，其中，所述氧化物半导体层的被照射的两侧区域形成欧姆接触层，未被照射的区域形成半导体有源层。
11.一种氧化物薄膜晶体管阵列基板，其特征在于，包括如权利要求10所述的氧化物薄膜晶体管。
12.一种显示装置，其特征在于，包括如权利要求11所述的氧化物薄膜晶体管阵列基板。
CN201510308733.6A 2015-06-08 2015-06-08 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置 Pending CN104900531A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201510308733.6A CN104900531A (zh) 2015-06-08 2015-06-08 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置
US15/156,858 US10141444B2 (en) 2015-06-08 2016-05-17 Oxide thin-film transistor with illuminated OHMIC contact layers, array substrate and methods for manufacturing the same, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510308733.6A CN104900531A (zh) 2015-06-08 2015-06-08 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置

Publications (1)

Publication Number Publication Date
CN104900531A true CN104900531A (zh) 2015-09-09

Family

ID=54033123

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510308733.6A Pending CN104900531A (zh) 2015-06-08 2015-06-08 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置

Country Status (2)

Country Link
US (1) US10141444B2 (zh)
CN (1) CN104900531A (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107425075A (zh) * 2017-05-17 2017-12-01 厦门天马微电子有限公司 薄膜晶体管器件及其制造方法、阵列基板以及显示装置
CN107564949A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 氧化物tft、其制造方法、使用其的显示面板和显示装置
CN107946244A (zh) * 2017-11-22 2018-04-20 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN110416313A (zh) * 2019-07-19 2019-11-05 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板及其制作方法
CN112786453A (zh) * 2021-01-18 2021-05-11 合肥鑫晟光电科技有限公司 薄膜晶体管及其制作方法和显示装置及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108807549B (zh) * 2018-06-01 2021-03-23 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288122A (ja) * 2006-03-22 2007-11-01 Seiko Epson Corp アクティブマトリクス基板の製造方法、アクティブマトリクス基板、電気光学装置及び電子機器
CN102064109A (zh) * 2010-11-08 2011-05-18 友达光电股份有限公司 薄膜晶体管及其制造方法
CN104282768A (zh) * 2013-07-10 2015-01-14 日新电机株式会社 薄膜晶体管的制作方法
CN104637950A (zh) * 2013-11-14 2015-05-20 上海和辉光电有限公司 薄膜晶体管驱动背板及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9919913D0 (en) * 1999-08-24 1999-10-27 Koninkl Philips Electronics Nv Thin-film transistors and method for producing the same
KR100584716B1 (ko) * 2004-04-06 2006-05-29 엘지.필립스 엘시디 주식회사 구동회로 일체형 액정표시장치용 어레이 기판의 제조 방법
JP5116225B2 (ja) * 2005-09-06 2013-01-09 キヤノン株式会社 酸化物半導体デバイスの製造方法
US20070269750A1 (en) * 2006-05-19 2007-11-22 Eastman Kodak Company Colored masking for forming transparent structures
KR101014473B1 (ko) * 2006-06-02 2011-02-14 가시오게산키 가부시키가이샤 산화아연의 산화물 반도체 박막층을 포함하는 반도체 장치및 그 제조방법
US8436349B2 (en) * 2007-02-20 2013-05-07 Canon Kabushiki Kaisha Thin-film transistor fabrication process and display device
US8153352B2 (en) * 2007-11-20 2012-04-10 Eastman Kodak Company Multicolored mask process for making display circuitry
TWI475615B (zh) * 2010-07-21 2015-03-01 Univ Nat Chiao Tung 自我對準之頂閘極薄膜電晶體及其製法
TWI423346B (zh) * 2010-10-26 2014-01-11 Au Optronics Corp 薄膜電晶體及其製造方法
CN102130009B (zh) * 2010-12-01 2012-12-05 北京大学深圳研究生院 一种晶体管的制造方法
WO2012090799A1 (en) * 2010-12-28 2012-07-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR102135275B1 (ko) * 2013-07-29 2020-07-20 삼성디스플레이 주식회사 박막 트랜지스터 기판, 이의 제조 방법 및 이를 포함하는 표시 장치
KR102281300B1 (ko) * 2013-09-11 2021-07-26 삼성디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터의 제조 방법 및 박막 트랜지스터를 포함하는 표시장치
KR20150061302A (ko) * 2013-11-27 2015-06-04 삼성디스플레이 주식회사 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
US10121898B2 (en) * 2014-05-09 2018-11-06 Joled Inc. Thin-film transistor substrate and method of manufacturing the same
KR20160043576A (ko) * 2014-10-13 2016-04-22 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288122A (ja) * 2006-03-22 2007-11-01 Seiko Epson Corp アクティブマトリクス基板の製造方法、アクティブマトリクス基板、電気光学装置及び電子機器
CN102064109A (zh) * 2010-11-08 2011-05-18 友达光电股份有限公司 薄膜晶体管及其制造方法
CN104282768A (zh) * 2013-07-10 2015-01-14 日新电机株式会社 薄膜晶体管的制作方法
CN104637950A (zh) * 2013-11-14 2015-05-20 上海和辉光电有限公司 薄膜晶体管驱动背板及其制造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564949A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 氧化物tft、其制造方法、使用其的显示面板和显示装置
US10396099B2 (en) 2016-06-30 2019-08-27 Lg Display Co., Ltd. Coplanar type oxide thin film transistor, method of manufacturing the same, and display panel and display device using the same
CN107564949B (zh) * 2016-06-30 2021-03-12 乐金显示有限公司 氧化物tft、其制造方法、使用其的显示面板和显示装置
CN107425075A (zh) * 2017-05-17 2017-12-01 厦门天马微电子有限公司 薄膜晶体管器件及其制造方法、阵列基板以及显示装置
CN107425075B (zh) * 2017-05-17 2020-05-29 厦门天马微电子有限公司 薄膜晶体管器件及其制造方法、阵列基板以及显示装置
CN107946244A (zh) * 2017-11-22 2018-04-20 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN107946244B (zh) * 2017-11-22 2020-08-04 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN110416313A (zh) * 2019-07-19 2019-11-05 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板及其制作方法
US11239331B2 (en) 2019-07-19 2022-02-01 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor substrate and method of fabricating same
CN112786453A (zh) * 2021-01-18 2021-05-11 合肥鑫晟光电科技有限公司 薄膜晶体管及其制作方法和显示装置及其制作方法

Also Published As

Publication number Publication date
US20160359053A1 (en) 2016-12-08
US10141444B2 (en) 2018-11-27

Similar Documents

Publication Publication Date Title
CN104900531A (zh) 一种氧化物薄膜晶体管、阵列基板及制作方法、显示装置
KR101015338B1 (ko) 박막 트랜지스터의 제조방법
CN103219391B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
US9748276B2 (en) Thin film transistor and method of manufacturing the same, array substrate and display device
CN103383989B (zh) 像素结构的制造方法及其结构
CN104253159A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
KR20110095615A (ko) 박막 트랜지스터 기판, 이의 제조 방법 및 이를 포함하는 표시 장치
KR102281848B1 (ko) 박막 트랜지스터 제조 방법과 박막 트랜지스터
US20160343739A1 (en) Thin film transistor, method of manufacturing thin film transistor, array substrate and display device
KR101922937B1 (ko) 박막트랜지스터 기판 및 이의 제조 방법
CN103018990A (zh) 一种阵列基板和其制备方法、及液晶显示装置
CN105140271A (zh) 薄膜晶体管、薄膜晶体管的制造方法及显示装置
CN104851910A (zh) 薄膜晶体管、阵列基板、制备方法、显示面板和显示装置
CN103578984B (zh) 半导体元件及其制造方法
CN103489921A (zh) 一种薄膜晶体管及其制造方法、阵列基板及显示装置
CN104124277A (zh) 一种薄膜晶体管及其制作方法和阵列基板
CN105097710A (zh) 薄膜晶体管阵列基板及其制造方法
CN107293493A (zh) 铟镓锌氧化物薄膜晶体管的制作方法
US10050092B2 (en) Array substrate, manufacturing method thereof and display device
CN104409415A (zh) 一种阵列基板及其制备方法、显示装置
CN104183603B (zh) 一种阵列基板及其制备方法、显示装置
CN104157610A (zh) 氧化物半导体tft基板的制作方法及其结构
CN105070729A (zh) 一种阵列基板和显示装置
CN104465670A (zh) 一种阵列基板及其制作方法、显示装置
US9640553B2 (en) Thin-film transistor (TFT), manufacturing method thereof, array substrate and display device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150909

RJ01 Rejection of invention patent application after publication