CN103531560A - 芯片的封装结构及其制造方法 - Google Patents
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Abstract
本发明提供了一种芯片的封装结构及其制造方法,包括:承载盘、芯片、多个第一导电块和塑封料;所述承载盘的正面具有多个凸起焊盘;所述芯片具有一有源面,所述第一导电块的一端与所述有源面电连接,所述第一导电块的另一端与所述凸起焊盘电连接;所述塑封料包围所述芯片并填满所述承载盘和所述芯片之间的空间。在本发明提供的芯片的封装结构及其制造方法中,通过刻蚀在承载盘的正面形成凸起焊盘,在凸起焊盘与芯片的有源面实现电连接的同时,增大了塑封料在芯片与承载盘之间的流通通道,使得塑封料能够填满芯片与承载盘之间的空间,因此塑封之前不必进行底部填充工艺,降低了封装成本。
Description
技术领域
本发明涉及芯片封装技术领域,特别涉及一种芯片的封装结构及其制造方法。
背景技术
随着科学技术的发展,各种芯片封装技术不断涌现,随之出现了各种封装形式的芯片。在各种封装形式的芯片中,双侧引脚扁平封装(dual flat packagee,简称DFP)和四侧无引脚扁平封装(quad flat non-leaded package,简称QFN)特别是装载方式采用倒装的QFN/DFN芯片,即倒装QFN/DFN芯片由于具有厚度薄、集成度高及散热性能好等优点,近年来得到广泛的应用。倒装QFN/DFN芯片在进行封装时芯片的正面朝下面对承载盘,所述芯片的正面与所述承载盘实现电连接,。其中,芯片的正面即芯片的有源面,所述有源面上排布有各种器件,所述承载盘可以为引线框架上的大面积中间焊盘,也可以为印刷电路板。
请参考图1,其为现有技术的倒装QFN/DFN芯片的封装结构示意图。如图1所示,现有技术中倒装QFN/DFN芯片的封装结构10包括承载盘11、芯片12、多个导电块13、塑封料14和引脚15,其中,为了保证QFN/DFN芯片具有良好的散热性能,所述承载盘11的面积一般比较大,所述引脚15位于所述承载盘11的边缘,所述引脚15的厚度与所述承载盘11的厚度相同,芯片12具有一有源面,所述有源面具有电极用于各个器件的电性引出,所述电极上设置有焊垫(图中未示出),所述焊垫的位置根据有源面的电极位置进行设置,一般呈阵列排列,每个焊垫分别通过导电块13与所述承载盘11或引脚15电连接。
可见,整个承载盘11的厚度都是相同的,所述导电块13的厚度等于所述芯片12与承载盘11的间距。通常的,所述导电块13采用的材料为金属铜,所述导电块13的厚度一般在45μm左右。
由于芯片的厚度很薄,而且塑封料14在承载盘11和所述芯片12之间的流动空间只有导电块13之间的空隙,塑封料14无法在所述承载盘11和所述芯片12之间正常流通并填满所述承载盘11与所述芯片12之间的空间,导致芯片容易损坏。为了解决这一问题,目前采用的方法是在进行塑封工艺之前,通过底部填充工艺在芯片12与承载盘11之间填满填充胶16,所述填充胶16的颗粒非常小同时具有良好的流动性,因此能够保证填充质量,解决细间距的封装结构存在的问题。如图1所示,所述承载盘11和所述芯片12之间填充有填充胶16,包围芯片12的其他区域填充有塑封料14。
目前,各种芯片包括倒装QFN/DFN芯片的厚度都越来越薄,为了保证封装质量塑封之前必须要在所述承载盘11和所述芯片12之间进行底部填充。但是,底部填充工艺会增加了芯片封装的成本和封装工艺的复杂程度。
基此,如何改善现有技术中芯片封装时由于芯片与承载盘的间距太小使得塑封料无法填满芯片与承载盘之间的空间导致器件容易损坏的问题已经成为本领域技术人员亟需解决的技术问题。
发明内容
本发明的目的在于提供一种芯片的封装结构及其制造方法,以解决现有的芯片封装过程中由于芯片与承载盘的间距小使得塑封料无法填满芯片与承载盘之间的空间导致器件容易损坏的问题。
为解决上述技术问题,本发明提供一种芯片的封装结构,所述芯片的封装结构包括:承载盘、芯片、多个第一导电块和塑封料;
所述承载盘的正面设置有多个凸起焊盘;
所述芯片具有一有源面,所述第一导电块的一端与所述有源面电连接,所述第一导电块的另一端与所述凸起焊盘电连接;
所述塑封料包围所述芯片并填满所述承载盘和所述芯片之间的空间。
优选的,在所述的芯片的封装结构中,所述凸起焊盘的厚度范围在20μm到250μm之间。
优选的,在所述的芯片的封装结构中,所述塑封料为环氧树脂。
优选的,在所述的芯片的封装结构中,还包括:若干个引脚;
所述引脚设置于所述承载盘的边缘,所述引脚的表面设置有引脚焊盘,所述引脚焊盘的表面与所述凸起焊盘的表面位于同一水平面。
优选的,在所述的芯片的封装结构中,还包括:多个第二导电块;
所述第二导电块的一端与所述有源面电连接,所述第二导电块的另一端与所述承载盘的凸起焊盘电连接。
优选的,在所述的芯片的封装结构中,所述第一导电块和第二导电块采用的材料均为金属铜,所述第一导电块和第二导电块的厚度均在45μm到60μm之间。
本发明还提供了一种芯片的封装结构的制造方法,所述芯片的封装结构的制造方法包括以下步骤:
提供一承载盘;
刻蚀所述承载盘在所述承载盘的正面形成凸起焊盘;
提供一芯片,所述芯片具有一有源面;
提供多个第一导电块;
利用所述第一导电块实现所述有源面与所述凸起焊盘的电连接;
提供塑封料;
进行塑封工艺,使所述塑封料包围所述芯片并填满所述芯片与所述承载盘之间的空间。
优选的,在所述的芯片的封装结构的制造方法中,在提供一承载盘的同时,还包括提供若干个引脚;
所述引脚位于所述承载盘的边缘,所述引脚的表面设置有引脚焊盘,所述引脚焊盘的表面与所述凸起焊盘的表面位于同一平面。
优选的,在所述的芯片的封装结构的制造方法中,在提供多个第一导电块的同时,还包括:提供多个第二导电块;
在利用所述第一导电块实现所述有源面与所述凸起焊盘的电连接的同时,还包括:利用所述第二导电块实现所述有源面与所述引脚焊盘的电连接。
优选的,在所述的芯片的封装结构的制造方法中,所述第一导电块和第二导电块采用的材料均为金属铜,所述第一导电块和第二导电块的厚度均在45μm到60μm之间。
在本发明提供的芯片的封装结构及其制造方法中,通过刻蚀在承载盘的正面形成凸起焊盘,在所述凸起焊盘与所述芯片实现电连接的同时,增大了塑封料在所述芯片与所述承载盘之间的流通通道,使得所述塑封料能够填满所述芯片与所述承载盘之间的空间,因此塑封工艺之前不必进行底部填充工艺,从而减少了芯片的封装工序,有效地降低了封装成本。
附图说明
图1是现有技术的倒装QFN/DFN芯片的封装结构示意图;
图2是本发明实施例的芯片的封装结构的制造方法的工艺流程图;
图3a至图3e是本发明实施例的芯片的封装结构的制造方法中各步骤的结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的芯片的封装结构及其制造方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图3e,其为本发明实施例的芯片的封装结构在塑封工艺之后的结构示意图。如图3e所示,所述芯片的封装结构20包括:承载盘21、芯片22、多个第一导电块23和塑封料24;所述承载盘21的正面设置有多个凸起焊盘26;所述芯片22具有一有源面27,所述第一导电块23的一端与所述有源面27电连接,所述第一导电块23的另一端与所述凸起焊盘26电连接;所述塑封料24包围所述芯片22并填满所述承载盘21和所述芯片22之间的空间。
具体的,所述承载盘21厚度均匀,其整体厚度一般在100μm到300μm之间。所述承载盘21的正面设置有多个凸起焊盘26,所述凸起焊盘26的厚度范围一般在20μm到250μm之间。所述凸起焊盘26之间形成了一定的空隙,所述空隙的大小主要与所述凸起焊盘26的厚度有关。所述凸起焊盘26的厚度越厚,空隙越大;反之,空隙越小。
所述第一导电块23的一端与所述所述芯片22的有源面27电连接,所述第一导电块23的另一端与所述承载盘21的凸起焊盘26电连接,所述芯片22与承载盘21通过多个第一导电块23实现电连接之后,所述塑封料24在所述芯片22与承载盘21之间的流动空间包括第一导电块23之间的空隙和凸起焊盘26之间的空隙。
可见,所述芯片的封装结构20中塑封料的流动空间不仅包括第一导电块23之间的空隙,还包括凸起焊盘26之间的空隙。而现有的倒装QFN/DFN芯片的封装结构10中只有导电块13之间的空隙是塑封料的流动空间,因此,在所述芯片的封装结构20中塑封料的流动空间比现有的倒装QFN/DFN芯片的封装结构10的要大。
本发明实施例中,所述塑封料24为环氧树脂,所述芯片22的周围以及所述承载盘21和所述芯片22之间的空间填充的塑封料24都是环氧树脂。
请继续参考图3e,如图3e所示,所述芯片的封装结构20还包括:若干个引脚25,所述引脚25位于所述承载盘21的边缘,所述引脚25的表面设置有引脚焊盘(图中未示出),所述引脚焊盘的表面与所述凸起焊盘26的表面位于同一水平面,每个引脚25通过所述第二导电块29与所述有源面27上的一个焊垫电连接。
其中,所述第一导电块23和第二导电块29的厚度均在45μm到60μm之间。所述第一导电块23和第二导电块29均可以采用任何导电材料,比如金、银、铜等导电金属。优选的,所述第一导电块23和第二导电块29采用的材料均为金属铜。
其中,所述凸起焊盘26和引脚25的数量及其位置都是根据芯片22上的器件数量及其位置进行设置的。
相应的,本实施例还提供了一种芯片的封装结构的制造方法。请参考图2,并结图3a至图3e,所述芯片的封装结构的制造方法包括以下步骤:
S10:提供一承载盘21;
S11:刻蚀所述承载盘21在所述承载盘21的正面形成若干个凸起焊盘26;
S12:提供一芯片22,所述芯片22具有一有源面27;
S13:提供多个第一导电块23;
S14:利用所述第一导电块23实现所述有源面27与所述凸起焊盘26的电连接;
S15:提供塑封料24;
S16:进行塑封工艺,使所述塑封料24包围所述芯片22并填满所述芯片22与所述承载盘21之间的空间。
具体的,首先,提供一厚度均匀的承载盘21和若干个引脚25。所述承载盘21和引脚25都可以采用现有的材料,其中,所述承载盘21可以是引线框架上的大面积中间焊盘,也可以是印刷电路板。如图3a所示,所述承载盘21和引脚25的厚度相等,一般都在100μm到300μm之间。所述若干个引脚25设置于所述承载盘21的边缘,所述引脚21的表面设置有引脚焊盘(图中未示出)。
接着,对所述承载盘21进行刻蚀在所述承载盘21的正面形成若干个凸起焊盘26。如图3b所示,所述承载盘21进行刻蚀之后,所述承载盘21的表面上形成了若干个凸起焊盘26,所述凸起焊盘26的表面仍与所述引脚25的表面即所述引脚焊盘的表面位于同一水平面,形成凸起焊盘26之后,所述承载盘21的厚度是不均匀的,形成有凸起焊盘26的位置比较厚,未形成凸起焊盘26的位置比较薄,所述凸起焊盘26的厚度范围一般在20μm到250μm之间。
然后,提供一芯片22。所述芯片22具有一有源面27。如图3c所示,所述有源面27上设置有若干个焊垫(图中未示出),所述焊垫的位置分别与所述凸起焊盘26和所述引脚焊盘的位置一一对应。
之后,在所述焊垫和凸起焊盘26之间和所述焊垫和引脚焊盘之间分别设置多个第一导电块23和多个第二导电块29,并分别利用第一导电块23和第二导电块29实现所述焊垫与所述凸起焊盘26和引脚焊盘的电连接。在此过程中,所述第一导电块23和第二导电块29是同时设置、同时连接的。
如图3d所示,多个第一导电块23设置于所述有源面27的焊垫和凸起焊盘26之间,所述第一导电块23的一端均与所述有源面27的一个焊垫电连接,所述第一导电块的另一端均与一个凸起焊盘电连接;多个第二导电块29设置于焊垫和引脚25之间,所述第二导电块29的一端与所述有源面27的一个焊垫电连接,所述第二导电块29的另一端与所述引脚25的引脚焊盘电连接。
其中,所述第一导电块23和第二导电块29的厚度均在45μm到60μm之间。所述第一导电块23和第二导电块29均可以采用任何导电材料,比如金、银、铜等导电金属。优选的,所述第一导电块23和第二导电块29均为金属铜。
请继续参考图3d,如图3d所示,由于凸起焊盘26之间具有空隙,塑封料24在所述芯片22与承载盘21之间的流动空间除了第一导电块23之间的空隙之外,还包括凸起焊盘26之间的空隙。所述流动空间的大小与凸起焊盘26的厚度和第一导电块23的厚度有关,凸起焊盘26和第一导电块23的厚度越厚,所述流动空间越大;反之,所述流动空间越小。
接着,提供塑封料24。本实施例中,所述塑封料24采用环氧树脂。
最后,执行塑封工艺,使所述塑封料24包围所述芯片22并填满所述芯片22与所述承载盘21之间的空间。如图3e所示,在所述芯片22的周围及所述芯片22与所述承载盘21之间注入塑封料24后包封成型,所述环氧树脂固化成型后包围整个芯片22并填满所述承载盘21和所述芯片22之间的空间。
至此,形成了所述芯片的封装结构20。所述芯片的封装结构20中,由于形成凸起焊盘26时承载盘21被刻蚀增加了芯片22与承载盘21之间的活动空间,从而增大了塑封料24在芯片22与承载盘21之间的流通通道,因此进行塑封工艺时塑封料24能够填满芯片22与承载盘21之间的空间。可见,底部填充工艺不再是芯片在封装过程中必须的工艺步骤,不进行底部填充工艺同样能够保证芯片的封装效果。
考虑到成本,一般直接采用环氧树脂对所述芯片22及所述承载盘21和所述芯片22之间的空间的进行塑封,塑封之前不再使用填充胶对所述承载盘21和所述芯片22之间的空间进行填充。
综上,在本发明实施例提供的芯片的封装结构及其制造方法中,在进行封装之前通过刻蚀在承载盘的正面形成与芯片的焊垫相对应的凸起焊盘,承载盘通过所述凸起焊盘与所述芯片的焊垫实现电连接的同时,由于承载盘的部分区域被刻蚀增大了塑封料在芯片与承载盘之间的流通通道,使得塑封料能够填满芯片与承载盘之间的空间,因此塑封工艺之前不必进行底部填充工艺,从而减少了芯片的封装工序,有效地降低了封装成本。
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (10)
1.一种芯片的封装结构,其特征在于,包括:承载盘、芯片、多个第一导电块和塑封料;
所述承载盘的正面设置有多个凸起焊盘;
所述芯片具有一有源面,所述第一导电块的一端与所述有源面电连接,所述第一导电块的另一端与所述凸起焊盘电连接;
所述塑封料包围所述芯片并填满所述承载盘和所述芯片之间的空间。
2.如权利要求1所述的芯片的封装结构,所述凸起焊盘的厚度范围在20μm到250μm之间。
3.如权利要求1所述的芯片的封装结构,其特征在于,所述塑封料为环氧树脂。
4.如权利要求1所述的芯片的封装结构,其特征在于,还包括:若干个引脚;
所述引脚设置于所述承载盘的边缘,所述引脚的表面设置有引脚焊盘,所述引脚焊盘的表面与所述凸起焊盘的表面位于同一水平面。
5.如权利要求4所述的芯片的封装结构,其特征在于,还包括:多个第二导电块;
所述第二导电块的一端与所述有源面电连接,所述第二导电块的另一端与所述引脚焊盘电连接。
6.如权利要求5所述的芯片的封装结构,其特征在于,所述第一导电块和第二导电块采用的材料均为金属铜,所述第一导电块和第二导电块的厚度均在45μm到60μm之间。
7.一种芯片的封装结构的制造方法,其特征在于,包括:
提供一承载盘;
刻蚀所述承载盘在所述承载盘的正面形成凸起焊盘;
提供一芯片,所述芯片具有一有源面;
提供多个第一导电块;
利用所述第一导电块实现所述有源面与所述凸起焊盘的电连接;
提供塑封料;
进行塑封工艺,使所述塑封料包围所述芯片并填满所述芯片与所述承载盘之间的空间。
8.如权利要求7所述的芯片的封装结构的制造方法,其特征在于,在提供一承载盘的同时,还包括:提供若干个引脚;
所述引脚位于所述承载盘的边缘,所述引脚的表面设置有引脚焊盘,所述引脚焊盘的表面与所述凸起焊盘的表面位于同一平面。
9.如权利要求8所述的芯片的封装结构的制造方法,其特征在于,在提供多个第一导电块的同时,还包括:提供多个第二导电块;
在利用所述第一导电块实现所述有源面与所述凸起焊盘的电连接的同时,还包括:利用所述第二导电块实现所述有源面与所述引脚焊盘的电连接。
10.如权利要求9所述的芯片的封装结构的制造方法,其特征在于,所述第一导电块和第二导电块采用的材料均为金属铜,所述第一导电块和第二导电块的厚度均在45μm到60μm之间。
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- 2014-10-21 TW TW103136320A patent/TW201528459A/zh unknown
- 2014-10-31 US US14/529,543 patent/US9123629B2/en active Active
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CN109545754A (zh) * | 2018-11-22 | 2019-03-29 | 京东方科技集团股份有限公司 | 一种芯片的封装结构、封装方法、显示装置 |
CN109545754B (zh) * | 2018-11-22 | 2021-01-26 | 京东方科技集团股份有限公司 | 一种芯片的封装结构、封装方法、显示装置 |
CN111725146A (zh) * | 2019-03-18 | 2020-09-29 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
CN111799241A (zh) * | 2020-06-24 | 2020-10-20 | 霸州市云谷电子科技有限公司 | 邦定结构及其制作方法和显示面板 |
Also Published As
Publication number | Publication date |
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TW201528459A (zh) | 2015-07-16 |
US9123629B2 (en) | 2015-09-01 |
US20150115439A1 (en) | 2015-04-30 |
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