CN103400819B - 一种引线框架及其制备方法和应用其的封装结构 - Google Patents
一种引线框架及其制备方法和应用其的封装结构 Download PDFInfo
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Abstract
本发明公开了一种引线框架,包括设置于底部,且具有导电性能的水平板和设置于水平板的表面,用于支撑并电连接于芯片,且具有导电性的多个凸块。本发明中的引线框架具有凸块,芯片依次叠置于凸块上方,凸块用于支撑芯片,且通过凸块与芯片之间的电连接,实现芯片与引线框架的电连接,避免了键合引线的连接方式,增强了封装结构的紧凑性,有效的缩减了芯片封装的厚度,进一步适应了电子元件小型化的市场需求。
Description
技术领域
本发明涉及集成电路封装技术领域,特别涉及一种引线框架,以及上述引线框架的制备方法,本发明还涉及一种应用上述引线框架的封装结构。
背景技术
集成电路塑封中使用的引线框架是集成电路封装的一种主要结构材料。它在电路中主要起承载IC芯片的作用,同时起连接芯片与外部线路板电信号的作用。
图1为现有技术中引线框架的剖面结构示意图,主要包括芯片托盘011与引脚012,其中,芯片托盘011与引脚012的上下表面都为平面结构,因此,现有技术中的引线框架的整体结构一般为薄片状结构。
现有技术中的引线框架应用到多芯片叠层封装体中时,具体的,应用在双芯片叠层封装体中时,其封装结构的剖面图如图2所示,在该封装结构中,第一芯片04和第二芯片05堆叠设置在引线框架的芯片托盘011上,第一芯片04的一表面通过粘合剂06连接至芯片托盘011的连接面上,第二芯片05的一表面通过粘合剂06连接至第一芯片04的另一表面。第二芯片05的宽度需要小于第一芯片04的宽度,以暴露出设置于第一芯片04边缘上的焊垫。
在这种薄片状结构的引线框架上进行的多芯片叠成封装,需要用到键合引线实现芯片上的焊垫与引线框架之间的连接。如图2所示,封装结构中是通过第一组键合引线02和第二组键合引线03分别将第一芯片04与第二芯片05的焊垫电性连接至引线框架的引脚012上。显然,第二组键合引线03的高度要高于第二芯片05。
因而,使得现有技术中引线框架的封装结构,其封装盒的厚度较大,从而不能满足随着电子元件的小型化,轻量化以及多功能化的需求的增加对半导体封装密度的要求。此外,在封装结构中使用键合引线由于自身存在的电感和/或者电阻的干扰,不利于提高芯片的高频性能。
综上所述,如何减小芯片封装结构的厚度,以满足电子元件小型化的市场需求,成为本领域技术人员亟待解决的技术问题。
发明内容
本发明的目的是提供一种引线框架,能够减小芯片封装结构的厚度,以满足电子元件小型化的市场需求,本发明的其他目的是提供上述引线框架的制备方法以及一种应用上述引线框架的封装结构。
为解决上述技术问题,本发明提供了如下技术方案:
一种制备引线框架的方法,包括以下步骤:
11)通过模具单独制备所述引线框架的水平板;
12)在所述水平板表面设置一掩膜板,所述掩膜板具有通槽;
13)在暴露于所述通槽位置的所述水平板上电镀导电材料;
14)所需凸块的结构形成后,去除所述掩膜板。
优选的,所述导电材料为铜。
一种制备引线框架的方法,包括以下步骤:
31)通过模具单独制造所述引线框架的水平板和凸块;
32)将所述凸块冲压于所述水平板的相应位置。
优选的,所述凸块可由多个不同材质的单元导电凸块堆叠形成。
一种制备引线框架的方法,包括以下步骤:
41)通过模具制备包含所述引线框架整体结构的毛坯,所述毛坯的底部尺寸与所述引线框架的水平板的底部尺寸一致,所述毛坯的厚度为所述水平板的厚度与最高的所述引线框架的凸块的高度之和;
42)在所述毛坯的厚度方向上的上下表面覆盖掩膜层;
43)刻蚀掉所述毛坯上表面的部分掩膜层,裸露出需被刻蚀掉的毛坯表面;
44)刻蚀被裸露的毛坯表面,去掉所有掩膜层,形成包含所述水平板和所述凸块的所述引线框架。
优选的,制备所述引线框架的毛坯材料为铜。
一种封装结构,包括:
应用上述制备引线框架的方法所制备的引线框架;
第一组焊块;
通过所述第一组焊块电连接于所述引线框架的水平板之上,且相互间隔叠置的至少一个第一组件;
第二组焊块;
叠置于所述第一组件之上,通过所述第二组焊块电连接于,位于所述第一组焊块外侧的所述引线框架的凸块上的至少一个第二组件。
优选的,上述封装结构中,所述第一组件为一芯片。
优选的,上述封装结构中,所述第二组件为一磁性元件。
优选的,上述封装结构中,还包括设置于所述第一组件和所述第二组件之间的粘合层。
优选的,上述封装结构中,所述第一组焊块和所述第二组焊块均为球体、矩形体或柱体。
优选的,上述封装结构中,所述第一组焊块和所述第二组焊块的材料为铜、锡或化镍镀金。
相对上述背景技术,本发明中的引线框架具有凸块,芯片依次叠置于凸块上方,凸块用于支撑芯片,且通过凸块与芯片之间的电连接,实现芯片与引线框架的电连接,避免了键合引线的连接方式,增强了封装结构的紧凑性,有效的缩减了芯片封装的厚度,进一步适应了电子元件小型化的市场需求。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中引线框架的剖面结构示意图;
图2为现有技术中引线框架的封装结构剖面图;
图3为本发明所提供的引线框架的结构示意图;
图4为采用电镀法制备本发明中的引线框架的流程图;
图5为采用冲压法制备本发明中的引线框架的流程图;
图6为采用刻蚀法制备本发明中的引线框架的流程图;
图7为应用本发明提供的引线框架的多组件的芯片封装结构示意图。
具体实施方式
本发明的核心是提供一种引线框架,能够减小芯片封装结构的厚度,以满足电子元件小型化的市场需求,本发明的其他核心内容是提供上述引线框架的制备方法以及一种应用上述引线框架的封装结构。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
请结合图3,图3为本发明所提供的引线框架的结构示意图。
本发明所提供的一种引线框架,包括水平板1和多个凸块2。
其中,水平板1和凸块2均由导电材料制成,水平板1位于整个引线框架结构的底部,凸块2设置于水平板1上表面,凸块2用于支撑芯片,并实现芯片与引线框架之间的电连接,凸块2连接于芯片的电气面。
引线框架的一具体结构中,处于与芯片连接的状态时,水平板1水平放置,多个凸块2垂直于水平板1设置在其上表面,凸块2用于与芯片实现电连接,其中,水平板1和凸块2的制造材料,可以为同一种导电材料,也可以为不同的导电材料,设置在水平板1上的凸块2的数量和具体尺寸由具体的封装结构决定,且凸块2可以为一整体的导电材料,也可为多种导电材料堆叠或者合金形成。
本发明实施例所提供的引线框架具有凸块2,用于支撑芯片,芯片依次叠置于凸块2上方,通过凸块2与芯片之间的电连接,实现芯片与引线框架的电连接,避免了现有技术中采用键合引线的连接方式给芯片带来的负面影响,不仅具有很好的机械稳定性,同时也具有很好的电气稳定性,同时,有利于增强封装结构的紧凑性,有效的缩减了芯片封装的厚度,进一步适应了电子元件小型化的市场需求。
针对上述引线框架的具体结构,本发明还提供了三种制备上述结构的引线框架的方法,分别为电镀法、冲压法和刻蚀法。
请结合图4,图4为采用电镀法制备本发明中的引线框架的流程图。
采用电镀法制备上述引线框架,具体包括以下步骤:
步骤S11,制备水平板1:
根据实际需求选用相应导电材料作为水平板1的板材,通过特定的模具加工水平板1。
步骤S12,在水平板1表面设置一掩膜板:
具体的,掩膜板具有通槽,通槽位置可暴露出水平板1的表面。
步骤S13,在暴露于通槽位置的水平板1表面电镀导电材料:
电镀一段时间,在水平板1表面形成凸块2,具体的,电镀过程中用于形成凸块2的导电材料可以为铜。
步骤S14,凸块2形成,去除掩膜板:
所需凸块2的结构形成后,去除掩膜板。
请结合图5,图5为采用冲压法制备本发明中的引线框架的流程图。
采用冲压法制备上述引线框架,包括以下步骤:
步骤S31,通过模具制造水平板1和凸块2:
采用特定的模具分别单独形成水平板1和凸块2。
步骤S32,将凸块2冲压于水平板1相应位置:
具体的,采用冲压工艺将所需的一个个独立的凸块2连接到水平板1的表面,形成具有凸块2的引线框架,且引线框架上的凸块2还可以由多个单元导电凸块堆叠形成,多个单元导电凸块可以为不同的导电材料。
请结合图6,图6为采用刻蚀法制备本发明中的引线框架的流程图。
采用刻蚀法制备上述引线框架的方法,包括以下步骤:
步骤S41,制备引线框架的毛坯:
通过模具制备包含引线框架整体结构的毛坯,毛坯的底部尺寸与水平板1的底部尺寸一致,毛坯的厚度为水平板1的厚度与最高的凸块2的高度之和,优选的毛坯的材料为铜;
步骤S42,在毛坯上覆盖掩膜层:
在毛坯的厚度方向上的上下表面覆盖掩膜层;
步骤S43,刻蚀掩膜层:
刻蚀掉毛坯上表面的部分掩膜层,裸露出需被刻蚀掉的毛坯表面;
步骤S44,刻蚀被裸露的毛坯,形成引线框架:
刻蚀被裸露的毛坯表面,去掉所有掩膜层,形成包含水平板1和凸块2的引线框架。
上述三种引线框架的制备方法采用常规工艺,利用现有技术和现有设备制作形成,无需额外添加设备,与现有微电子工艺具有较好的兼容性。
如图7所示,图7为应用本发明提供的引线框架的多组件的芯片封装结构示意图。
本发明实施例还提供了一种应用上述引线框架的多组件的芯片封装结构,包括位于底层的引线框架,位于引线框架之上的芯片4(第一组件),以及层叠在芯片4之上的磁性元件5(第二组件),磁性元件5具体可为电感。
其中,芯片4通过第一组焊块31电连接至引线框架的水平板1上,电感通过第二组焊块32电连接于所述引线框架的凸块2上,其中凸块2设置在第一组焊块31的外侧,与芯片4相隔离,整体结构紧凑,机械稳定性强。
其中,第一组焊块31和第二组焊块32均为球体、矩形体或柱体,第一组焊块31和第二组焊块32的材料为铜、锡或化镍镀金。
在该实施例中,多组件的芯片封装结构还包括位于芯片4和电感之间的粘合层405,来更好的固定引线框架、芯片4和电感之间的相对位置,以及使整个多组件的芯片封装结构的牢固性更强。不同组件上的电极性通过第一组焊块31或第二组焊块32连接至引线框架的水平板1或者凸块2上,从而使引线框架具有相应的电极性,用于与外部电路相连。
采用图7所示的多组件的芯片封装结构,所有组件都采用倒装形式的连接方式,引线框架通过凸块2实现与上层组件的电性连接,因此,多组件的芯片封装结构的厚度大大减小,避免了键合引线的连接方式,给芯片性能带来的负面影响,不仅具有很好的机械稳定性,同时也具有很好的电气稳定性。
另外,对磁性元件而言,采用层叠式的封装结构,将电感和芯片封装于一单一的封装结构中,可以容纳更大体积,电感值更大的电感,更有利于***的高集成化和小体积化。
以上对本发明所提供的一种引线框架及其制备方法和应用其的封装结构进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以对本发明进行若干改进和修饰,这些改进和修饰也落入本发明权利要求的保护范围内。
Claims (5)
1.一种制备引线框架的方法,包括以下步骤:
11)通过模具单独制备所述引线框架的水平板(1);
12)在所述水平板(1)表面设置一掩膜板,所述掩膜板具有通槽;
13)在暴露于所述通槽位置的所述水平板(1)上电镀导电材料,形成凸块(2),所述凸块(2)用于支撑并电连接于芯片;
14)所述凸块(2)的结构形成后,去除所述掩膜板。
2.如权利要求1所述的制备引线框架的方法,其特征在于,所述导电材料为铜。
3.一种制备引线框架的方法,包括以下步骤:
31)通过模具单独制造所述引线框架的水平板(1)和凸块(2),所述凸块(2)可由多个不同材质的单元导电凸块堆叠形成,所述凸块(2)用于支撑并电连接于芯片;
32)将所述凸块(2)冲压于所述水平板(1)的相应位置。
4.一种制备引线框架的方法,包括以下步骤:
41)通过模具制备包含所述引线框架整体结构的毛坯,所述毛坯的底部尺寸与所述引线框架的水平板(1)的底部尺寸一致,所述毛坯的厚度为所述水平板(1)的厚度与最高的所述引线框架的凸块(2)的高度之和,所述凸块(2)用于支撑并电连接于芯片;
42)在所述毛坯的厚度方向上的上下表面覆盖掩膜层;
43)刻蚀掉所述毛坯上表面的部分掩膜层,裸露出需被刻蚀掉的毛坯表面;
44)刻蚀被裸露的毛坯表面,去掉所有掩膜层,形成包含所述水平板(1)和所述凸块(2)的所述引线框架。
5.如权利要求4所述的制备引线框架的方法,其特征在于,制备所述引线框架的毛坯材料为铜。
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10840005B2 (en) | 2013-01-25 | 2020-11-17 | Vishay Dale Electronics, Llc | Low profile high current composite transformer |
CN103531560A (zh) | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | 芯片的封装结构及其制造方法 |
CN103700639B (zh) | 2013-12-31 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | 封装组件及其制造方法 |
CN103730444B (zh) | 2014-01-20 | 2017-06-27 | 矽力杰半导体技术(杭州)有限公司 | 封装组件及其制造方法 |
CN104269385B (zh) * | 2014-10-21 | 2017-12-19 | 矽力杰半导体技术(杭州)有限公司 | 封装组件及其制造方法 |
US10099574B2 (en) * | 2015-04-15 | 2018-10-16 | Ford Global Technologies, Llc | Vehicle power module assemblies |
TWI566356B (zh) | 2015-10-15 | 2017-01-11 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
US10998124B2 (en) | 2016-05-06 | 2021-05-04 | Vishay Dale Electronics, Llc | Nested flat wound coils forming windings for transformers and inductors |
JP7160438B2 (ja) | 2016-08-31 | 2022-10-25 | ヴィシェイ デール エレクトロニクス エルエルシー | 低い直流抵抗を有す高電流コイルを備えた誘導子 |
CN107393836B (zh) | 2017-06-19 | 2020-04-10 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装方法及封装结构 |
CN108807299B (zh) * | 2017-08-14 | 2024-05-17 | 苏州能讯高能半导体有限公司 | 引线框架结构、引线框架和封装器件 |
CN107808868B (zh) | 2017-10-13 | 2020-03-10 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装结构及其制造方法 |
US10714412B2 (en) * | 2017-11-22 | 2020-07-14 | Texas Instruments Incorporated | Semiconductor package with integrated passive electrical component |
CN109712948A (zh) * | 2019-01-24 | 2019-05-03 | 广东气派科技有限公司 | 一种集成被动元件的芯片封装结构 |
CN110323141B (zh) | 2019-04-15 | 2021-10-12 | 矽力杰半导体技术(杭州)有限公司 | 引线框架结构,芯片封装结构及其制造方法 |
US11538739B2 (en) | 2020-04-21 | 2022-12-27 | Toyota Motor Engineering & Manufacturing North America, Inc. | Compact low inductance chip-on-chip power card |
US11948724B2 (en) | 2021-06-18 | 2024-04-02 | Vishay Dale Electronics, Llc | Method for making a multi-thickness electro-magnetic device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569099A (zh) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | 一种倒装芯片的封装方法 |
CN103000608A (zh) * | 2012-12-11 | 2013-03-27 | 矽力杰半导体技术(杭州)有限公司 | 一种多组件的芯片封装结构 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1255866C (zh) | 2002-11-04 | 2006-05-10 | 矽统科技股份有限公司 | 倒装芯片封装工艺及其装置 |
US7148086B2 (en) * | 2005-04-28 | 2006-12-12 | Stats Chippac Ltd. | Semiconductor package with controlled solder bump wetting and fabrication method therefor |
US20070130759A1 (en) | 2005-06-15 | 2007-06-14 | Gem Services, Inc. | Semiconductor device package leadframe formed from multiple metal layers |
KR101194842B1 (ko) * | 2007-09-06 | 2012-10-25 | 삼성전자주식회사 | 반도체 패키지가 삽입된 인쇄회로기판 |
US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
CN101814480B (zh) | 2010-04-16 | 2011-08-31 | 杭州矽力杰半导体技术有限公司 | 一种芯片封装结构及其封装方法 |
US8283758B2 (en) | 2010-12-16 | 2012-10-09 | Monolithic Power Systems, Inc. | Microelectronic packages with enhanced heat dissipation and methods of manufacturing |
US8361899B2 (en) * | 2010-12-16 | 2013-01-29 | Monolithic Power Systems, Inc. | Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing |
US20120273935A1 (en) * | 2011-04-29 | 2012-11-01 | Stefan Martens | Semiconductor Device and Method of Making a Semiconductor Device |
US8749056B2 (en) * | 2011-05-26 | 2014-06-10 | Infineon Technologies Ag | Module and method of manufacturing a module |
CN102394232A (zh) | 2011-11-29 | 2012-03-28 | 杭州矽力杰半导体技术有限公司 | 一种引线框架及应用其的芯片倒装封装装置 |
CN102376671A (zh) | 2011-11-29 | 2012-03-14 | 杭州矽力杰半导体技术有限公司 | 引线框架以及应用其的倒装芯片式半导体封装结构 |
US8629539B2 (en) * | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
CN102983083B (zh) * | 2012-12-24 | 2015-11-18 | 厦门永红科技有限公司 | 引线框架及其生产方法 |
US9805956B2 (en) * | 2013-01-23 | 2017-10-31 | Asm Technology Singapore Pte Ltd | Lead frame and a method of fabrication thereof |
-
2013
- 2013-08-14 CN CN201310353446.8A patent/CN103400819B/zh active Active
-
2014
- 2014-04-10 TW TW103113217A patent/TWI552296B/zh active
- 2014-08-14 US US14/459,515 patent/US9373567B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569099A (zh) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | 一种倒装芯片的封装方法 |
CN103000608A (zh) * | 2012-12-11 | 2013-03-27 | 矽力杰半导体技术(杭州)有限公司 | 一种多组件的芯片封装结构 |
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