TWI223879B - Package stack module with vertical conductive wires inside molding compound - Google Patents
Package stack module with vertical conductive wires inside molding compound Download PDFInfo
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- TWI223879B TWI223879B TW092127883A TW92127883A TWI223879B TW I223879 B TWI223879 B TW I223879B TW 092127883 A TW092127883 A TW 092127883A TW 92127883 A TW92127883 A TW 92127883A TW I223879 B TWI223879 B TW I223879B
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- Prior art keywords
- package
- item
- sealant
- scope
- semiconductor
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Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 51
- 238000000465 moulding Methods 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 120
- 238000007789 sealing Methods 0.000 claims description 68
- 239000000565 sealant Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 23
- 239000008393 encapsulating agent Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000084 colloidal system Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 description 25
- 125000006850 spacer group Chemical group 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 5
- QFLWZFQWSBQYPS-AWRAUJHKSA-N (3S)-3-[[(2S)-2-[[(2S)-2-[5-[(3aS,6aR)-2-oxo-1,3,3a,4,6,6a-hexahydrothieno[3,4-d]imidazol-4-yl]pentanoylamino]-3-methylbutanoyl]amino]-3-(4-hydroxyphenyl)propanoyl]amino]-4-[1-bis(4-chlorophenoxy)phosphorylbutylamino]-4-oxobutanoic acid Chemical compound CCCC(NC(=O)[C@H](CC(O)=O)NC(=O)[C@H](Cc1ccc(O)cc1)NC(=O)[C@@H](NC(=O)CCCCC1SC[C@@H]2NC(=O)N[C@H]12)C(C)C)P(=O)(Oc1ccc(Cl)cc1)Oc1ccc(Cl)cc1 QFLWZFQWSBQYPS-AWRAUJHKSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- GHYOCDFICYLMRF-UTIIJYGPSA-N (2S,3R)-N-[(2S)-3-(cyclopenten-1-yl)-1-[(2R)-2-methyloxiran-2-yl]-1-oxopropan-2-yl]-3-hydroxy-3-(4-methoxyphenyl)-2-[[(2S)-2-[(2-morpholin-4-ylacetyl)amino]propanoyl]amino]propanamide Chemical compound C1(=CCCC1)C[C@@H](C(=O)[C@@]1(OC1)C)NC([C@H]([C@@H](C1=CC=C(C=C1)OC)O)NC([C@H](C)NC(CN1CCOCC1)=O)=O)=O GHYOCDFICYLMRF-UTIIJYGPSA-N 0.000 description 1
- VIJSPAIQWVPKQZ-BLECARSGSA-N (2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-acetamido-5-(diaminomethylideneamino)pentanoyl]amino]-4-methylpentanoyl]amino]-4,4-dimethylpentanoyl]amino]-4-methylpentanoyl]amino]propanoyl]amino]-5-(diaminomethylideneamino)pentanoic acid Chemical compound NC(=N)NCCC[C@@H](C(O)=O)NC(=O)[C@H](C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](CC(C)(C)C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](CCCNC(N)=N)NC(C)=O VIJSPAIQWVPKQZ-BLECARSGSA-N 0.000 description 1
- LFOIDLOIBZFWDO-UHFFFAOYSA-N 2-methoxy-6-[6-methoxy-4-[(3-phenylmethoxyphenyl)methoxy]-1-benzofuran-2-yl]imidazo[2,1-b][1,3,4]thiadiazole Chemical compound N1=C2SC(OC)=NN2C=C1C(OC1=CC(OC)=C2)=CC1=C2OCC(C=1)=CC=CC=1OCC1=CC=CC=C1 LFOIDLOIBZFWDO-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 229940125797 compound 12 Drugs 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010411 cooking Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
1223879 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種半導體封裝件之組合模組，特別 糸有關於一種封裝件堆疊模組〔Mul ti—1223879 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a combination module of a semiconductor package, and particularly to a package stacking module [Mul ti—
Module〕。 【先前技術】 ^于裝件堆疊模組〔Multi- Package Module〕係為 二，複數個半導體封裝件垂直向堆疊，其係將該些半導體 * 口件之封膠體〔molding c〇mp〇und〕相互疊設，不同於 在單一封膠體内之多晶片堆疊封裝件〔Multi chip stack ，在我國專利公告第52701 8號係揭示一種封裝 ^ 其係將該些半導體封裝件之外連接端（如導 卷m r道錫鉛銲球〕設在對應封膠體之外周邊或側 ΐ良方ί疊之半導趙封裝η然其係具 縮小化，該些外連接“ί易:體封裝件之尺寸 脫掉。 银％不谷易達到準確地對位接合且容易 另種S知之封I件堆疊模組係、以間隔電路板 〔wiring spacer )作Λ摊矗糾牯从 係設在封膠體之周邊Λ;隹參叠:第=之電性連接界面’其 堆叠模組係主要包ί有;’；種習知之封裝件 與一第-丰導沪射：L互堆疊之—第-半導體封裝件10 與第一 +導體封裝件20，其中該第 堆疊設置於該第-半導體封請〇上，該第一 件㈣包含有一密封有半導體晶片〔圖未：出 11與-基板12 ’該封膠體"係設在該基板12之上表面且 1223879Module]. [Previous technology] ^ The multi-package module is two, and a plurality of semiconductor packages are stacked vertically, which is a molding compound [molding c〇mp〇und] Stacking each other is different from a multi-chip stack package in a single colloid (Multi chip stack, disclosed in Chinese Patent Bulletin No. 52701 8) a package ^ which is a connection terminal (such as the The volume of mr lead tin-lead solder balls] is provided on the periphery or side of the corresponding sealing gel. The semi-conducting Zhao package is reduced in size. These external connections are "easy: the size of the body package It is easy to achieve accurate registration and bonding, and it is easy to realize another type of sealed I-stacked module system. The wiring spacer (wiring spacer) is used as the Λ booth, and the correction is set at the periphery of the sealing gel. Λ隹 Refer to the stack: the electrical connection interface of the first = 'the stack module is mainly included;'; a conventional package and a first-Fengdaohushe: L mutually stacked-the first-semiconductor package 10 And the first + conductor package 20, wherein the first stack is disposed on the -half The conductor is sealed, and the first piece contains a sealed semiconductor wafer [not shown: 11 and-substrate 12 'The sealing compound " is located on the upper surface of the substrate 12 and 1223879
”亥封膠體11内之半導體晶片係可以覆晶接合或打線連接而 電性連接至該基板1 2〔圖未繪出〕，習知該基板丨2之下表 面另包含有複數個銲球13，其係呈球格陣列型態，為了電 ^生連接该第二半導體封裝件2 〇至該第一半導體封裝件丨〇之 基板12，請參閱第圖，該基板12會設計成具較大電性 連接面之基板，以配合對應一間隔電路板3〇〔 spacer〕，該間隔電路板3〇係具有雙面電性導通之金屬線 路31以及一位於該間隔電路板3〇中央之開口32，其中該些 線路31係電性連接在該間隔電路板3〇上表面之複數個連& 墊3 4與在该間隔電路板3 〇下表面之複數個凸塊3 3，該些連 接墊34係提供作為該第二半導體封裝件2〇之複數個凸塊21 接合，該些凸塊33係用以電性接合至該基板12之上表面， 故該間隔電路板30係作為該基板1 2之增高電性連接之間隔 物，使得該第二半導體封裝件2〇能垂直向堆疊衿該第一半 導體封裝件1〇，由於該間隔電路板3〇之開口32必須要大於 該封膠體11之尺寸，使得該第一半導體封裝件1〇之基板12 亦須相匹配而增大尺寸，再者，該間隔電路板3〇具有該開 口 32，因此容易造成该間隔電路板3〇翹曲，當該第二半導 體封裝件20以該些凸塊21電性連接該間隔電路板3〇及該間 隔電路板30以該呰凸塊33電性連接該基板12時，因該間隔 電路板30翹曲而造成該些凸塊21、33之接點斷裂而電性連 接不良、斷路，因此該間隔電路板30之厚度與翹曲度係被 嚴格要求在一準確的範圍，該間隔電路板3〇之翹曲導致該"The semiconductor wafer in the Haifeng colloid 11 can be flip-chip bonded or wire-connected to be electrically connected to the substrate 12 (not shown). It is known that the lower surface of the substrate 2 further includes a plurality of solder balls 13 It is in the form of a ball grid array. In order to electrically connect the substrate 12 of the second semiconductor package 20 to the first semiconductor package, please refer to the figure. The substrate 12 will be designed to have a larger size. The substrate on the electrical connection surface is matched with a spacer circuit board 30. The spacer circuit board 30 has a double-sided electrically conductive metal circuit 31 and an opening 32 in the center of the spacer circuit board 30. Wherein, the lines 31 are a plurality of connections electrically connected to the upper surface of the spacer circuit board 30 and a plurality of pads 3 4 and a plurality of bumps 3 3 on the lower surface of the spacer circuit board 30. The connection pads 34 is provided as a plurality of bumps 21 for bonding as the second semiconductor package 20, and the bumps 33 are used for electrical bonding to the upper surface of the substrate 12, so the spacer circuit board 30 is used as the substrate 1 A spacer that increases the electrical connection of 2 so that the second semiconductor The package 20 can be stacked vertically to the first semiconductor package 10. Since the opening 32 of the spacer circuit board 30 must be larger than the size of the sealing compound 11, the substrate 12 of the first semiconductor package 10 It must also be matched to increase the size. Furthermore, the spacer circuit board 30 has the opening 32, so it is easy to cause the spacer circuit board 30 to warp. When the second semiconductor package 20 is electrically connected to the bumps 21, When the spacer circuit board 30 and the spacer circuit board 30 are electrically connected to the substrate 12 with the bump bump 33, the contacts of the bumps 21 and 33 are broken due to the warpage of the spacer circuit board 30. Poor electrical connection and open circuit. Therefore, the thickness and warpage of the spacer circuit board 30 are strictly required to be in an accurate range. The warpage of the spacer circuit board 30 causes the
些凸塊2 1、3 3之接點斷裂已成為要消除該習知封裝件堆疊The breakage of the contacts of these bumps 2 1, 3 3 has become to eliminate the conventional package stacking
第10頁Page 10
12238791223879
五、發明說明（3) 模組之不良率首要解決的問題。 【發明内容】 本發明之主要目的係在於提供一種在封膠體内养有縱 向導通線之封裝件堆疊模組，其係利用在一半導體封裝件 之封膠體内設有複數個縱向導通線，該些縱向導通線之— 端係接合在该封膠體底面之連接墊’另一端係顯露於該封 膠體頂面，並且在該封膠體頂面貼設一異方性導電膜層， 以利在該封膠體上堆疊另一半導體封裝件，並且藉由該異 方性導電膜層與該些縱向導通線電性導通該相鄰堆昼之半 導體封裝件，取代習知在封膠體外周邊之間隔電路板。 本發明之次一目的係在於提供一種在封膠體内具有縱 向導通線之半導體封裝件，利用在一封膠體内設有複數個 縱向導通線，該些縱向導通線之一端係接合在封膠體底面 之連接墊，另一端係顯露於封膠體頂面，使得該半導體封 裝件之封膠體可供電性連接之垂直堆疊，並且具有在封膠 體内縱向導通路徑之穩固形成，以取代習知在封膠體外周 邊之間隔電路板。 依本發明之在封膠體内具有縱向導通線之封裝件堆疊 模組’其主要包含有一第一半導體封裝件、一第二半‘體 封裝件及在該些半導體封裝件之間之異方性導電膜層 〔Anisotropic Conductive Film， ACF〕，其中該第一半 導體封裝件係包含有一封膠體、複數個連接墊、一半導體 晶片以及複數個縱向導通線，該封膠體係具有一頂面及一 底面，該些連接墊係形成於該封膠體之底面，該半導體晶V. Description of the Invention (3) The first problem to be solved by the defective rate of the module. [Summary of the Invention] The main object of the present invention is to provide a package stacking module having longitudinal conducting lines in a sealing compound, which utilizes a plurality of longitudinal conducting lines provided in a sealing compound of a semiconductor package. The other end of the vertical conductive lines—the end of the connection pad that is connected to the bottom surface of the encapsulant—is exposed on the top surface of the encapsulant, and an anisotropic conductive film layer is pasted on the top surface of the encapsulant to facilitate Another semiconductor package is stacked on the sealing compound, and the anisotropic conductive film layer and the vertical conduction lines are used to electrically connect the adjacent semiconductor packages in the daytime to replace the conventional spacer circuit outside the sealing compound. board. A second object of the present invention is to provide a semiconductor package having a vertical conductive line in a sealing compound. A plurality of vertical conductive lines are provided in a gel, and one end of the vertical conductive lines is bonded to the bottom surface of the sealing compound. The other end of the connection pad is exposed on the top surface of the sealing compound, so that the sealing compound of the semiconductor package can be vertically stacked for power supply connection, and has a stable formation of a vertical conduction path in the sealing compound to replace the conventional sealing compound. Spacer circuit board on the outer periphery. According to the present invention, a package stacking module having longitudinal conductive lines in a sealing compound mainly includes a first semiconductor package, a second half-body package, and anisotropy between the semiconductor packages. Anisotropic Conductive Film (ACF), wherein the first semiconductor package includes a gel, a plurality of connection pads, a semiconductor wafer, and a plurality of vertical conductive lines. The sealant system has a top surface and a bottom surface. The connection pads are formed on the bottom surface of the sealing compound, and the semiconductor crystal
1223879 五、發明說明（4) ' 片係電性連接至該些連接墊並以該封膠體密封該半導體晶 片’該些縱向導通線係設於該封膠體内，該些縱向導通線 之一端接合於該些連接墊，另一端係顯露於該封膠體之頂 面’以電性導通該封膠體之該頂面與該底面，並且該異方 性導電膜層係貼設於該封膠體之頂面，以供第二半導體封 裝件之堆疊與電性導通。 【實施方式】1223879 V. Description of the invention (4) 'The chip system is electrically connected to the connection pads and the semiconductor wafer is sealed with the sealing compound' The longitudinal conductive lines are provided in the sealing compound, and one end of the vertical conductive lines is bonded At the connection pads, the other end is exposed on the top surface of the sealing gel to electrically connect the top surface and the bottom surface of the sealing gel, and the anisotropic conductive film layer is attached to the top of the sealing gel. Surface for stacking and electrical conduction of the second semiconductor package. [Embodiment]
參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之第一具體實施例，請參閱第3圖，一種封 展件堆疊模組係主要包含有一第一半導體封裝件丨〇〇、一 第一半導體封裝件200以及在第一半導體封裝件iQ〇與第二 半導體封裝件200之間的異方性導電膜層300 〔Anisotropic Conductive Film，ACF〕，在本實施例中 该第二半導體封裝件2 〇 〇係堆疊在該第一半導體封裝件1 〇 〇 上〇 該第一半導體封裝件1 0 0係包含有一封膠體1 ^ 〇 〔molding compound〕、複數個連接墊1 20、一半導體晶 片1 3 0以及複數個縱向導通線1 4 0，其中該封膠體11 〇係可 為壓模〔mo 1 di ng〕形成之電絕緣性固化樹脂，用以密 封、保遵與結合該半導體晶片1 3 0，該封膠體11 〇係具有一 頂面111及一對應之底面11 2，在該封膠體11 〇之底面11 2係 形成有該些連接墊1 2 〇，該些連接墊1 2 0係可呈塊狀、平墊 狀、凸點狀或導腳狀，其係可由一BCC〔 Bump Chip Carrier，凸點晶片載板〕金屬板或是由一qFn〔 QuadWith reference to the drawings, the present invention will be illustrated by the following embodiments. According to a first specific embodiment of the present invention, please refer to FIG. 3. A package stacking module system mainly includes a first semiconductor package, a first semiconductor package 200, and a first semiconductor package. Anisotropic conductive film layer 300 (Anisotropic Conductive Film, ACF) between iQ〇 and second semiconductor package 200. In this embodiment, the second semiconductor package 200 is stacked on the first semiconductor package. The first semiconductor package 100 is composed of a colloidal compound 1, a plurality of connection pads 120, a semiconductor wafer 130, and a plurality of vertical conductive lines 140. The sealing compound 110 can be an electrically insulating curing resin formed by a stamper [mo 1 di ng], which is used to seal, guarantee compliance and bond the semiconductor wafer 130. The sealing compound 110 has a top surface. 111 and a corresponding bottom surface 11 2, the connection pads 12 2 are formed on the bottom surface 11 2 of the sealant 11 〇, and the connection pads 1 2 0 can be block-shaped, flat-cushion-shaped, or bump-shaped. Or guide-pin-shaped, which can be changed by a BCC [Bump Chi p Carrier, bump chip carrier board] metal plate or a qFn [Quad
第12頁 1223879 發明說明（5)Page 12 1223879 Description of the invention (5)
Flat Non-leaded，四方扁平無接腳〕、s〇N〔SmaUFlat Non-leaded], s〇N [SmaU
Outline Non-leaded,小外型無接腳〕等無外接腳式導線 架之金屬板所構成，由於BCC、QFN、s〇N已為習知之封裝 型態，因此以金屬板或導線架形成本實施例之該些連接墊 1 2 0不在此贅述。Outline Non-leaded, small lead-free] and other metal plates without external lead type lead frames. Since BCC, QFN, and SON are already known packaging types, the cost is formed by metal plates or lead frames. The connection pads 120 in the embodiment are not described in detail here.
該半導體晶片1 3 0係被密封於該封膠體丨丨〇内，其係具 有一主動面131及一對應之背面132，其中該主動面131係 形成有複數個銲墊133，在本實施例中，該半導體晶片13〇 之煮面132係為顯露於该封膠體11〇，一種具體形成顯露該 半導體晶片130之背面132方式，係在製程中可利用一貼片 〔tape〕貼附在該半導體晶片13〇之背面132，在壓模形成 該封膠體110之後撕離該貼片，另一種具體形成方式為， 係以一金屬板承載該半導體晶片丨3 〇之背面丨32 ,在電性連 接與形成該封膠體11 0之後，以蝕刻除去該金屬板。在本 實施例中’該半導體晶片1 3 〇係利用打線形成之鋅線1 5 〇電 性連接該些銲墊133與對應連接墊120。 该些縱向導通線 140〔vertical conductive wire〕The semiconductor wafer 130 is sealed in the sealing compound. It has an active surface 131 and a corresponding back surface 132. The active surface 131 is formed with a plurality of bonding pads 133. In this embodiment, In the process, the cooking surface 132 of the semiconductor wafer 13 is exposed to the sealing compound 11, a specific method for forming the back surface 132 of the semiconductor wafer 130 is exposed, and a tape (tape) can be attached to the surface during the manufacturing process. The back surface 132 of the semiconductor wafer 13 is detached from the patch after the sealant 110 is formed by compression molding. Another specific formation method is to carry a back surface 32 of the semiconductor wafer 32 with a metal plate. After connecting and forming the sealing compound 110, the metal plate is removed by etching. In this embodiment, the semiconductor wafer 13 is electrically connected to the bonding pads 133 and the corresponding connection pads 120 by using zinc wires 15 formed by wire bonding. The vertical conductive wires 140 (vertical conductive wires)
係設於該封膠體140内，每一縱向導通線140係具有一第一 端141及一第二端142，該些縱向導通線140之第一端141係 接合於該些連接墊120，該些縱向導通線140之第二端142 係顯露於該封膠體11 〇之頂面111，以電性導通該封膠體 110之該頂面111與該底面112，該些縱向導通線14〇係選自 於金線、鋁線、銅線與電鍍孔，在本實施例中，該些縱向 導通線140係為打線形成之金線，並且與在對應連接墊12〇Each of the vertical conductive lines 140 has a first end 141 and a second end 142. The first ends 141 of the vertical conductive lines 140 are connected to the connection pads 120. The second ends 142 of the vertical conductive lines 140 are exposed on the top surface 111 of the sealing compound 110 to electrically connect the top surface 111 and the bottom surface 112 of the sealing compound 110. The vertical conductive lines 14 are selected. Since the gold wire, the aluminum wire, the copper wire, and the plated hole, in this embodiment, the vertical conducting wires 140 are gold wires formed by wire bonding, and are connected to the corresponding connection pad 12.
第13頁 1223879 五、發明說明（6) 上連接之銲線150為一體形成。 ”亥異方性導電膜層 3〇〇〔Anis〇tropic Conductive F/ ACF〕係貼設於該封膠體110之頂面111，其包含有 適當密度分佈之細粒度導電粒子及熱固性膠，以作為在該 封膠體11 0之頂面11 1上垂直向電性導通結構，而達到電性 連接該第一半導體封裝件1〇〇之縱向導通線14〇與該第二半 導體封裝件200之對外電性連接端21()。 該第二半導體封裝件200係可為一種微小尺寸之半導 體封裝件，如晶片尺寸封裝件〔Chip Scale package， CSP〕、四方扁平無接腳封裝件〔Quad Flat N〇n-leade(1 package〕或覆晶封裝件〔flip —chip package〕，在本實 施例中/ ’该第二半導體封裝件2〇〇係與該第一半導體封裝 件1 00係為。不相同電性功能之封裝件，例如為微處理器、 ^形處理器或為記憶體，該第二半導體封裝件2〇〇係包含 此Ϊ ^個對外電性連接端2 1 〇 ’在本實施例中，較佳地該 二夕電性連接端2 1 〇係可為凸塊或銲球，該第二半導體 =裝件2 00係疊設於該第一半導體封裝件1〇〇上，該些對外 連接端210係接合於該異方性導電膜層3〇〇，並藉由該 健，導電膜層300電性連接至該些縱向導通線14〇，當該 #笛二f體封裝件1 〇 〇與該第二半導體封裝件2 0 0堆疊時， = 導體封裝件2〇〇係經由在該封膠體頂面"I之 雷地性*導電膜層3〇〇與該封膠體110内該些縱向導通線 140電性連接至第—车道_ hi +導體封裝件100之半導體晶片130， 運到多封裝件之垂直堆疊。Page 13 1223879 V. Description of the invention (6) The welding wire 150 connected to the body is integrally formed. Anisotropic conductive film layer 300 (Anisotropic Conductive F / ACF) is attached to the top surface 111 of the sealing colloid 110, and contains fine-grained conductive particles and thermosetting glue with appropriate density distribution as the A vertical electrical conduction structure is vertically formed on the top surface 11 1 of the sealing compound 110 to achieve electrical connection between the vertical conduction line 14 of the first semiconductor package 100 and the second semiconductor package 200. 21 (). The second semiconductor package 200 may be a micro-sized semiconductor package, such as a chip scale package (CSP), a quad flat no-pin package [Quad Flat No. n-leade (1 package) or flip-chip package, in this embodiment / 'The second semiconductor package 200 is the same as the first semiconductor package 100. Not the same The electrical function package is, for example, a microprocessor, a processor, or a memory. The second semiconductor package 200 includes the external electrical connection terminals 2 1 0 ′ in this embodiment. Medium, preferably the second night electrical connection terminal 2 The 10 series can be bumps or solder balls. The second semiconductor = mounting device 200 is stacked on the first semiconductor package 100. The external connection terminals 210 are bonded to the anisotropic conductive film. Layer 300, and through this key, the conductive film layer 300 is electrically connected to the vertical conducting lines 14o, when the #dif body package 100 is stacked with the second semiconductor package 2000 Time, = the conductor package 200 is electrically connected to the first lane via the lightning-resistant * conductive film layer 300 on the top surface of the encapsulant and the longitudinal conductive lines 140 in the encapsulant 110. The semiconductor wafer 130 of the hi + conductor package 100 is transported to a vertical stack of multiple packages.
1223879 五、發明說明（7) 因此’本發明之封裝件堆疊模組係利用「在密封半導 體晶片130之封膠體11〇内設有縱向導通線15〇，其一端係 接合在封膠體110底面112之連接墊12〇，其另一端係顯露 於封膠體11 0頂面111」以及「貼設在封膠體丨丨〇頂面丨丨i之 異方性導電膜層3 〇 〇」之技術特徵，達到在該封膠體丨丨〇上 之縱向導通以及該些縱向導通線14〇在該封膠體11()内穩固 形成’以取代習知在封膠體外周邊之間隔電路板，將明顯 減少封裝件堆疊模組之尺寸面積與組裝成本，此外，在封 裝件堆疊模組之組裝過程，只要在該第一半導體封裝件 1 〇 0之封膠體11 〇貼設該異方性導電膜層3 〇 〇即可堆疊該第 二半導體封裝件200，並且藉由該封膠體11〇内之該些縱向 導通線1 40與該異方性導電膜層3〇〇即可使該第一半導體封 裳件1 〇 〇與第二半導體封裝件2 〇 〇電性導通，比習知需要設 置習知間隔電路板之封裝件堆疊模組製程具有更縮短之 步驟且產品信賴度更高，不需要考慮間隔電路板之翹曲 度01223879 V. Description of the invention (7) Therefore, the package stacking module of the present invention uses "a longitudinal conductive line 15 is provided in the sealing compound 11 of the sealed semiconductor wafer 130, and one end thereof is bonded to the bottom surface 112 of the sealing compound 110 The other end of the connection pad 12o is exposed on the top surface of the sealing compound 110 and the technical characteristics of the "anisotropic conductive film layer 3 00" attached to the top surface of the sealing compound 丨 丨 〇 丨, Reaching the vertical conduction on the sealant 丨 丨 〇 and the vertical conduction lines 14o are firmly formed in the sealant 11 () to replace the conventional circuit board on the periphery of the sealant, which will significantly reduce the number of packages. The size, area and assembly cost of the stacked module. In addition, during the assembly process of the packaged stacked module, as long as the anisotropic conductive film layer 3 is attached to the sealing compound 11 of the first semiconductor package 100. The second semiconductor package 200 can be stacked, and the first semiconductor package 1 can be made by the vertical conductive lines 1 40 and the anisotropic conductive film layer 300 in the sealing compound 110. 〇〇 and the second semiconductor package 2 〇 Electrically conductive than the conventional need to set the interval conventional package stacking module circuit board manufacturing process having a step of further reducing the product reliability and higher, without regard to the interval circuit board warpage 0
依本發明之第二具體實施例，請參閱第4圖，另一種 封裝件堆疊模組係包含一第一半導封裝件4〇〇、一第二半 導體封裝件200以及在第一半導體封裝件4〇〇與第二半導體 封裝件200之間的異方性導電膜層3〇〇，其中該第二半導體 封裳件200與該異方性導電膜層300與第一具體實施例相 同，並以相同圖號代表之。該第一半導封裝件4〇〇係包含 有一封膠體410、一基板420、一半導體晶片43〇及複數個 縱向導通線440，其中該基板420形成複數個連接墊421， 1223879 五、發明說明（8) 該些連接墊421係對應形成於該封膠體410之底面412，該 半導體晶片4 2 0係設於該基板4 2 0上並密封於該封膠體 410，在本實施例中，該半導體晶片42〇之背面432係朝 上’以在該半導體晶片420之主動面431之複數個凸塊433 覆晶接合至該基板4 2 0，並以該基板4 2 0之内部連接線路使 該半導體晶片420電性連接至該些連接墊421 ,此外，該封 膠體410内設有該些複數個縱向導通線44〇，該些縱向^通 線440之一端接合於該些連接墊421，其另一端係顯露於該 封膠體410之頂面411，以達到電性導通該封膠體41〇之該/ 頂面411與該底面412，較佳地，在該基板42〇之另一表面 係接合有複數個銲球4 5 0，以供外部電性連接，因此，藉 由該封膠體410内之該些縱向導通線44〇與該異方性導電膜 層300即可使該第一半導體封裝件4〇〇與第二半導體封裝件 200電性導通而達到堆疊與電性導通之封裝件堆疊模組。 依本發明之第三具體實施例，請參閱第5圖，一種封 裝件堆疊模組係包含一第一半導封裝件5〇〇、一第二半導 體封裝件200以及在第一半導體封裝件5〇〇與第二半導體 裝件200之間的異方性導電膜層3()()，其中該異方性導電膜 層300係貼設於該第一半導封裝件5 00之封膠體51 〇之頂面、 511，該第二半導體封裝件2〇〇係堆疊在該第一半導體封裝 件500上，並經由該異方性導電膜層3〇〇 裝件500電性連接。 τ π ”亥第I導體封裝件500係主要包含有-封膠體510、 複數個具有連接塾521之導職0、—半導體晶片53〇以及 1223879According to a second embodiment of the present invention, please refer to FIG. 4. Another package stacking module includes a first semiconductor package 400, a second semiconductor package 200, and a first semiconductor package. The anisotropic conductive film layer 300 between 400 and the second semiconductor package 200, wherein the second semiconductor package 200 and the anisotropic conductive film layer 300 are the same as the first embodiment, and It is represented by the same drawing number. The first semiconductor package 400 includes a colloid 410, a substrate 420, a semiconductor wafer 43, and a plurality of vertical conductive lines 440, wherein the substrate 420 forms a plurality of connection pads 421, 1223879. 5. Description of the invention (8) The connection pads 421 are correspondingly formed on the bottom surface 412 of the sealing compound 410, and the semiconductor wafer 4 2 0 is disposed on the substrate 4 2 0 and sealed to the sealing compound 410. In this embodiment, the The rear surface 432 of the semiconductor wafer 42 is facing upwards, and a plurality of bumps 433 are bonded on the active surface 431 of the semiconductor wafer 420 to the substrate 4 2 0, and the internal connection lines of the substrate 4 2 0 make the The semiconductor chip 420 is electrically connected to the connection pads 421. In addition, the sealing body 410 is provided with the plurality of vertical conductive lines 44. One end of the vertical conductive lines 440 is connected to the connection pads 421. The other end is exposed on the top surface 411 of the sealing compound 410 so as to achieve electrical conduction between the / top surface 411 and the bottom surface 412 of the sealing compound 410. Preferably, the other surface of the substrate 42 is bonded. There are multiple solder balls 4 5 0 for external electrical connection, because Therefore, the first semiconductor package 400 and the second semiconductor package 200 can be electrically connected to each other through the vertical conductive lines 44 in the sealing compound 410 and the anisotropic conductive film layer 300. Stacked and electrically conductive package stacking modules. According to a third specific embodiment of the present invention, please refer to FIG. 5. A package stacking module includes a first semiconductor package 500, a second semiconductor package 200, and a first semiconductor package 5 〇〇 and the second semiconductor package 200 between the anisotropic conductive film layer 3 () (), wherein the anisotropic conductive film layer 300 is attached to the first semiconducting package 5 00 of the sealing body 51 511, the second semiconductor package 200 is stacked on the first semiconductor package 500, and is electrically connected through the anisotropic conductive film layer 300 package 500. τ π ″ Hiltier I conductor package 500 series mainly includes-sealing gel 510, a plurality of guides with a connection 塾 521,-semiconductor wafers 53 and 1223879
複數個縱向導通線540，其中該封膠體510之頂面51ι係貼 没有4異方性導電膜層3〇〇 ’該封膠體51〇之底面512係形 成有該些連接墊521，該些導腳520係由一QFN導線架所構 成，其連接延伸之連接墊521係形成於該封膠體510之該底 面512並且具有不被該封膠體51〇覆蓋之顯露導接面，該半 導體晶片5 3 0係覆晶接合於該些導腳5 2 1，以電性連接該半 導體晶片5 3 0與該些連接墊5 2 1，在本實施例中，該些導腳 5 2 0與該半導體晶片5 3 0係被該封膠體5 1 0所密封。該半導 體晶片530係具有一主動面531及一對應之背面532，而該 主動面531係形成有複數個凸塊533，以接合該些連接墊 5 2 1延伸之導腳5 2 0，該些縱向導通線5 4 0係設於該些連接 墊521上且被該封膠體54〇密封，且每一縱向導通線540係 具有一端部’其係顯露於該封膠體5 1 〇之頂面5 11，其係與 異方性導電膜層300達到微間距縱向電性連接，以供電性 導接該第二半導體封裝件2〇〇。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準’任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。The plurality of vertical conductive lines 540, wherein the top surface 51m of the sealing gel 510 is not provided with 4 anisotropic conductive film layers 300 ′, and the bottom surface 512 of the sealing gel 51 is formed with the connection pads 521. The leg 520 is composed of a QFN lead frame, and the connecting pad 521 is formed on the bottom surface 512 of the sealing compound 510 and has an exposed conductive surface that is not covered by the sealing compound 51. The semiconductor chip 5 3 0 series flip chip is bonded to the guide pins 5 2 1 to electrically connect the semiconductor wafer 5 3 0 and the connection pads 5 2 1. In this embodiment, the guide pins 5 2 0 and the semiconductor wafer 5 3 0 is sealed by the sealant 5 1 0. The semiconductor wafer 530 has an active surface 531 and a corresponding back surface 532, and the active surface 531 is formed with a plurality of bumps 533 to engage the extending pins 5 2 0 of the connection pads 5 2 1. The longitudinal conducting lines 5 4 0 are disposed on the connection pads 521 and sealed by the sealing compound 54 〇, and each longitudinal conducting line 540 has one end portion, which is exposed on the top surface 5 of the sealing compound 5 1 〇 11. The micro-pitch vertical electrical connection is achieved with the anisotropic conductive film layer 300, and the second semiconductor package 200 is electrically conductively connected. The scope of protection of the present invention shall be determined by the scope of the appended patent application. 'Anyone skilled in the art and any changes and modifications made without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .
第17頁 1223879 圊式簡單說明 【圖式簡單說明】 I1圖：習知之封裝件堆疊模組之截面示意圖； ，2圖：：：，封裝件堆叠模組之間隔電路板之上表面示 第3圖：依本發明之第一具體眚竑 組之截面示意圖實施例’一種封裝件堆叠模 依本發明之第二具體實施 模組之截面示意圖；及 另種封裝件堆疊 依本發明之第三具體實妳 組之截面示意圖。 ，一種封裝件堆疊模 元件符號簡單說明： 10第一半導體封裝件 11 封膠體 12 2 0 第二半導體封裝件 30 間隔電路板 31 33 凸塊 34 1 0 0第一半導體封裝件 封膠體 111頂面 120連接墊 130半導體晶片 131主動 13：3銲墊 140縱向 141第一端 142第二 200第二半導體封裝件 基板 線路 連接 墊 銲球 21凸塊 32開口 面 導通線 端 第18頁 1223879 圖式簡單說明 210 對外電性連接端 300 異方性導電膜層 400 第一半導體封裝件 410 封膠體 411 頂面 412 底 面 420 基板 421 連接墊 430 半導體晶片 431 主動面 432 背 面 433 凸塊 440 縱向導通線 450 鲜球 500 第一半導體封裝件 510 封膠體 511 頂面 512 底 面 520 導腳 521 連接墊 530 半導體晶片 531 主動面 532 背 面 533 凸塊 540 縱向導通線Page 17 1223879 Simple description [simple illustration] Figure I1: a cross-sectional schematic diagram of a conventional package stacking module;, Figure 2: ::: The upper surface of the spacer circuit board of the package stacking module is shown in Figure 3 Figure: Schematic cross-sectional view of the first specific group of the embodiment of the present invention Example 'A cross-sectional schematic view of a package stacking module according to the second specific implementation module of the present invention; and another package stacking according to the third specific embodiment of the present invention Schematic cross section of your group. A simple description of the components of a package stack mold: 10 first semiconductor package 11 sealing compound 12 2 0 second semiconductor package 30 spacer circuit board 31 33 bump 34 1 0 0 top surface of the first semiconductor package sealing compound 111 120 connection pad 130 semiconductor wafer 131 active 13: 3 pad 140 vertical 141 first end 142 second 200 second semiconductor package substrate circuit connection pad solder ball 21 bump 32 open surface conduction line end page 18 1223879 diagram is simple Description 210 External electrical connection terminal 300 Anisotropic conductive film layer 400 First semiconductor package 410 Sealant 411 Top surface 412 Bottom surface 420 Substrate 421 Connection pad 430 Semiconductor wafer 431 Active surface 432 Back surface 433 Bump 440 Vertical conduction line 450 Fresh Ball 500 First semiconductor package 510 Sealant 511 Top surface 512 Bottom surface 520 Guide pin 521 Connection pad 530 Semiconductor wafer 531 Active surface 532 Back surface 533 Bump 540 Vertical conduction line
第19頁Page 19
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