CN102986006B - 使用基于飞秒的激光及等离子体蚀刻的晶圆切割 - Google Patents
使用基于飞秒的激光及等离子体蚀刻的晶圆切割 Download PDFInfo
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- 238000001020 plasma etching Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims abstract description 141
- 239000004065 semiconductor Substances 0.000 claims abstract description 112
- 238000005520 cutting process Methods 0.000 claims abstract description 90
- 239000013078 crystal Substances 0.000 claims abstract description 85
- 230000008569 process Effects 0.000 claims abstract description 76
- 238000000059 patterning Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 67
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 34
- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 229920000642 polymer Polymers 0.000 claims description 6
- 230000000670 limiting effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 79
- 238000003860 storage Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 15
- 239000002313 adhesive film Substances 0.000 description 14
- 239000002184 metal Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 238000000608 laser ablation Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000005336 cracking Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910003460 diamond Inorganic materials 0.000 description 5
- 239000010432 diamond Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000013047 polymeric layer Substances 0.000 description 4
- 208000037656 Respiratory Sounds Diseases 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 230000003685 thermal hair damage Effects 0.000 description 3
- RRHGJUQNOFWUDK-UHFFFAOYSA-N Isoprene Chemical compound CC(=C)C=C RRHGJUQNOFWUDK-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910014558 c-SiO Inorganic materials 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910002026 crystalline silica Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000002271 resection Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 2
- 230000008016 vaporization Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 1
- UWQPDVZUOZVCBH-UHFFFAOYSA-N 2-diazonio-4-oxo-3h-naphthalen-1-olate Chemical class C1=CC=C2C(=O)C(=[N+]=[N-])CC(=O)C2=C1 UWQPDVZUOZVCBH-UHFFFAOYSA-N 0.000 description 1
- -1 702) Inorganic materials 0.000 description 1
- 241000931526 Acer campestre Species 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- WBYWAXJHAXSJNI-SREVYHEPSA-N Cinnamic acid Chemical compound OC(=O)\C=C/C1=CC=CC=C1 WBYWAXJHAXSJNI-SREVYHEPSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XTXRWKRVRITETP-UHFFFAOYSA-N Vinyl acetate Chemical compound CC(=O)OC=C XTXRWKRVRITETP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 201000006549 dyspepsia Diseases 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32889—Connection or combination with other apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32899—Multiple chambers, e.g. cluster tools
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L21/67092—Apparatus for mechanical treatment
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
本发明描述切割半导体晶圆的方法,其中每一晶圆具有多个集成电路。一种方法包括以下步骤:在所述半导体晶圆上形成掩模。所述掩模由覆盖且保护所述集成电路的层组成。用基于飞秒的激光划线工艺将所述掩模图案化,以提供具有间隙的一经图案化的掩模。所述图案化曝露所述集成电路之间的所述半导体晶圆的区域。然后穿过所述经图案化的掩模中的所述间隙蚀刻所述半导体晶圆,以单分所述集成电路。
Description
相关申请案的交叉引用
本申请案主张2010年6月22日提出申请的美国临时申请案第61/357,468号的权益,所述申请的全部内容以引用的方式并入本文中。
背景
1)领域
本发明的实施例关于半导体处理领域,具体关于切割半导体晶圆的方法,其中每一晶圆上具有多个集成电路。
2)相关技术的描述
在半导体晶圆处理中,在由硅或其他半导体材料组成的晶圆(亦被称作衬底)上形成集成电路。通常,利用半导体、导电或绝缘的不同材料层来形成集成电路。使用各种公知工艺掺杂、沉积及蚀刻这些材料,以形成集成电路。处理每一晶圆以形成大量含有集成电路的个体区域,所述个体区域称为管芯。
在集成电路形成工艺之后,“切割”晶圆以将个体管芯彼此分隔,以用于封装或在较大电路内以未封装形式使用。用于晶圆切割的两种主要技术为划线及锯切。藉由划线,沿预成形的划割线越过晶圆表面移动金刚石尖头划线器。这些划割线沿管芯之间的间隔延伸。这些间隔通常被称作“切割道(street)”。金刚石划线器沿切割道在晶圆表面中形成浅划痕。在诸如以滚轴施加压力之后,晶圆沿所述划割线分开。晶圆断裂遵循晶圆衬底的晶格结构。划线可用于厚度约10密耳(千分之一英寸)或更小的晶圆。对于更厚的晶圆,目前锯切为用于切割的较佳方法。
藉由锯切,以每分钟高转数旋转的金刚石尖头锯接触晶圆表面,且沿切割道锯切晶圆。晶圆安装在诸如在薄膜框架上伸展的粘合薄膜之类的支撑构件上,且锯反复施加于垂直切割道与水平切割道两者。划线或锯切的一个问题为:切屑及挖伤可沿所述等管芯的切断边缘形成。此外,裂纹可形成且从所述管芯的边缘扩散至衬底中,且致使集成电路不工作。剥落及裂化特别为划线的问题,因为正方形或矩形管芯仅一侧可沿结晶结构的<110>方向被划线。因此,所述管芯另一侧的裂开产生一锯齿状分隔线。由于剥落及裂化,故在晶圆上的管芯之间需要额外间隔,以防止损坏集成电路,例如,将切屑及裂纹维持在与实际集成电路一定距离处。由于间隔要求,导致在一标准尺寸晶圆上不能形成同样多的管芯,且浪费了原本可用于电路的晶圆空间(realestate)。锯的使用加重半导体晶圆上空间的浪费。锯刃约15微米厚。因此,为保证由锯造成的切口周围的裂纹及其他损坏不损害集成电路,通常必须将每个所述管芯的电路分隔三百微米至五百微米。此外,在切割之后,每一管芯需要实质性清洁,以移除由锯切工艺产生的微粒及其他污染物。
亦使用了等离子体切割,但等离子体切割同样可具有局限性。举例而言,成本可为阻碍实施等离子体切割的一个局限。用于图案化抗蚀剂的标准光刻操作可致使实施成本过高。可能阻碍实施等离子体切割的另一局限为,在沿切割道切割中的常见金属(例如铜)的等离子体处理可造成生产问题或产量限制。
发明内容
本发明的实施例包括切割半导体晶圆的方法,其中每一晶圆上具有多个集成电路。
在一实施例中,一种切割具有多个集成电路的半导体晶圆的方法包括以下步骤:在所述半导体晶圆上方形成一掩模,所述掩模由覆盖且保护所述集成电路的层组成。然后用基于飞秒的激光划线工艺将所述掩模图案化,以提供具有间隙的经图案化的掩模,从而曝露所述集成电路之间的所述半导体晶圆的区域。然后穿过所述经图案化的掩模中的所述间隙蚀刻所述半导体晶圆,以单片化所述集成电路。
在另一实施例中,一种用于切割半导体晶圆的***包括工厂接口。激光划线设备与所述工厂接口耦合,且包括基于飞秒的激光。等离子体蚀刻腔室亦与所述工厂接口耦合。
在另一实施例中,一种切割具有多个集成电路的半导体晶圆的方法包括以下步骤:在硅衬底上方形成聚合物层。所述聚合物层覆盖且保护安置于所述硅衬底上的集成电路。所述集成电路由安置于低介电常数材料层及铜层上方的二氧化硅层组成。用基于飞秒的激光划线工艺将所述聚合物层、所述二氧化硅层、所述低介电常数材料层及所述铜层图案化,以曝露所述集成电路之间的所述硅衬底的区域。然后穿过间隙蚀刻所述硅衬底,以单片化所述集成电路。
附图说明
图1图示根据本发明的实施例的待切割的半导体晶圆的俯视图。
图2图示根据本发明的实施例的待切割的半导体晶圆的俯视图,所述半导体晶圆上形成有切割掩模。
图3为示出根据本发明的实施例的切割半导体晶圆的方法的操作的流程图,所述半导体晶圆包括多个集成电路。
图4A图示根据本发明的实施例的在执行切割所述半导体晶圆的方法期间的包括多个集成电路的半导体晶圆的横截面图,所述横截面图对应于图3的流程图的操作302。
图4B图示根据本发明的实施例的在执行切割所述半导体晶圆的方法期间的包括多个集成电路的半导体晶圆的横截面图,所述横截面图对应于图3的流程图的操作304。
图4C图示根据本发明的实施例的在执行切割所述半导体晶圆的方法期间的包括多个集成电路的半导体晶圆的横截面图,所述横截面图对应于图3的流程图的操作306。
图5图示根据本发明的实施例的使用飞秒范围内的激光脉冲与较长脉冲时间比较的效果。
图6图示根据本发明的实施例的可用于半导体晶圆或衬底的切割道区域的材料的堆迭的横截面图。
图7包括根据本发明的实施例的结晶硅(c-Si)、铜(Cu)、结晶二氧化硅(c-SiO2)及非晶二氧化硅(a-SiO2)的吸收系数随着光子能变化的曲线图。
图8为方程序,所述方程序展示给定激光的激光强度与激光脉冲能量、激光脉冲宽度及激光光束半径的函数关系。
图9A至图9D图示根据本发明的实施例的切割半导体晶圆的方法的不同操作的横截面图。
图10图示根据本发明的实施例的藉由使用与常规切割相比较窄的切割道达成的半导体晶圆上的紧密作用,所述常规切割可受限于最小宽度。
图11图示根据本发明的实施例的允许较紧密堆积且因此与栅格对准方法相比允许每晶圆更多的管芯的自由形式集成电路布置。
图12图示根据本发明的实施例的用于晶圆或衬底的激光及等离子体切割的工具布局的框图。
图13图示根据本发明的实施例的示例性计算机***的框图。
具体实施方式
已描述切割半导体晶圆的方法,其中每一晶圆上具有多个集成电路。在以下描述中阐述众多特定细节,诸如基于飞秒的激光划线及等离子体蚀刻条件及材料状况,以提供对本发明的实施例的透彻理解。对本领域普通技术人员显而易见的是,本发明的实施例可在无这些特定细节的情况下实施。在其他实例中,诸如集成电路制造的公知方面不作详述,以免不必要地使本发明的实施例难以理解。此外,应理解,附图中所示的各种实施例为说明性表示,且未必按比例绘制。
可实施涉及初始激光划线及后续等离子体蚀刻的混合晶圆或衬底切割工艺,以用于管芯单片化。激光划线工艺可用于清除掩模层、有机及无机介电层及器件层。然后可在曝露或部分蚀刻晶圆或衬底之后终止所述激光蚀刻工艺。然后可使用切割工艺的等离子体蚀刻部分来蚀刻穿过大块的晶圆或衬底(诸如穿过大块单晶硅),以产生管芯或芯片单片化或切割。
常规晶圆切割方法包括基于纯机械分离的金刚石锯切、初始激光划线及后续金刚石锯切割或纳秒或皮秒激光切割。对于诸如50微米厚的大块硅单片化之类的薄晶圆或衬底单片化而言,所述常规方法仅产生不良工艺品质。在从薄晶圆或衬底单片化管芯时可能面临的一些挑战可包括:在不同层之间形成微裂或分层、无机介电层的剥落、保持严格的锯口宽度控制或精确的切除深度控制。本发明的实施例包括混合激光划线及等离子体蚀刻管芯单片化方法,所述方法可适用于克服上述挑战中的一个或多个。
根据本发明的实施例,基于飞秒的激光划线与等离子体蚀刻的组合用于将半导体晶圆切割成个体化或单片化的集成电路。在一个实施例中,基于飞秒的激光划线被用作基本(若非完全)非热工艺。举例而言,所述基于飞秒的激光划线可定位于无热损坏或可忽略热损坏的区域。在实施例中,本文的方法用于具有超低介电常数薄膜的经单片化的集成电路。藉由常规切割,可能需要锯减速以适应此类低介电常数薄膜。此外,现在通常在切割之前将半导体晶圆减薄。因此,在实施例中,现在常见将掩模图案化与使用基于飞秒的激光的部分晶圆划线组合,并继之以等离子体蚀刻工艺。在一个实施例中,藉由激光直接写入可排除对光阻层的光刻图案化操作的需要,且可以极低的成本实施。在一个实施例中,使用通孔型硅蚀刻在等离子体蚀刻环境中完成所述切割工艺。
因此,在本发明的方面中,可使用基于飞秒的激光划线与等离子体蚀刻的组合将半导体晶圆切割成单片化的集成电路。图1图示根据本发明的实施例的待切割的半导体晶圆的俯视图。图2图示根据本发明的实施例的待切割的半导体晶圆的俯视图,所述半导体晶圆上形成有切割掩模。
参看图1,半导体晶圆100具有包括集成电路的多个区域102。区域102由垂直切割道104及水平切割道106分隔。切割道104及切割道106为不含集成电路的半导体晶圆的区域,且将切割道104及切割道106设计为切割晶圆所沿着的位置。本发明的一些实施例涉及利用基于飞秒的激光划线与等离子体蚀刻技术的组合,以沿所述切割道穿过半导体晶圆切割沟道,以使得所述管芯被分成个体芯片或管芯。由于激光划线与等离子体蚀刻工艺皆不依赖于结晶结构定向,所以待切割的半导体晶圆的结晶结构对实现穿过所述晶圆的垂直沟道并不重要。
参看图2,半导体晶圆100具有沉积于半导体晶圆100上的掩模200。在一个实施例中,所述掩模以常规方式经沉积,以实现约4-10微米厚的层。用激光划线工艺将掩模200及半导体晶圆100的一部分图案化,以沿切割道104及切割道106界定切割半导体晶圆100所在的位置(例如间隙202及204)。半导体晶圆100的集成电路区域由掩模200覆盖及保护。掩模200的区域206经定位以使得在后续刻蚀工艺期间,集成电路不被所述蚀刻工艺降级。在区域206之间形成水平间隙204及垂直间隙202,以界定将在蚀刻工艺期间被蚀刻以最终切割半导体晶圆100的区域。
图3为根据本发明的实施例的表示切割半导体晶圆的方法的操作的流程图300,所述半导体晶圆包括多个集成电路。图4A至图4C图示根据本发明的实施例在执行切割所述半导体晶圆的方法期间的包括多个集成电路的半导体晶圆的横截面图,所述横截面图对应于流程图300的操作。
参看流程图300的操作302以及相应图4A,掩模402形成于半导体晶圆或衬底404上方。掩模402由覆盖且保护集成电路406的层组成,集成电路406形成于半导体晶圆404的表面上。掩模402亦覆盖介入切割道407,介入切割道407形成于集成电路406中的每一者之间。
根据本发明的实施例,形成掩模402包括:形成诸如(但不限于)光阻层或自交系(I-line)图案化层之类的层。举例而言,诸如光阻层之类的聚合物层可由另外适用于光刻工艺的材料组成。在一个实施例中,所述光阻层由正光阻材料组成,诸如(但不限于)248纳米(nm)抗蚀剂、193nm抗蚀剂、157nm抗蚀剂、极紫外线(extremeultra-violet;EUV)抗蚀剂或含有重氮基萘醌敏化剂的酚树脂介质。在另一实施例中,所述光阻层由负光阻材料组成,诸如(但不限于)聚顺异戊二烯及聚桂皮酸乙烯酯。
在实施例中,半导体晶圆或衬底404由适合于经受制造工艺的材料组成,且可将半导体处理层适当安置于所述材料上。举例而言,在一个实施例中,半导体晶圆或衬底404由基于IV族的材料组成,诸如(但不限于)结晶硅、锗或硅/锗。在特定实施例中,提供半导体晶圆404包括:提供单晶硅衬底。在特定实施例中,所述单晶硅衬底掺杂有杂质原子。在另一实施例中,半导体晶圆或衬底404由III-V族材料组成,诸如用于发光二极管(lightemittingdiode;LED)的制造的III-V族材料衬底。
在实施例中,半导体晶圆或衬底404具有安置于半导体晶圆或衬底404上或半导体晶圆或衬底404中的半导体器件的阵列,所述半导体器件作为集成电路406的一部分。此类半导体器件的实例包括(但不限于):在硅衬底中制造且包装于介电层中的存储器器件或互补金属氧化物半导体(complimentarymetal-oxide-semiconductor;CMOS)晶体管。在所述器件或晶体管上方及周围介电层中可形成多个金属互连,且所述金属互连可用于电气耦合所述器件或晶体管,以形成集成电路406。组成切割道407的材料可与用于形成集成电路406的那些材料相似或相同。举例而言,切割道407可由多层介电材料、半导体材料及金属化组成。在一个实施例中,切割道407中的一个或多个包括类似于集成电路406的实际器件的测试器件。
参看流程图300的操作304以及相应图4B,用基于飞秒的激光划线工艺将掩模402图案化,以提供具有间隙410的经图案化的掩模408,从而曝露集成电路406之间的半导体晶圆或衬底404的区域。因此,基于飞秒的激光划线工艺用于移除最初形成于集成电路406之间的切割道407的材料。根据本发明的实施例,用基于飞秒的激光划线工艺将掩模402图案化包括:形成沟道412部分进入集成电路406之间的半导体晶圆404的区域,如图4B所示。
在实施例中,用激光划线工艺将掩模408图案化包括:使用具有飞秒范围内的脉冲宽度的激光。具体而言,具有在可见光谱加紫外线(ultra-violet;UV)及红外线(infra-red;IR)范围(总计宽频光谱)内的波长的激光可用于提供基于飞秒的激光,亦即具有量级为飞秒(10-15秒)的脉冲宽度的激光。在一个实施例中,切除不依赖于或基本不依赖于波长,且因此适合于复合薄膜,诸如掩模402的薄膜、切割道407的薄膜及可能一部分半导体晶圆或衬底404的薄膜。
图5图示根据本发明的实施例的使用飞秒范围内的激光脉冲与较长频率比较的效果。参看图5,与较长脉冲宽度比较(例如,藉由皮秒处理通孔500B产生损坏502B及藉由纳秒处理通孔500A产生显著损坏502A),使用具有飞秒范围内的脉冲宽度的激光缓解或消除了热损坏问题(例如,藉由飞秒处理通孔500C最小化至无损坏502C)。在形成通孔500C期间损坏的消除或缓解可归因于缺乏低能量再耦合(如见于基于皮秒的激光切除)或热平衡(如见于基于纳秒的激光切除),如图5所示。
激光参数选择(诸如脉冲宽度)可为研发成功的激光划线及切割工艺的关键,成功的激光划线及切割工艺将剥落、微裂及分层减至最少,以达成平整的激光划线切口。激光划线切口愈平整,则用于最终的管芯单片化而执行的蚀刻工艺愈顺利。在半导体器件晶圆中,许多不同材料类型(例如导体、绝缘体、半导体)及厚度的功能层通常安置于半导体元件晶圆上。此类材料可包括(但不限于)诸如聚合物之类的有机材料、金属或诸如二氧化硅及氮化硅之类的无机电介质。
安置于晶圆或衬底上的个体集成电路之间的切割道可包括与所述集成电路本身相似或相同的层。举例而言,图6图示根据本发明的实施例的材料的堆迭的横截面图,所述材料可用于半导体晶圆或衬底的切割道区域中。
参看图6,切割道区域600包括硅衬底的顶部部分602、第一二氧化硅层604、第一蚀刻终止层606、第一低介电常数介电层608(例如,具有小于二氧化硅的介电常数4.0的介电常数)、第二蚀刻终止层610、第二低介电常数介电层612、第三蚀刻终止层614、无掺杂硅玻璃(undopedsilicaglass;USG)层616、第二二氧化硅层618及光阻层620,其中描绘了相对厚度。铜金属化622安置于第一蚀刻终止层606与第三蚀刻终止层614之间,且穿过第二蚀刻终止层610。在特定实施例中,第一蚀刻终止层606、第二蚀刻终止层610及第三蚀刻终止层614由氮化硅组成,而低介电常数介电层608及612由掺碳氧化硅材料组成。
在常规激光照射(诸如基于纳秒或基于皮秒的激光照射)下,切割道600的材料在光吸收及切除机制方面表现相当不同。举例而言,诸如二氧化硅之类的介电层在正常情况下对所有市售的激光波长均为基本透明。相反,金属、有机物(例如低介电常数材料)及硅能够非常容易地耦合光子,尤其响应于基于纳秒或基于皮秒的激光照射。举例而言,图7包括根据本发明的实施例的结晶硅(c-Si,702)、铜(Cu,704)、结晶二氧化硅(c-SiO2,706)及非晶二氧化硅(a-SiO2,708)的吸收系数随着光子能变化的曲线图700。图8为方程序800,所述方程序展示给定激光的激光强度与激光脉冲能量、激光脉冲宽度及激光光束半径的函数关系。
在实施例中,利用方程序800及吸收系数的曲线图700,可选择基于飞秒激光的工艺的参数,以对无机及有机电介质、金属及半导体实现基本共同的切除效应,尽管此类材料的一般能量吸收特征在某些条件下可大不相同。举例而言,二氧化硅的吸收率为非线性的,且在适当激光切除参数下二氧化硅的吸收率可与有机电介质、半导体及金属的吸收率更加一致。在一个此类实施例中,高强度及短脉冲宽度的基于飞秒的激光工艺用于切除层的堆迭,所述层的堆迭包括二氧化硅层及有机电介质、半导体或金属中的一个或多个。在特定实施例中,约小于或等于400飞秒的脉冲用于基于飞秒的激光照射工艺,以移除掩模、切割道及一部分硅衬底。
相反,若选择非最佳激光参数,则在涉及无机电介质、有机电介质、半导体或金属中的两者或两者以上的堆迭结构中,激光切除工艺可造成分层问题。举例而言,激光穿透高带隙能量电介质(诸如具有约9eV带隙的二氧化硅),而无可量测吸收。然而,所述激光能可在下方的金属层或硅层中被吸收,从而引起所述金属层或硅层的显著汽化。所述汽化可产生高压,以升起上覆的二氧化硅介电层,且可能造成严重的层间分层及微裂化。在一实施例中,尽管基于皮秒的激光照射工艺在复合堆迭中导致微裂化及分层,但已证明,基于飞秒的激光照射工艺并不导致相同材料堆迭的微裂化或分层。
为了能够直接切除介电层,介电材料可能需要发生离子化,以使得所述介电材料藉由强吸收光子而与导电材料表现相似。所述吸收可在最终切除介电层之前阻碍大部分激光能量穿透至下方的硅层或金属层。在一实施例中,当激光强度足够高以致在无机介电材料中引发光子离子化及撞击离子化时,所述无机电介质的离子化是可行的。
根据本发明的一实施例,合适的基于飞秒的激光工艺的特征为:高峰值强度(照射度),所述高峰值强度通常在不同材料中导致非线性相互作用。在一个此类实施例中,飞秒激光源具有近似在10飞秒至500飞秒的范围内的脉冲宽度,不过所述脉冲宽度较佳在100飞秒至400飞秒的范围内。在一个实施例中,飞秒激光源具有近似在1570纳米至200纳米的范围内的波长,不过所述波长较佳在540纳米至250纳米的范围内。在一个实施例中,激光及相应光学***在工作表面处提供近似在3微米至15微米的范围内的焦点,不过所述焦点较佳近似在5微米至10微米的范围内。
在所述工作表面处的空间光束剖面可为单模(高斯)或具有顶帽形状的剖面。在一实施例中,激光源具有近似在200kHz至10MHz范围内的脉冲重复率,不过所述脉冲重复率较佳近似在500kHz至5MHz的范围内。在一实施例中,激光源在工作表面处传递近似在0.5uJ至100uJ的范围内的脉冲能量,不过所述脉冲能量较佳近似在1uJ至5uJ的范围内。在一实施例中,激光划线工艺以近似在500mm/sec至5m/sec的范围内的速度沿工件表面执行,不过所述速度较佳近似在600mm/sec至2m/sec的范围。
划线工艺可仅单程执行或多程执行,但在一实施例中,较佳1至2程。在一个实施例中,工件的划线深度近似在5微米至50微米深的范围内,较佳近似在10微米至20微米深的范围内。激光可以给定的脉冲重复率施加于一系列单一脉冲中,或一系列脉冲猝发中。在一实施例中,所产生激光光束的锯口宽度近似在2微米至15微米的范围内,不过在硅晶圆划线/切割中在元件/硅接口处所量测的所述锯口宽度较佳近似在6微米至10微米的范围内。
可选择具有以下益处及优点的激光参数:诸如提供足够高的激光强度,以达成无机电介质(例如二氧化硅)的离子化,且在直接切除无机电介质之前将由底层损坏造成的分层及切削减至最少。又,可选择参数,以藉由精确控制的切除宽度(例如锯口宽度)及深度提供用于工业应用的有意义的工艺产量。如上所述,与基于皮秒及基于纳秒的激光切除工艺相比,基于飞秒的激光远远更适合于提供此类优点。然而,即使在基于飞秒的激光切除的光谱中,某些波长亦可提供较其他波长更佳的性能。举例而言,在一个实施例中,与具有更接近红外线范围或在红外线范围内的波长的基于飞秒的激光工艺相比,具有更接近紫外线范围或在紫外线范围内的波长的基于飞秒的激光工艺提供更平整的切除工艺。在一特定此类实施例中,适合于半导体晶圆或衬底划线的基于飞秒的激光工艺是基于具有约小于或等于540纳米的波长的激光。在一特定此类实施例中,使用约小于或等于400飞秒的脉冲的激光,所述激光具有约小于或等于540纳米的波长。然而,在替代实施例中,使用双激光波长(例如,红外线激光与紫外线激光的组合)。
参看流程图300的操作306及相应图4C,穿过经图案化的掩模408中的间隙410将半导体晶圆404蚀刻,以单片化集成电路406。根据本发明的一实施例,蚀刻半导体晶圆404包括:蚀刻用基于飞秒的激光划线工艺形成的沟道412,以最终完全蚀刻穿过半导体晶圆404,如图4C所示。
在一实施例中,蚀刻半导体晶圆404包括:使用等离子体蚀刻工艺。在一个实施例中,使用硅通孔(through-silicon-via)型蚀刻工艺。举例而言,在一特定实施例中,半导体晶圆404的材料的蚀刻速度大于25微米/分钟。超高密度等离子体源可用于管芯单片化工艺的等离子体蚀刻部分。适于执行此类等离子体蚀刻工艺的处理腔室的示例为可购自应用材料公司(美国加利福尼亚州桑尼维尔市)的AppliedSilviaTMEtch***。AppliedSilviaTMEtch***组合电容性与感应射频(radiofrequency;RF)耦合,与仅电容性耦合甚至磁性增强所提供改良的可能情况相比,电容性与感应射频耦合给予离子密度及离子能量更多独立控制。此组合使离子密度能够与离子能量有效地去耦,以便即使在极低压力下亦可实现不具有可能有害的高直流(DC)偏压电平的相对较高密度的等离子体。此举产生异常宽的工艺窗口。然而,可使用能够蚀刻硅的任何等离子体蚀刻腔室。在一示例性实施例中,深硅蚀刻用于以大于约40%的常规硅蚀刻速度的蚀刻速度蚀刻单晶硅衬底或晶圆404,同时维持基本精确的剖面控制及实质上无扇形的侧壁。在一特定实施例中,使用硅通孔型蚀刻工艺。所述蚀刻工艺是基于反应性气体所产生的等离子体,所述反应性气体通常为氟基气体,诸如SF6、C4F8、CHF3、XeF2,或能够以相对较快蚀刻速度蚀刻硅的任何其他反应性气体。在一实施例中,在单片化工艺后移除掩模层408,如图4C所示。
因此,再次参看流程图300及图4A至图4C,可藉由初始激光切除穿过掩模层、穿过晶圆切割道(包括金属化)且部分进入硅衬底而执行晶圆切割。可在飞秒范围内选择所述激光脉冲宽度。然后可藉由后续穿硅等离子体深蚀刻完成管芯单片化。根据本发明的一实施例,下文结合图9A至图9D描述用于切割的材料堆迭的特定示例。
参看图9A,用于混合激光切除及等离子体蚀刻切割的材料堆迭包括掩模层902、器件层904及衬底906。掩模层、器件层及衬底安置于管芯粘着薄膜908上方,管芯粘着薄膜908附着至衬带910。在一实施例中,掩模层902为光阻层,诸如上文结合掩模402所述的光阻层。器件层904包括安置于一个或多个金属层(诸如铜层)及一个或多个低介电常数介电层(诸如掺碳氧化物层)上方的无机介电层(诸如二氧化硅)。元件层904亦包括布置于集成电路之间的切割道,所述切割道包括与集成电路相同或相似的层。衬底906为大块单晶硅衬底。
在一实施例中,在大块单晶硅衬底906附着至管芯粘着薄膜908之前,从背侧使大块单晶硅衬底906变薄。可藉由背侧研磨工艺执行所述变薄步骤。在一实施例中,使大块单晶硅衬底906变薄至近似在50-100微米范围内的厚度。在一实施例中,重要的是应注意,在激光切除及等离子体蚀刻切割工艺之前执行所述变薄。在一实施例中,光阻层902具有约5微米的厚度,而器件层904具有近似在2-3微米范围内的厚度。在一实施例中,管芯粘着薄膜908(或能够将变薄或薄的晶圆或衬底接合至衬带910的任何合适的替代物)具有约20微米的厚度。
参看图9B,用基于飞秒的激光划线工艺912将掩模902、器件层904及一部分衬底906图案化,以在衬底906中形成沟道914。参看图9C,穿硅等离子体深蚀刻工艺916用于将沟道914向下延伸至管芯粘着薄膜908,从而曝露管芯粘着薄膜908的顶部部分且单片化硅衬底906。在穿硅等离子体深蚀刻工艺916期间,藉由光阻层902保护器件层904。
参看图9D,单片化工艺可进一步包括:将管芯粘着薄膜908图案化,从而曝露衬带910的顶部部分且单片化管芯粘着薄膜908。在一实施例中,藉由激光工艺或藉由蚀刻工艺单片化管芯粘着薄膜。其他实施例可包括:随后从衬带910移除衬底906的单片化的部分(例如,作为个体集成电路)。在一个实施例中,单片化的管芯粘着薄膜908保留在衬底906的单片化的部分的背侧上。其他实施例可包括:从器件层904移除掩模光阻层902。在一替代实施例中,在衬底906比约50微米薄的情况下,激光切除工艺912用于彻底单片化衬底906,而无需使用额外等离子体工艺。
在一实施例中,在单片化管芯粘着薄膜908之后,从器件层904移除掩模光阻层902。在一实施例中,从衬带910移除单片化的集成电路,以用于封装。在一个此类实施例中,经图案化的管芯粘着薄膜908保留在每一集成电路的背侧上且包括在最终的封装中。然而,在另一实施例中,在单片化工艺期间或在单片化工艺之后移除经图案化的管芯粘着薄膜908。
再次参看图4A至图4C,可藉由具有约10微米或更小的宽度的切割道407分隔所述多个集成电路406。利用基于飞秒的激光划线方法,可在集成电路的布局中使此紧密作用得以实现,此举至少部分归因于严密的激光剖面控制。举例而言,图10图示根据本发明的一实施例,藉由使用与常规切割相比较窄的切割道实现的半导体晶圆或衬底上的紧密作用,所述常规切割可限于最小宽度。
参看图10,藉由使用与常规切割相比较窄的切割道(例如,在布局1002中约10微米或更小的宽度)实现半导体晶圆上的紧密作用,所述常规切割可限于最小宽度(例如,在布局1000中约70微米或更大的宽度)。然而,应理解,即使在其他方面可藉由基于飞秒的激光划线工艺来实现,并非总是期望将切割道宽度减少至小于10微米。举例而言,一些应用可能需要至少40微米的切割道宽度,以在分隔集成电路的切割道中制造虚拟器件或测试器件。
再次参看图4A至图4C,所述多个集成电路406可以非限制性布局布置在半导体晶圆或衬底404上。举例而言,图11图示允许较紧密堆积的自由形式集成电路布置。根据本发明的一实施例,与栅格对准方法相比,所述较紧密堆积可提供每晶圆更多的管芯。参看图11,自由形式布局(例如半导体晶圆或衬底1102上的非限制性布局)允许较紧密堆积,且因此与栅格对准方法(例如,半导体晶圆或衬底1100上的限制性布局)相比允许每晶圆更多的管芯。在一实施例中,激光切除及等离子体蚀刻单片化工艺的速度与管芯大小、布局或切割道数目无关。
单一工艺工具可经配置以执行混合基于飞秒的激光切除及等离子体蚀刻单片化工艺中的许多或全部操作。举例而言,图12图示根据本发明的一实施例用于晶圆或衬底的激光及等离子体切割的工具布局的框图。
参看图12,工艺工具1200包括工厂接口(factoryinterface;FI)1202,工厂接口1202具有与工厂接口1202耦合的多个负载锁室1204。群集工具1206与工厂接口1202耦合。群集工具1206包括一或多个等离子体蚀刻腔室,诸如等离子体蚀刻腔室1208。激光划线设备1210亦耦合至工厂接口1202。在一个实施例中,工艺工具1200的整体覆盖面积可为约3500毫米(3.5米)×约3800毫米(3.8米),如图12所示。
在一实施例中,激光划线设备1210容纳基于飞秒的激光。基于飞秒的激光适合于执行混合激光及蚀刻单片化工艺的激光切除部分,诸如上述的激光切除工艺。在一个实施例中,激光划线设备1200中亦包括活动平台,所述活动平台经设置以用于使晶圆或衬底(或晶圆或衬底的载体)相对于基于飞秒的激光移动。在一特定实施例中,基于飞秒的激光亦可活动。在一实施例中,激光划线设备1210的整体覆盖面积可为约2240毫米×约1270毫米,如图12所示。
在一实施例中,一个或多个等离子体蚀刻腔室1208经设置以用于穿过经图案化的掩模中的间隙蚀刻晶圆或衬底,以单片化多个集成电路。在一个此类实施例中,一个或多个等离子体蚀刻腔室1208经设置以执行深硅蚀刻工艺。在一特定实施例中,一个或多个等离子体蚀刻腔室1208为AppliedSilviaTMEtch***,所述***可购自应用材料公司(美国加尼福尼亚州桑尼维尔市)。可将所述蚀刻腔室特定设计用于深硅蚀刻,所述深硅蚀刻用于产生安放于单晶硅衬底或晶圆上或单晶硅衬底或晶圆中的单片化的集成电路。在一实施例中,等离子体蚀刻腔室1208中包括高密度等离子体源,以促进高的硅蚀刻速度。在一实施例中,工艺工具1200的群集工具1206部分中包括超过一个的蚀刻腔室,以使单片化或切割工艺的高制造产量得以实现。
工厂接口1202可为合适的大气端口,所述大气端口作为带有激光划线设备1210的外部制造设施与群集工具1206之间的接口。工厂接口1202可包括具有臂或叶片的机器人,所述机器人用于将晶圆(或晶圆的载体)从储存单元(诸如前开口式晶圆盒)传送至群集工具1206或激光划线设备1210或所述两者中。
群集工具1206可包括适合于执行单片化方法中的功能的其他腔室。举例而言,在一个实施例中,群集工具1206包括沉积腔室1212,以代替额外的蚀刻腔室。沉积腔室1212可经设置以用于在晶圆或衬底的激光划线之前在晶圆或衬底的器件层上或上方沉积掩模。在一个此类实施例中,沉积腔室1212适合于沉积光阻层。在另一实施例中,群集工具1206包括湿润/干燥站1214,以代替额外的蚀刻腔室。所述湿润/干燥站可适合于清洁残渣及碎片,或用于在衬底或晶圆的激光划线及等离子体蚀刻单片化工艺之后移除掩模。在一实施例中,群集工具1206亦包括作为工艺工具1200的部件的测量站。
本发明的实施例可提供为计算机程序产品或软体,所述计算机程序产品或软体可包括机器可读取介质,所述机器可读取介质上储存有指令,所述指令可用于对计算机***(或其他电子元件)编程以执行根据本发明的实施例的工艺。在一个实施例中,所述计算机***与结合图12描述的工艺工具1200耦合。机器可读取介质包括用于储存或传送由机器(例如计算机)读取的形式的信息的任何机构。举例而言,机器可读取(例如计算机可读取)介质包括机器(例如计算机)可读取储存介质(例如只读存储器(readonlymemory;ROM)、随机存取存储器(randomaccessmemory;RAM)、磁碟储存介质、光学储存介质、快闪存储器器件等等)、机器(例如计算机)可读取传输介质(电气、光学、声学或其他传播信号形式(例如红外信号、数字信号等等)),等等。
图13图示以计算机***1300为示例性形式的机器的图形表示,在计算机***1300内可执行一组指令,所述指令用于使机器执行本文所述方法中的任何一个或多者。在替代实施例中,所述机器可在局域网(LocalAreaNetwork;LAN)、企业内部网、企业外部网或因特网中连接(例如网路连接)至其他机器。所述机器在客户端-服务器网络环境中可作为服务器或客户端机器工作,或在对等(或分散式)网络环境中作为对等机器工作。所述机器可为个人计算机(personalcomputer;PC)、平板PC、机顶盒(set-topbox;STB)、个人数字助理(PersonalDigitalAssistant;PDA)、蜂窝式电话、web设备、服务器、网络路由器、交换机或桥接器,或能够执行指定所述机器将要采取的动作(顺序或其他方式)的一组指令的任何机器。此外,尽管仅图示单个机器,但术语“机器”亦应被视为包括个体或共同执行一组(或多组)指令以执行本文所述方法中的任何一个或多者的机器(例如计算机)的任何集合。
示例性计算机***1300包括处理器1302、主存储器1304(例如只读存储器(ROM)、快闪存储器、诸如同步DRAM(SDRAM)或RambusDRAM(RDRAM)之类的动态随机存取存储器(dynamicrandomaccessmemory;DRAM)等等)、静态存储器1306(例如快闪存储器、静态随机存取存储器(staticrandomaccessmemory;SRAM)等等)及辅助存储器1318(例如数据储存器件),所述设备经由总线1330彼此通讯。
处理器1302表示一个或多个通用处理器件,诸如微处理器、中央处理单元等等。更特定言之,处理器1302可为复杂指令集计算(complexinstructionsetcomputing;CISC)微处理器、精简指令集计算(reducedinstructionsetcomputing;RISC)微处理器、超长指令字集(verylonginstructionword;VLIW)微处理器、实施其他指令集的处理器或实施指令集组合的处理器。处理器1302亦可为一个或多个专用处理元件,诸如专用集成电路(applicationspecificintegratedcircuit;ASIC)、现场可编程门阵列(fieldprogrammablegatearray;FPGA)、数字信号处理器(digitalsignalprocessor;DSP)、网络处理器等等。处理器1302经设置以执行用于执行本文所述操作的处理逻辑1326。
计算机***1300可进一步包括网络接口器件1308。计算机***1300亦可包括视频显示单元1310(例如液晶显示器(liquidcrystaldisplay;LCD)、发光二极管(LED)显示器或阴极射线管(cathoderaytube;CRT))、字母数字输入设备1312(例如键盘)、光标控制设备1314(例如鼠标)及信号产生设备1316(例如扬声器)。
辅助存储器1318可包括机器可存取储存介质(或更具体而言,计算机可读取储存介质)1331,实施本文所述方法或功能中的任何一个或多者的一或多组指令(例如软件1322)储存在机器可存取储存介质1331上。在计算机***1300执行软件1322期间,软件1322亦可完全或至少部分地常驻于主存储器1304内部及/或处理器1302内部,主存储器1304及处理器1302亦构成机器可读取储存介质。可进一步经由网络接口器件1308在网络1320上发送或接收软件1322。
尽管在示例性实施例中将机器可存取储存介质1331图示为单个介质,但术语“机器可读取储存介质”应被视为包括储存一组或多组指令的单个介质或多个介质(例如集中式或分布式数据库,和/或相关联的高速缓存及服务器)。术语“机器可读取储存介质”亦应被视为包括能够储存或编码由机器执行且使机器执行本发明的方法中任何一个或多者的一组指令的任何介质。因此,术语“机器可读取储存介质”应被视为包括(但不限于)固态存储器以及光学及磁性介质。
根据本发明的实施例,机器可存取储存介质具有储存在机器可存取储存介质上的指令,所述指令使数据处理***执行切割具有多个集成电路的半导体晶圆的方法。所述方法包括在半导体晶圆上方形成掩模,所述掩模由覆盖且保护集成电路的一层组成。然后用基于飞秒的激光划线工艺将所述掩模图案化,以提供具有间隙的经图案化的掩模。在集成电路之间曝露所述半导体晶圆的区域。然后穿过经图案化的掩模中的间隙蚀刻半导体晶圆,以单片化集成电路。
因此,本文揭示了切割半导体晶圆的方法,其中每一晶圆具有多个集成电路。根据本发明的一实施例,切割具有多个集成电路的半导体晶圆的方法包括以下步骤:在所述半导体晶圆上形成掩模,所述掩模由覆盖且保护所述集成电路的一层组成。所述方法亦包括以下步骤:用基于飞秒的激光划线工艺将所述掩模图案化,以提供具有间隙的经图案化的掩模,从而曝露所述集成电路之间的半导体晶圆的区域。所述方法亦包括以下步骤:穿过经图案化的掩模中的间隙蚀刻所述半导体晶圆,以单片化集成电路。在一个实施例中,用基于飞秒的激光划线工艺将所述掩模图案化包括:在所述集成电路之间的半导体晶圆的区域中形成沟道。在所述实施例中,蚀刻半导体晶圆包括:蚀刻由激光划线工艺形成的沟道。
Claims (13)
1.一种切割包含多个集成电路的半导体晶圆的方法,所述方法包括以下步骤:
在所述半导体晶圆上形成掩模,所述掩模包括覆盖且保护所述集成电路的层;
用基于飞秒的激光划线工艺将所述掩模图案化,以提供经激光划线的掩模,所述掩模具有多个划线,每个划线具有宽度,所述划线曝露所述集成电路之间的所述半导体晶圆的多个区域;以及
在所述半导体晶圆中以等离子体蚀刻方式蚀刻出多个沟道,以单片化所述集成电路,每个沟道具有所述宽度。
2.如权利要求1所述的方法,其特征在于,用所述基于飞秒的激光划线工艺将所述掩模图案化的步骤包括在所述集成电路之间的所述半导体晶圆的所述区域中形成多个经激光刻划的沟道,且在所述半导体晶圆中以等离子体蚀刻方式蚀刻出多个沟道的步骤包括延伸所述多个经激光刻划的沟道以单片化所述集成电路。
3.如权利要求1所述的方法,其特征在于,用所述基于飞秒的激光划线工艺将所述掩模图案化的步骤包括使用一激光,所述激光具有约小于或等于540纳米的波长,且所述激光具有约小于或等于400飞秒的激光脉冲宽度。
4.如权利要求1所述的方法,其特征在于,等离子体蚀刻所述半导体晶圆的步骤包括使用高密度等离子体蚀刻工艺。
5.如权利要求1所述的方法,其特征在于,形成所述掩模的步骤包括以下步骤:形成从由光阻层和自交系图案化层组成的群组中选择的层。
6.如权利要求1所述的方法,其特征在于,所述多个集成电路由多个切割道分隔,所述切割道具有约10微米或更小的宽度,所述宽度是在器件层/衬底界面处量测的。
7.如权利要求1所述的方法,其特征在于,所述多个集成电路具有非限制性布局。
8.一种切割包括多个集成电路的半导体晶圆的方法,所述方法包括以下步骤:
在硅衬底上形成聚合物掩膜层,所述聚合物掩膜层覆盖且保护安置于所述硅衬底上的多个集成电路,所述集成电路包括二氧化硅层,所述二氧化硅层安置于低介电常数材料层及铜层上;
用基于飞秒的激光划线工艺将所述聚合物掩膜层、所述二氧化硅层、所述低介电常数材料层及所述铜层图案化,以提供经激光划线的聚合物掩模,所述聚合物掩模具有多个划线,每个划线具有宽度,所述划线曝露所述集成电路之间的所述半导体晶圆的多个区域;以及
在所述半导体晶圆中以等离子体蚀刻方式蚀刻出多个沟道,以单片化所述集成电路,每个沟道具有所述宽度。
9.如权利要求8所述的方法,其特征在于,用所述基于飞秒的激光划线工艺将所述二氧化硅层、所述低介电常数材料层及所述铜层图案化的步骤包括以下步骤:在切除所述低介电常数材料层及所述铜层之前切除所述二氧化硅层。
10.如权利要求8所述的方法,其特征在于,用所述基于飞秒的激光划线工艺图案化的步骤进一步包括在所述集成电路之间的所述硅衬底的所述区域中形成多个经激光刻划的沟道,且其中在所述半导体晶圆中以等离子体蚀刻方式蚀刻出多个沟道的步骤包括延伸所述多个经激光刻划的沟道以单片化所述集成电路。
11.如权利要求8所述的方法,其特征在于,用所述基于飞秒的激光划线工艺图案化的步骤包括以下步骤:使用一激光,所述激光具有约小于或等于530纳米的波长,且所述激光具有约小于或等于400飞秒的激光脉冲宽度。
12.如权利要求8所述的方法,其特征在于,等离子体蚀刻所述硅衬底的步骤包括以下步骤:使用高密度穿硅等离子体蚀刻工艺。
13.如权利要求8所述的方法,其特征在于,所述集成电路由多个切割道分隔,所述切割道具有约10微米或更小的宽度。
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