CN102150253A - 自对准沟槽的形成方法 - Google Patents
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- 230000015572 biosynthetic process Effects 0.000 title claims description 12
- 239000000463 material Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 75
- 238000005530 etching Methods 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000945 filler Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000011049 filling Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 36
- 230000010354 integration Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 74
- 238000005516 engineering process Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 description 2
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910021386 carbon form Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract
本发明涉及半导体装置的形成方法,其包含形成自对准沟槽,其中使用第一组沟槽(300)来对准第二组沟槽(302)。本文所教示的方法可用作间距加倍技术,且因此可提高装置整合度。另外,通过使用极薄CMP终止层(211)并使周围材料凹陷与所述CMP终止层(211)的厚度大致相等的量可在所述装置的表面上提供改善的平坦性。
Description
技术领域
本发明实施例涉及半导体结构的形成方法,更具体来说涉及在半导体处理中形成自对准沟槽的方法。
背景技术
集成电路设计者制造更快更小集成电路的一种方式是降低包括集成电路的各元件间的分隔距离。此增加衬底上电路元件密度的方法通常称作“缩放”或增加装置整合度。在设计整合度较高的集成电路的方法中,人们研发出经改善的装置构造及制造方法。
发明内容
本发明揭示包含自对准沟槽的半导体结构的制造技术。自对准沟槽可用作间距加倍技术的一部分,其可提高装置整合度。有利的是,本文所述的制造技术使得能够更精确地蚀刻、将对衬底的应力降至最低和/或提高半导体结构表面的平坦性。
附图说明
本文所揭示的本发明的实例性实施例阐释于附图中,其并非按比例绘出而是仅用于阐释目的:
图1显示部分形成的半导体装置的剖视图。
图2显示使用光掩模图案化硬掩模后图1中部分形成半导体装置的剖视图。
图3显示使用硬掩模图案化第二硬掩模后图2中部分形成半导体装置的剖视图。
图4显示使某些层图案化并在所述层上形成间隔层后图3中部分形成半导体装置的剖视图。
图5显示在衬底中蚀刻出第一组沟槽后图4中部分形成半导体装置的剖视图。
图6显示填充沟槽后图5中部分形成半导体装置的剖视图。
图7显示平坦化后图6中部分形成半导体装置的剖视图。
图8显示在经填充沟槽之间选择性蚀刻占位层并沉积间隔层材料后图7中部分形成半导体装置的剖视图。
图9显示执行间隔层蚀刻并随后以自对准方式在衬底中选择性蚀刻出第二组沟槽后图8中部分形成半导体装置的剖视图。
图10显示填充第二组沟槽后图9中部分形成半导体装置的剖视图。
图11显示在蚀刻终止层上终止平坦化后图10中部分形成半导体装置的剖视图。
图12显示使表面的多个部分选择性凹陷后图11中部分形成半导体装置的详细剖视图。
图13显示去除蚀刻终止层后图12中部分形成半导体装置的详细剖视图。
图14展示图13半导体装置的俯视图。
具体实施方式
图1是部分形成的包含衬底110的半导体装置的剖视图,在衬底上形成有若干额外层以有助于掩模工艺。衬底110包括适用于半导体处理的各种工件中的一者或多者。在一些实施例中,衬底110包含在衬底上制造的半导体结构,例如掺杂硅平台。尽管所示衬底110包括单晶硅晶片,但在其它实施例中,衬底110包括其它形式的半导体层,所述半导体层任选地包含半导体装置的其它有源部分或可操作部分。衬底在本文中还用于指代包含形成于衬底上的集成层的工件。
如图1中所示,在一些实施例中,衬底110上生长或沉积有氧化物层210。氧化物层210可包括厚度介于约与之间的薄垫氧化物。可使用适宜沉积方法(例如化学蒸气沉积(“CVD”)或物理蒸气沉积(“PVD”))来沉积氧化物层210,或可通过下伏表面的氧化来生长氧化物层。
图1的部分形成的半导体装置还展示蚀刻终止层211,其是通过例如CVD或PVD等适宜沉积方法在氧化物层210上形成。蚀刻终止层211用作后续平坦化步骤的终止层(例如,CMP终止层),如下文所述。相对于常规CMP终止层,蚀刻终止层211可以极薄,例如,厚度可介于约与之间、更具体来说介于约与之间。从下文所述可以了解,此薄蚀刻终止层可提高平坦性以便于随后的处理。在一些实施例中,蚀刻终止层211包括氮化物,例如氮化硅(“Si3N4”)。在其它实施例中,蚀刻终止层211包括氧化铝(“Al2O3”)或另一材料,可通过化学和/或机械蚀刻工艺来选择性地蚀刻其相邻材料(尤其为氧化硅)。
如图1中所示,一些实施例还提供在蚀刻终止层211上形成的占位材料212。优选地,占位材料212的厚度可足以提供在下文所述的后续步骤中形成间隔层材料的空间。因此,占位材料212可具有适于随后界定侧壁间隔层高度的厚度,例如介于约到之间、更具体来说介于到之间。在所示实施例中,占位材料212包括多晶硅,但也可使用可相对于周围材料、且尤其相对于沟槽隔离材料进行选择性蚀刻的其它材料。
根据本发明实施例,提供硬掩模来蚀刻第一组沟槽。在图1中所示的实施例中,提供两个硬掩模层213、214,第一硬掩模层214用于图案化第二硬掩模层213,且经由用作掩模的第二硬掩模层213来蚀刻第一组沟槽。在下文中将更详细地阐述此实施例,这是因为此布置提供了某些性能优点,例如蚀刻第一组沟槽的纵横比得以改善。然而,仅使用单一硬掩模来蚀刻第一组沟槽的其它实施例也是可能的,例如通过使用光掩模来蚀刻碳质硬掩模且然后经由所述碳质硬掩模来蚀刻沟槽。在其它实施例中,根本不使用硬掩模,且代之以仅使用光掩模来形成第一组沟槽。
再次参照图1中所示的实施例,通过任一适宜沉积方法(例如CVD或PVD)在占位材料212上形成第二硬掩模层213。第二硬掩模层213可包括例如原硅酸四乙酯(“TEOS”)等氧化硅形式,且其厚度可介于约到之间、更具体来说介于到之间。第一硬掩模层214可包括碳,例如不定型碳。具体来说,不定型碳可呈对光高度透明的透明碳形式,例如A.海布(A.Helmbold),D.迈斯纳(D.Meissner),固体薄膜(Thin Solid Films),283(1996),196-203中所揭示者,其全部揭示内容以引用方式并入本文中。第一硬掩模层214的厚度可介于约到之间、更具体来说介于到之间。因此,第二硬掩模213的厚度相对于第一硬掩模214的厚度的百分比小于100%、更具体来说为30-70%、甚至更具体来说为40-60%。在蚀刻第一组沟槽时,与直接使用第一硬掩模214相比,相对于第一硬掩模层214减小第二硬掩模层213的厚度可有利地提供较低纵横比。
如图1中所示,一些实施例还提供形成于第一硬掩模214上的涂层215、216。电介质抗反射涂层(“DARC”)215可有利地保护第一硬掩模214。DARC 215可包括富硅材料,例如氮氧化硅(“SixOyNz”)。有机底部抗反射涂层(“BARC”)216的介面上还可包含有光阻剂218。
图1中所示的光阻剂218提供图案以经由光刻和蚀刻技术去除第一硬掩模214的若干部分。在一些实施例中,如图1中所示,光阻剂218提供由间隙彼此分隔的平行线图案(示于图1中的横截面中;也可参见图13)。在一些实施例中,例如在期望装置整合度较高时,线与线间间隙的宽度可大约等于“F”,其中F可为使用特定光刻技术可形成的最小特征尺寸。然而,通常来说,在图中使用“F”来代表相对尺寸。所属领域技术人员应了解,在F大于最小分辨率时也可实施本文所述的方法。其它实施例可使用界定其它图案的光阻剂218,进而在后续步骤中产生了不同的沟槽构造。在一实例性实施例中,通过以下步骤形成光阻剂218:在光敏材料上实施旋涂,经由含有期望图案的掩模将光敏材料暴露于光中,且然后使所述材料显影成为光阻剂218。随后,可经由光阻剂218中的间隙来蚀刻第一硬掩模214。对第一硬掩模214实施光刻及蚀刻后,可剥除光阻剂218,或可在第一硬掩模214的蚀刻期间去除光阻剂,由此产生图2中所示的部分形成的半导体装置。
在图2中,已使用线和间隙交替的图案蚀刻第一硬掩模214。如上所述,在一些实施例中,可经由第一硬掩模214在衬底中蚀刻出第一组沟槽。然而,在图2-3中所示的实施例中,经由较厚的第一硬掩模214蚀刻相对较薄的第二硬掩模213,且然后去除第一硬掩模214。此工艺产生了图3中所示的部分形成的半导体装置,其中已将第二硬掩模213图案化。
参照图4,第二硬掩模213的图案已转移(例如,经由选择性湿法蚀刻)到占位材料212上。沿占位材料212与第二硬掩模213的侧壁可形成上侧壁间隔层217。上侧壁间隔层217可通过以下步骤形成:将均匀厚氧化硅(例如与第二硬掩模213中相同的材料)保形沉积至上表面和侧壁表面上,且然后定向蚀刻所沉积的氧化物以便优先去除水平表面,但在期望位置保留上侧壁间隔层217。在一些实施例中,上侧壁间隔层217具有大约1/4F的厚度,此可在上侧壁间隔层217之间提供大约1/2F的间隙。所述构造可有利地提供两组一致的沟槽,其宽度大致相等且由大致相等的距离分隔,如下文所述。
参照图5,已经由第二硬掩模213和上侧壁间隔层217在衬底110中蚀刻出第一组沟槽300。蚀刻工艺可为选择性蚀刻工艺,其优先蚀刻形成沟槽时欲去除的材料(例如硅),而并不蚀刻第二硬掩模213和间隔层217的材料(例如TEOS或其它基于氧化硅的材料)。所属领域技术人员应了解,例如在层间电介质(“ILD”)中形成镶嵌沟槽时,可使用其它硬掩模材料及其它选择性蚀刻化学品。因此,图5显示,在形成第一组沟槽300后第二硬掩模213仍保留在适当位置。然而,所属领域技术人员应认识到,选择性蚀刻可能并不完美,因此在第一组沟槽300的蚀刻工艺中会消除第二硬掩模213的全部或一部分。
在一些实施例中,第一组沟槽300由一系列沟槽间区域301分隔,随后在301中可形成第二组沟槽。在一些实施例中,沟槽间区域301的宽度可大约等于1.5F。因此,在图5中所示的实施例中,在形成第一组沟槽300后,沟槽宽度大约等于1/2F,上侧壁间隔层217的宽度大约等于1/4F,且包含上侧壁间隔层217的沟槽间区域301的宽度大约等于1.5F。
第一组沟槽300具有深度“D1”,所述深度定义为在第一组沟槽300的蚀刻步骤后立即测量的从沟槽间区域301中的衬底110顶部到沟槽300的底部硅的距离。在一些实施例中,D1介于约与之间、更具体来说介于到之间。
第一组沟槽300也具有由沟槽深度“D2”(在此情形下包含掩模层)与沟槽顶部处的沟槽宽度的比率所定义的纵横比。深度D2定义为在第一组沟槽300的蚀刻步骤后立即测量的从沟槽间区域301中的顶部表面到沟槽300底部的距离。由于上述原因,在第一组沟槽的蚀刻步骤后立即测量,沟槽间区域301的顶部表面可位于第二硬掩模213顶部处(如图5中所示)或位于占位材料212顶部处。在一些实施例中,纵横比介于约5∶1与100∶1之间、更具体来说介于约10∶1与25∶1之间。
形成第一组沟槽300后,可填充沟槽。在一些实施例中,沟槽300可内衬有一个或一个以上衬层。举例来说,在图6中所示的实施例中,在沟槽中以及沟槽间区域301表面上生长厚度介于约到之间的薄氧化物层220。氧化物层220可有利地修复沟槽300壁的蚀刻损坏。图6还展示厚度介于约到之间的氮化物层221,所述氮化物层作为障壁层沉积于氧化物层220上以促进后续的氧化物致密化。厚度介于约到之间的TEOS层223可任选地形成于氮化物层221上,其可在SOD致密化期间提供扩散路径以使氧化剂的分布更均匀。然后使用例如电隔离材料等填充剂材料225来填充沟槽300。在一实例性实施例中,填充剂材料225包括旋涂电介质。如图6中所示,填充步骤可包含过填充沟槽300,以便填充剂材料225延伸至沟槽300顶部上方。
图7显示对表面实施平坦化后图6中部分形成的半导体装置的剖视图。平坦化工艺可包括化学机械抛光工艺。如图7中所示,平坦化步骤可终止于占位材料212上,以便在平坦化步骤后,部分形成的装置的表面在沟槽300中包括填充剂材料225且在沟槽间区域301中包括暴露的占位材料212。
接下来,可去除上侧壁间隔层217(如果其在早期工艺中未被去除),且可从沟槽间区域301中选择性蚀刻占位材料212,由此产生部分形成的装置,其中沟槽300中的填充剂材料225突出至沟槽间区域301的表面上方。在一些实施例中,可在各向同性湿法蚀刻中使用TMAH从沟槽间区域301选择性去除占位材料212。然后可毯覆沉积第二间隔层材料230(例如TEOS)以贴合装置表面,如图8中所示。
然后可使用定向间隔层蚀刻优先从水平表面蚀刻间隔层材料230。定向间隔层蚀刻在大致垂直表面上的适当位置留下了呈侧壁间隔层形式的第二间隔层材料230,例如沟槽300上方的填充剂材料部分的侧壁,其突出至沟槽间区域301的表面上方。然后第二间隔层材料230的这些剩余部分可用于对准沟槽间区域301内由间隔层与第一沟槽300间隔的第二组沟槽302。在一些实施例中,在优先蚀刻第二间隔层材料230后,间隔层材料可具有大约等于1/2F的厚度。所述实施例可提供大致一致的第一和第二组沟槽的宽度以及大致一致的第一与第二组沟槽间的间隔或间隙。
图9展示在衬底110中蚀刻出第二组沟槽302后部分形成的半导体装置的剖视图。图8展示第一沟槽300比第二沟槽302深的实施例,但其它构造也是可能的:第二组可比第一组深、或第一组与第二组可具有大致相同的深度。如上所述,实施例可提供间距加倍技术,其中第一组300中的沟槽与第二组302中的沟槽的间距小于距离F(例如,大约1/2F)。
图10展示已填充第二沟槽302后的部分形成的半导体装置。第二沟槽302可内衬有氧化物衬层310,例如生长到厚度介于约与之间的氧化物。如图10中所示,然后可使用第二填充剂材料312(例如使用高密度等离子体(“HDP”)氧化物)过填充沟槽302使其延伸至沟槽302顶部上方。应注意,尽管在所示实施例中通过不同技术和实施例填充所示沟槽300、302,但所述两组沟槽均是通过在选择性蚀刻方面化学上相似的氧化硅形式来填充。
填充沟槽302后,然后可对部分形成的装置实施平坦化。可使用化学机械抛光(“CMP”)工艺来实施平坦化,且其可止于蚀刻终止层211上。通常很难以足够高的精确度控制平坦化工艺止于薄蚀刻终止层211顶部表面上,从而造成在CMP工艺结束时消耗了所示薄蚀刻终止层211的大部分厚度。通常在终止CMP工艺的过程中消耗约到的蚀刻终止层211,此可代表约50%到80%的蚀刻终止层211厚度。实施此平坦化步骤后部分形成的装置的剖视图示于图11中。
在一些实施例中,平坦化步骤后的装置表面可主要包括蚀刻终止层211和结构材料(例如氧化硅)。然后可通过(例如)选择性蚀刻蚀刻终止层氮化物的相邻氧化物来使结构材料选择性凹陷到与蚀刻终止层的下表面大致共面。
图12显示结构材料选择性凹陷后装置表面的详图。结构材料(示为氧化物)的凹陷量优选地约等于剩余蚀刻终止层211的厚度。在所示实施例中,结构材料凹陷约到更具体来说到因此,凹陷结构材料的上表面与蚀刻终止层211的下表面大致共面(例如,内,更具体来说内)。如图12中所示,装置的其它部分(例如氮化物衬层221)可突出至沿蚀刻终止层211选择性凹陷的部分的上方。
接下来,可通过(例如)选择性蚀刻氮化物来去除蚀刻终止层211。所述蚀刻步骤也可去除突出至结构材料表面上的其它部分,例如氮化物衬层221。本发明者观察到所述工艺可增加装置表面的平坦性。图13显示了这些步骤后半导体装置的详图。
图11及14显示填充有隔离材料的平行沟槽,其是根据本文所述方法制得。在一实施例中,深沟槽300代表阵列(例如,例如DRAM等存储器阵列)中晶体管之间的浅沟槽隔离。这些较深沟槽与平行浅沟槽302交替出现。从2006年3月2日公开的美国专利申请案第2006-0046407号(其揭示内容以引用方式并入本文中)的工艺流程可以了解,这些浅沟槽302可代表U型突出晶体管结构中源极柱与漏极柱之间的间隙,且可保留填充有绝缘材料或在“3面”沟道结构中可使用栅极电介质和栅极电极材料来替代。如所纳入的‘407公开案中所述,随后的中等深度的交叉沟槽可在晶体管行之间提供间隙,其中可围绕U型半导体结构在至少两侧形成栅极电极材料。在其它实施例中,沟槽可用于深DRAM电容器中;均可用于沟槽隔离中且可具有大约相等的深度;可在绝缘材料中用作镶嵌沟槽以供随后使用金属线来填充;等等。
已阐述各种方法来为半导体结构的形成提供若干优点。举例来说,已教示各种使用占位材料作为在衬底中形成自对准沟槽的一部分的方法。自对准沟槽可用作间距加倍技术的一部分,其可提高装置整合度。举例来说,在所示实施例中,部分形成的装置的间距在图1到图7中所示的阶段为2F,但间距在图13中所示的阶段为F;特征尺寸从图1阶段的F缩减到图13阶段的1/2F。有利的是,本文所述的制造技术通过(例如)使用相对薄的第二硬掩模来改善沟槽蚀刻期间的纵横比而使得能够更精确地进行蚀刻。另外,本文所揭示的方法通过(例如)提供相对薄的蚀刻终止层及使周围材料凹陷与在CMP步骤期间消耗后蚀刻终止层的剩余量大约相等的量的步骤序列来提高半导体结构的表面的平坦性。
根据一个实施例,提供形成装置的方法。所述方法包括在衬底上形成多晶硅层及在衬底中形成第一组沟槽,其中所述多晶硅层的剩余部分保留于衬底上在第一组的沟槽间的沟槽间区域中。所述方法进一步包括使用填充剂材料填充第一组沟槽,其中所述填充剂材料向上至少延伸到毗邻多晶硅层的剩余部分的水平。另外,所述方法包括从沟槽间区域选择性蚀刻多晶硅层的剩余部分,在沟槽间区域中的填充剂材料的侧壁上形成间隔层,及在衬底中于间隔层之间蚀刻出第二组沟槽。
在另一实施例中,提供在衬底上形成装置的方法。所述方法包括在衬底上形成蚀刻终止层及经由蚀刻终止层和衬底蚀刻多个第一沟槽。所述方法进一步包括使用隔离材料填充第一沟槽并使其突出至衬底上方,在隔离材料的突出部分的侧壁上形成间隔层,及在间隔层之间蚀刻多个第二沟槽。所述方法进一步包括使用第二填充剂材料填充第二沟槽,对第二填充剂材料实施平坦化及在蚀刻终止层上终止平坦化。
在另一实施例中,提供形成集成电路的方法。所述方法包括在衬底上形成结构,所述结构包括结构材料和蚀刻终止层,所述蚀刻终止层具有上表面和下表面。所述方法进一步包括对所述结构实施平坦化及在蚀刻终止层上终止平坦化。所述方法进一步包括选择性地使结构材料凹陷到与蚀刻终止层的下表面大致共面,及选择性去除蚀刻终止层。
所属领域技术人员应了解,可对上述方法和结构作出各种其它省略、添加及修改,此并不背离本发明的范围。举例来说,尽管所示实施例涉及在半导体材料中蚀刻交替“浅”沟槽隔离(“STI”)及使用电绝缘隔离材料进行填充,但所属领域技术人员应了解,本文所教示的原则及优点可应用于其它背景中。举例来说,本文所教示的一些方法可用于界定使用金属线填充的紧密相间的自对准镶嵌沟槽。所有所述改变均意欲属于本发明的范围内,如随附权利要求所界定。
Claims (32)
1.一种形成装置的方法,所述方法包括:
在衬底上形成多晶硅层;
在所述衬底中形成第一组沟槽,其中所述多晶硅层的剩余部分保留于所述衬底上在所述第一组的沟槽间的沟槽间区域中;
使用填充剂材料填充所述第一组沟槽,其中所述填充剂材料向上至少延伸到毗邻所述多晶硅层的所述剩余部分的水平;
从所述沟槽间区域选择性蚀刻所述多晶硅层的所述剩余部分;
在所述沟槽间区域中的所述填充剂材料的侧壁上形成间隔层;及
在所述衬底中在所述间隔层间蚀刻出第二组沟槽。
2.根据权利要求1所述的方法,其进一步包括在填充后对所述衬底上的所述填充剂材料实施平坦化以暴露所述沟槽间区域中的所述多晶硅层的所述剩余部分,然后选择性蚀刻所述多晶硅层的所述剩余部分。
4.根据权利要求1所述的方法,其中蚀刻所述第二组沟槽包括蚀刻与所述第一组沟槽实质上平行的第二组沟槽。
5.根据权利要求4所述的方法,其中蚀刻所述第二组沟槽包括以小于F的宽度分隔所述第一组沟槽中的沟槽与所述第二组沟槽中的沟槽,其中F为使用光刻技术可形成的最小特征尺寸。
6.根据权利要求5所述的方法,其中在蚀刻所述第二组沟槽后,所述第一和第二组沟槽中的所述沟槽间距大致一致且具有大致一致的宽度。
7.根据权利要求5所述的方法,其中所述第一组中的所述沟槽的深度大于所述第二组的深度。
8.根据权利要求1所述的方法,其中形成第一组沟槽包括经由硬掩模层在所述多晶硅层上蚀刻所述第一组沟槽。
9.根据权利要求8所述的方法,其中所述硬掩模层包括原硅酸四乙酯(“TEOS”)。
10.根据权利要求8所述的方法,其进一步包括在蚀刻所述第一组沟槽之前在所述硬掩模层的至少一部分侧壁上形成间隔层。
12.根据权利要求8所述的方法,其中所述第一组沟槽的纵横比介于约5∶1与100∶1之间,其中所述纵横比为所述第一组沟槽的深度与所述第一组的沟槽的宽度的比率,其中深度是从所述沟槽间区域的所述顶部表面到所述第一组沟槽的所述底部计算的。
13.根据权利要求8所述的方法,其进一步包括使用碳质硬掩模图案化所述硬掩模层并去除所述碳质硬掩模,然后蚀刻所述第一组沟槽。
16.根据权利要求1所述的方法,其进一步包括在所述多晶硅层下方形成蚀刻终止层,且在蚀刻所述第二组沟槽后使用第二填充剂材料填充所述第二组沟槽并对所述第二填充剂材料实施平坦化,其中所述第二填充剂材料的平坦化包括在所述蚀刻终止层上终止。
17.一种在衬底上形成装置的方法,其包括:
在所述衬底上形成蚀刻终止层;
经由所述蚀刻终止层和所述衬底蚀刻多个第一一沟槽;
使用隔离材料填充所述第一沟槽并使其突出至所述衬底上方;
在所述隔离材料的突出部分的侧壁上形成间隔层;
在所述间隔层之间蚀刻多个第二沟槽;
使用第二填充剂材料填充所述第二沟槽;及
对所述第二填充剂材料实施平坦化并在所述蚀刻终止层上终止平坦化。
19.根据权利要求17所述的方法,其中平坦化包括化学机械平坦化。
20.根据权利要求17所述的方法,其中形成蚀刻终止层包括形成氮化硅蚀刻终止层。
21.根据权利要求17所述的方法,其中形成蚀刻终止层包括形成氧化铝蚀刻终止层。
22.根据权利要求17所述的方法,其中使用隔离材料填充所述第一沟槽并使其突出至所述衬底上方包括:
使用隔离材料过填充所述沟槽;
对所述隔离材料实施平坦化以暴露位于所述第一沟槽的侧壁间在所述隔离材料下方的占位材料;
选择性蚀刻位于所述第一沟槽的侧壁之间的所述占位材料。
23.根据权利要求22所述的方法,其中使用隔离材料过填充所述沟槽包括使用旋涂电介质过填充所述沟槽。
24.根据权利要求22所述的方法,其中填充所述第一沟槽中的每一者进一步包括使所述沟槽内衬有至少一个衬层。
25.根据权利要求17所述的方法,其中蚀刻多个第二沟槽包括以小于F的宽度间隔所述第二沟槽与所述第一沟槽,其中F为使用光刻技术可形成的最小特征尺寸。
26.根据权利要求17所述的方法,其中蚀刻多个第二沟槽包括将所述第二沟槽蚀刻到小于所述第一沟槽的深度的深度。
27.一种形成集成电路的方法,其包括:
在衬底上形成结构,所述结构包括结构材料和蚀刻终止层,所述蚀刻终止层具有上表面和下表面;
对所述结构实施平坦化并在所述蚀刻终止层上终止平坦化;
使所述结构材料选择性凹陷到与所述蚀刻终止层的所述下表面大致共面;及
选择性去除所述蚀刻终止层。
28.根据权利要求27所述的方法,其中所述结构材料包括氧化硅形式。
29.根据权利要求27所述的方法,其中所述蚀刻终止层包括氮化物。
30.根据权利要求29所述的方法,其中所述蚀刻终止层包括Si3N4。
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US20130113069A1 (en) | 2013-05-09 |
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US8685859B2 (en) | 2014-04-01 |
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US8101497B2 (en) | 2012-01-24 |
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US8552526B2 (en) | 2013-10-08 |
US8343875B2 (en) | 2013-01-01 |
US20120108069A1 (en) | 2012-05-03 |
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