CN102130164A - Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) - Google Patents

Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) Download PDF

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Publication number
CN102130164A
CN102130164A CN2010100272898A CN201010027289A CN102130164A CN 102130164 A CN102130164 A CN 102130164A CN 2010100272898 A CN2010100272898 A CN 2010100272898A CN 201010027289 A CN201010027289 A CN 201010027289A CN 102130164 A CN102130164 A CN 102130164A
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China
Prior art keywords
ldmos
buried layer
type
trap
buried
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CN2010100272898A
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Chinese (zh)
Inventor
张帅
遇寒
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Priority to CN2010100272898A priority Critical patent/CN102130164A/en
Publication of CN102130164A publication Critical patent/CN102130164A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a buried layer of an LDMOS (laterally diffused metal-oxide semiconductor), wherein a plurality of buried layer structures (11a) are arranged between a substrate (10) and an epitaxial layer (13), and the buried layer structures (11a) are mutually spaced in the horizontal direction. The traditional LDMOS is changed from a whole buried layer (11) to a plurality of the buried layer structures (11a) which are mutually spaced, the buried layer structures can still maintain the effect of an isolation device, and also can be used for reducing a surface electric field of a drift region and further improving the breakdown voltage of the LDMOS device. Furthermore, the on-resistance of the LDMOS device is not increased, the existing BCD (bistable cholesteric display) process is not changed, and impacts on other bipolar devices and CMOS (complementary metal oxide semiconductor) devices can be further avoided.

Description

The buried regions of LDMOS
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of LDMOS (laterally diffused MOS, laterally diffused MOS transistor) device.
Background technology
See also Fig. 1, this is the generalized section of the existing n type LDMOS that makes with BCD (Bipolar, CMOS, DMOS) technology.Having n type buried regions 11 and p type buried regions 12 on p type substrate 10, up then is n type epitaxial loayer 13 again.A plurality of isolated areas 14 are arranged in the n type epitaxial loayer 13, and these isolated areas 14 are isolated the high pressure p trap 151 in the n type epitaxial loayer 13, high pressure n trap 152, high pressure p trap 153, high pressure n trap 154, high pressure p trap 155 mutually.
Has low pressure p trap 161 in the high pressure p trap 151.Has low pressure n trap 162 in the high pressure n trap 152, as the drain electrode of LDMOS device.Has low pressure p trap 163 in the high pressure p trap 153.Has low pressure n trap 164 in the high pressure n trap 154.Has low pressure p trap 165 in the middle of the high pressure p trap 155.
Has p type heavily doped region 171 in the low pressure p trap 161.Has n type heavily doped region 172 in the low pressure n trap 162, as the drain electrode of LDMOS device.Have p type heavily doped region 173 and n type heavily doped region 174 in the low pressure p trap 163, isolated by isolation structure 14 between the two.P type heavily doped region 173 is as the body electrode (body) of LDMOS device.N type heavily doped region 174 source electrodes as the LDMOS device.Has n type heavily doped region 175 in the low pressure n trap 164, as the drain electrode of LDMOS device.Has p type heavily doped region 176 in the low pressure p trap 165.
Described n type heavily doped region 172,175 is same loop configuration on domain, therefore with the conduct drain electrode.
Having gate oxide 18 on the n type epitaxial loayer 13, up is grid 19, as the grid of LDMOS device again.Being surrounded by medium around the grid 19 and become floating boom.The below of grid 19 comprises isolated area 14, n type epitaxial loayer 13 and 163 3 parts of low pressure p trap.
Among the said n type LDMOS, the doping type of each several part structure being become on the contrary, promptly become p type LDMOS, also is feasible.
Among the LDMOS shown in Figure 1, n type buried regions 11 and p type buried regions 12 are to adopt ion implantation technology to form in p type substrate 10 and n type epitaxial loayer 13, and these two buried regions both had been used for doing isolation, also are used for reducing the conducting resistance of LDMOS device.Wherein have immovable positive charge on the n type buried regions 11, these positive charges can form on grid 19 surface one with drift region (being n type epitaxial loayer 13 and the high pressure n trap 154) electric field that the surface field direction is consistent, the stack of this electric field and drift region surface field can cause drift region surface field intensity to increase, thereby makes that the LDMOS device is easy to puncture ahead of time on the surface, drift region.
Summary of the invention
Technical problem to be solved by this invention provides the buried structure of a kind of LDMOS, can improve the puncture voltage of LDMOS device.
For solving the problems of the technologies described above, the buried regions of LDMOS of the present invention has a plurality of buried structures (11a) between substrate (10) and epitaxial loayer (13), and these buried structures (11a) are the space in the horizontal direction.
The present invention is the buried structure (11a) that one buried regions (11) becomes the polylith space with traditional LDMOS whole, these buried structures have still kept the effect of isolating device, can reduce the drift region surface field again, thereby improve the puncture voltage of LDMOS device.And the present invention does not increase the conducting resistance of LDMOS device, does not make change for existing BCD technology yet, thus can bipolar (Bipolar) device to other and cmos device impact.
Description of drawings
Fig. 1 is the generalized section of existing LDMOS;
Fig. 2 is the generalized section of LDMOS of the present invention.
Description of reference numerals among the figure:
10 is p type substrate; 11 is n type buried regions; 11a is a n type buried structure; 12 is p type buried regions; 13 is n type epitaxial loayer; 14 is isolation structure; 151,153,155 is high pressure p trap; 152,154 is high pressure n trap; 161,163,165 is low pressure p trap; 162,164 is low pressure n trap; 171,173,176 is n type heavily doped region; 172,174,175 is p type heavily doped region; 18 is gate oxide; 19 is grid.
Embodiment
See also Fig. 2, the difference of LDMOS device of the present invention and traditional LDMOS device is: having a plurality of n type buried structure 11a and p type buried regions 12 on p type substrate 10, up then is n type epitaxial loayer 13 again.Wherein a plurality of n type buried structure 11a separate in the horizontal direction mutually, and to have replaced existing integral body be one n type buried regions 11.
The quantity of these buried structures 11a and spacing with ion inject, and annealed diffusion after still can play the effect of isolating p type substrate 10 and n type epitaxial loayer 13 and be as the criterion.Can be the spacing that equates between these buried structures 11a, also can be the spacing that does not wait.
If p type LDMOS, then the doping type of each several part structure becomes on the contrary among Fig. 2; Being to have a plurality of p type buried structures between the n type substrate p type epitaxial loayer, also is feasible.
For the LDMOS device, improve breakdown potential and be pressed with following several approach:
One, the length of increase device drift region; But this can increase conducting resistance, also can increase the area of LDMOS device.
Its two, the concentration of regulating high pressure p trap and high pressure n trap; But this can influence the performance of bipolar device and cmos device.BCD technology is to make bipolar device, cmos device and DMOS device on same chip, needs to guarantee that these three kinds of devices all have superperformance.
Its three, the n type buried regions of removing among Fig. 1 11 reduces the drift region surface field, but this causes the conducting resistance of LDMOS device significantly to increase, and can not be to isolating between p type substrate 10 and the n type epitaxial loayer 13.
The present invention is divided into the polylith buried structure with original buried regions dexterously, still can play the isolation effect between substrate and the epitaxial loayer on the one hand well, has reduced the drift region surface field on the other hand again, has improved the puncture voltage of LDMOS device.Particularly, a plurality of buried structures are with respect to whole one n type buried regions, and its doping content reduces, and the positive charge that provides weakens at the formed electric field of gate surface, and it is breakdown to make that the surface, drift region is not easy, and has protected gate oxide, has also improved puncture voltage.By the TCAD software simulation, the present invention can improve 3V with puncture voltage with respect to traditional LDMOS device.The present invention has also taken into account the performance of BJT (bipolar device) and cmos device, does not also increase the LDMOS size of devices, has also kept the lower conducting resistance of LDMOS device.
On manufacture method, compare with the manufacturing process of original LDMOS, the present invention has adjusted the zone that ion injects, an original whole ion implanted region territory is changed into the ion implanted region territory of a plurality of mutual separations, still kept BCD technology not do change, therefore can other BJT (bipolar device) and cmos device do not impacted.

Claims (4)

1. the buried regions of a LDMOS is characterized in that, has a plurality of buried structures (11a) between substrate (10) and epitaxial loayer (13), and these buried structures (11a) are the space in the horizontal direction.
2. the buried regions of LDMOS according to claim 1 is characterized in that, described substrate (10) is the p type, and epitaxial loayer (13) and buried structure (11a) are the n type.
3. the buried regions of LDMOS according to claim 1 is characterized in that, described substrate (10) is the n type, and epitaxial loayer (13) and buried structure (11a) are the p type.
4. the buried regions of LDMOS according to claim 1 is characterized in that, the spacing between described a plurality of buried structures (11a) equates.
CN2010100272898A 2010-01-18 2010-01-18 Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) Pending CN102130164A (en)

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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102901524A (en) * 2011-07-28 2013-01-30 上海腾怡半导体有限公司 Low-noise low-offset voltage hall sensor
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method
CN103035525A (en) * 2011-10-10 2013-04-10 上海华虹Nec电子有限公司 Manufacturing method of high voltage isolating N type laterally diffused metal oxide semiconductor (LDMOS) component
CN103745988A (en) * 2014-01-07 2014-04-23 无锡芯朋微电子股份有限公司 Isolation structure of high-voltage driving circuit
CN103840008A (en) * 2014-03-31 2014-06-04 成都立芯微电子科技有限公司 High-voltage LDMOS device based on BCD process and manufacturing process
CN104518023A (en) * 2013-09-30 2015-04-15 无锡华润上华半导体有限公司 High-voltage LDMOS (laterally-diffused metal oxide semiconductor) device
CN104681621A (en) * 2015-02-15 2015-06-03 上海华虹宏力半导体制造有限公司 High-voltage LDMOS for source electrode rising voltage use and manufacturing method for high-voltage LDMOS
CN104701372A (en) * 2013-12-06 2015-06-10 无锡华润上华半导体有限公司 LDMOS (lateral diffusion metallic oxide conductor) device and production method thereof
CN104821334A (en) * 2015-03-11 2015-08-05 上海华虹宏力半导体制造有限公司 N-type LDMOS device and process method thereof
CN105140303A (en) * 2014-05-30 2015-12-09 无锡华润上华半导体有限公司 Junction field effect transistor and preparation method thereof
CN107887436A (en) * 2016-09-30 2018-04-06 上海华虹宏力半导体制造有限公司 PLDMOS structures and its manufacture method
US9997626B2 (en) 2015-05-25 2018-06-12 Shanghai Huahong Grace Semiconductor Manufacturing Corporation NLDMOS device and method for manufacturing the same
CN110120414A (en) * 2018-02-07 2019-08-13 联华电子股份有限公司 Transistor arrangement

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102901524A (en) * 2011-07-28 2013-01-30 上海腾怡半导体有限公司 Low-noise low-offset voltage hall sensor
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method
CN103035525B (en) * 2011-10-10 2015-06-03 上海华虹宏力半导体制造有限公司 Manufacturing method of high voltage isolating N type laterally diffused metal oxide semiconductor (LDMOS) component
CN103035525A (en) * 2011-10-10 2013-04-10 上海华虹Nec电子有限公司 Manufacturing method of high voltage isolating N type laterally diffused metal oxide semiconductor (LDMOS) component
CN104518023B (en) * 2013-09-30 2017-12-15 无锡华润上华科技有限公司 high-voltage LDMOS device
CN104518023A (en) * 2013-09-30 2015-04-15 无锡华润上华半导体有限公司 High-voltage LDMOS (laterally-diffused metal oxide semiconductor) device
CN104701372B (en) * 2013-12-06 2017-10-27 无锡华润上华科技有限公司 Transverse diffusion metal oxide semiconductor device and its manufacture method
CN104701372A (en) * 2013-12-06 2015-06-10 无锡华润上华半导体有限公司 LDMOS (lateral diffusion metallic oxide conductor) device and production method thereof
US20160240659A1 (en) * 2013-12-06 2016-08-18 Csmc Technologies Fab1 Co., Ltd. Laterally diffused metal oxide semiconductor device and manufacturing method therefor
CN103745988B (en) * 2014-01-07 2017-01-25 无锡芯朋微电子股份有限公司 Isolation structure of high-voltage driving circuit
CN103745988A (en) * 2014-01-07 2014-04-23 无锡芯朋微电子股份有限公司 Isolation structure of high-voltage driving circuit
CN103840008A (en) * 2014-03-31 2014-06-04 成都立芯微电子科技有限公司 High-voltage LDMOS device based on BCD process and manufacturing process
CN103840008B (en) * 2014-03-31 2016-06-08 成都立芯微电子科技有限公司 Based on high-voltage LDMOS device and the manufacturing process of BCD technique
CN105140303A (en) * 2014-05-30 2015-12-09 无锡华润上华半导体有限公司 Junction field effect transistor and preparation method thereof
CN105140303B (en) * 2014-05-30 2017-12-12 无锡华润上华科技有限公司 Junction field effect transistor and preparation method thereof
CN104681621B (en) * 2015-02-15 2017-10-24 上海华虹宏力半导体制造有限公司 A kind of source electrode raises high-voltage LDMOS and its manufacture method that voltage is used
CN104681621A (en) * 2015-02-15 2015-06-03 上海华虹宏力半导体制造有限公司 High-voltage LDMOS for source electrode rising voltage use and manufacturing method for high-voltage LDMOS
CN104821334A (en) * 2015-03-11 2015-08-05 上海华虹宏力半导体制造有限公司 N-type LDMOS device and process method thereof
CN104821334B (en) * 2015-03-11 2018-08-21 上海华虹宏力半导体制造有限公司 N-type LDMOS device and process
US9997626B2 (en) 2015-05-25 2018-06-12 Shanghai Huahong Grace Semiconductor Manufacturing Corporation NLDMOS device and method for manufacturing the same
CN107887436A (en) * 2016-09-30 2018-04-06 上海华虹宏力半导体制造有限公司 PLDMOS structures and its manufacture method
CN110120414A (en) * 2018-02-07 2019-08-13 联华电子股份有限公司 Transistor arrangement

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