CN103745988A - Isolation structure of high-voltage driving circuit - Google Patents

Isolation structure of high-voltage driving circuit Download PDF

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Publication number
CN103745988A
CN103745988A CN201410005662.8A CN201410005662A CN103745988A CN 103745988 A CN103745988 A CN 103745988A CN 201410005662 A CN201410005662 A CN 201410005662A CN 103745988 A CN103745988 A CN 103745988A
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type
well region
type well
buried layer
isolation structure
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CN103745988B (en
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易扬波
李海松
陶平
陈健
张立新
吴虹
王钦
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WUXI CHIPOWN MICROELECTRONICS CO Ltd
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WUXI CHIPOWN MICROELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

The invention discloses an isolation structure of a high-voltage driving circuit. The isolation structure comprises a P type substrate, wherein a first P type buried layer, a second P type intermittent island buried layer area, a third P type buried layer, a first N type buried layer and a second N type buried layer; the second P type intermittent island buried layer area is located between the first P type buried layer and the first N type buried layer; the third P type buried layer is located between the first N type buried layer and the second N type buried layer. According to the isolation structure, the problem that the peak value of the surface electric field of the transverse PN junction of RESURFLDMOS is overhigh is solved, and the reliability of the isolation structure is improved.

Description

A kind of isolation structure of high-voltage driving circuit
Technical field
The present invention relates to power semiconductor integrated circuit fields, say more accurately, relate to a kind of isolation structure of high-voltage driving circuit.
Background technology
High-voltage driving circuit can be used for various fields, as the electron rectifier in motor driving, fluorescent lamp and power management etc.The key component that in high-voltage driving circuit, level shift circuit is whole circuit, electricity coupling between electric property and the high-voltage LDMOS of the High-Voltage Insulation gate field-effect transistor LDMOS of composition level shift circuit can affect the performance of shift circuit, the large electric current of high-voltage LDMOS source and drain terminal and large voltage also can cause that thereby the ghost effect in other regions of whole integrated circuit affects the electric property of whole drive circuit, so the electric property of level shift circuit mesohigh LDMOS and the isolation of high-voltage LDMOS are undoubtedly the important content of high-voltage driving circuit performance and technical study, in high-voltage driving circuit, the design of isolation structure is the key of high-voltage driving circuit design always, but in isolation structure design technology, be faced with the withstand voltage and large difficult point of Leakage Current two.High-voltage driving circuit is that novel high-pressure power device, high-low pressure logic control circuit and protective circuit are integrated in to the circuit on single silicon chip; due to the advantage in its system: high reliability and stability and low-power consumption, volume, weight and cost, high-voltage driving circuit has great significance to miniaturization, intellectuality and the energy-saving of realizing the devices such as household electrical appliance, automotive electronics.High-voltage driving circuit can be divided into again high lateral circuit, low lateral circuit and height and tie termination environment, for preventing the impact of high-tension circuit on its peripheral circuits, mutually crosstalking between the cross influence between high voltage power device and high-tension circuit and device, the isolation technology of high-voltage driving circuit is high-voltage driving circuit basis normal, that effectively work, is also the key components that form HLV compatible IC technique platform.
In high-voltage LDMOS in conventional isolation structures, as shown in Figure 5, the P type well region at source region and substrate zone place and high-pressure N-shaped well region have formed the transverse p/n junction in RESURF system, because this PN junction does not have other conductive layer impacts around, can only mutually exhaust, in addition the surface structure curvature of this PN junction is larger, therefore this PN junction surface peak value electric field is very high, if there is being extraneous conductive ion to enter under the impact of situation, puncture and easily occur in this, thereby easily bring integrity problem in using for a long time.
Summary of the invention
The object of the invention is to provide a kind of isolation structure for high-voltage driving circuit, has solved the too high problem of RESURF LDMOS transverse p/n junction peak surface electric field, has improved the reliability of isolation structure.
The present invention for achieving the above object, adopts following technical scheme:
A kind of isolation structure of high-voltage driving circuit, comprise P type substrate, in P type substrate, be provided with the first p type buried layer, the 2nd P type interruption island buried regions district, the 3rd p type buried layer, the first n type buried layer, the second n type buried layer, and the 2nd P type is interrupted island buried regions district and is positioned between the first p type buried layer and the first n type buried layer, and the 3rd p type buried layer is between the first n type buried layer and the second n type buried layer.On the surface of P type substrate, be provided with a P type well region, a P type well region below is connected with the first p type buried layer.On the surface of P type substrate, be provided with the first N-type well region, the first N-type well region is connected with a P type well region, and is positioned at the top that the 2nd P type is interrupted island buried regions district.On the surface of P type substrate, be also provided with the second N-type well region, the second N-type well region is connected with the first N-type well region, and is positioned at the top of the first n type buried layer.On the surface of P type substrate, be also provided with the 2nd P type well region and the 3rd N-type well region, the 2nd P type well region is positioned at the top of the 3rd p type buried layer, and the 3rd N-type well region is positioned at the top of the second n type buried layer.Between the second N-type well region and the 2nd P type well region, be provided with the 4th N-type well region, between the 3rd N-type well region and the 2nd P type well region, be provided with the 5th N-type well region.In a P type well region, be provided with HeNXing contact zone, P type contact zone.In the second N-type well region, be provided with N-type contact zone.In the 3rd N-type well region, be provided with HeNXing contact zone, P type contact zone.On HeNXing contact zone, P type contact zone, be provided with metal, and be connected with N-type contact zone by metal.
The concentration of the first p type buried layer, the 2nd P type interruption island buried regions district and the 3rd p type buried layer can be identical, also can be different.
The 2nd P type is interrupted island buried regions district and consists of the little buried structure of several P types, and the number of little buried structure is more than or equal to 1, and the size of little buried structure can change, and the spacing between them also can change.
Preferred: it is identical by the width of the little buried regions of several P types that described the 2nd P type is interrupted island buried regions district (4), and spacing gradual change increases and be adjustable.
The 2nd P type is interrupted island buried regions district and can be connected with the first p type buried layer, also can separate.
The concentration of the first n type buried layer and the second n type buried layer can be identical, also can be different.
The concentration of the first N-type well region, the 5th N-type well region and the 4th N-type well region can be identical, also can be different.
The concentration of the second N-type well region and the 3rd N-type well region can be identical, also can be different.
The concentration of the first N-type well region, the 5th N-type well region and the 4th N-type well region is less than or equal to the concentration of the second N-type well region and the 3rd N-type well region.
Isolation structure for high-voltage driving circuit is compatible mutually with existing technique, and compared with existing other isolation technologies, tool of the present invention has the following advantages:
The present invention adds p type buried layer below the P type well region at source region and substrate zone place, and below high-pressure N-shaped well region, adds a series of island p type buried layers, and the width of this serial island p type buried layer is identical, and spacing gradual change increases and be adjustable.The auxiliary P type well region of p type buried layer and the high-pressure N-shaped well region that introduce P type well region below exhaust, thereby make electric field line disperse to reduce surperficial peak value electric field; And the peak value electric field value that a series of island p type buried layers can make the interior PN junction of body of the p type buried layer of P type well region below introducing and the composition of high-pressure N-shaped well region produce reduces and moves to drain region, thereby surface field also decreases, as shown in Figure 6.Solve the too high problem of RESURF LDMOS transverse p/n junction peak surface electric field, improved the reliability of isolation structure.
Accompanying drawing explanation
Fig. 1 is the high-voltage driving circuit isolation structure cross-sectional view that comprises high-voltage LDMOS in the present invention.
Fig. 2 is the high-voltage driving circuit isolation structure plane graph that comprises a high-voltage LDMOS in the present invention.
Fig. 3 is the high-voltage driving circuit isolation structure plane graph that comprises two high-voltage LDMOSs in the present invention.
Fig. 4 is the high-voltage driving circuit isolation structure plane graph that comprises multiple high-voltage LDMOSs in the present invention.
Fig. 5 is conventional high-tension drive circuit isolation structure cross-sectional view.
Fig. 6 is LDMOS surface field contrast schematic diagram in LDMOS surface field and conventional high-tension drive circuit isolation structure in high-voltage driving circuit isolation structure of the present invention;
In figure, Proposed Structure is structure of the present invention, and Traditional Structure is traditional structure, and Electric Filed is electric field.
Embodiment
A kind of isolation structure of high-voltage driving circuit as shown in Figure 1, comprise P type substrate 1, in P type substrate 1, be provided with the first p type buried layer 3, the 2nd P type interruption island buried regions district 4, the 3rd p type buried layer 5, the first n type buried layer 6, the second n type buried layer 7, and the 2nd P type is interrupted island buried regions district 4 between the first p type buried layer and the first n type buried layer 6, and the 3rd p type buried layer 5 is between the first n type buried layer 6 and the second n type buried layer 7.On the surface of P type substrate 1, being provided with P type well region 9, the one P type well region 9 belows is connected with the first p type buried layer 3.On the surface of P type substrate 1, be provided with the first N-type well region 8, the first N-type well regions 8 and be connected with a P type well region 9, and be positioned at the top that the 2nd P type is interrupted island buried regions district 4.On the surface of P type substrate 1, be also provided with the second N-type well region 10, the second N-type well regions 10 and be connected with the first N-type well region 8, and be positioned at the top of the first n type buried layer 6.On the surface of P type substrate 1, be also provided with the top that the 2nd P type well region 12 and the 3rd N-type well region 13, the two P type well regions 12 are positioned at the 3rd p type buried layer 5, the 3rd N-type well region 13 is positioned at the top of the second n type buried layer 7.Between the second N-type well region 10 and the 2nd P type well region 12, be provided with the 4th N-type well region 14, between the 3rd N-type well region 13 and the 2nd P type well region 12, be provided with the 5th N-type well region 11.In a P type well region 9, be provided with 15HeNXing contact zone, P type contact zone 16.In the second N-type well region 10, be provided with N-type contact zone 17.In the 3rd N-type well region 13, be provided with 18HeNXing contact zone, P type contact zone 19.On 18HeNXing contact zone, P type contact zone 19, be provided with metal 20, and be connected with N-type contact zone 17 by metal 20.
The concentration of the first p type buried layer 3, the 2nd P type interruption island buried regions district 4 and the 3rd p type buried layer 5 can be identical, also can be different.
The 2nd P type is interrupted island buried regions district 4 and consists of the little buried structure of several P types, and the number of little buried structure is more than or equal to 1, and the size of little buried structure can change, and the spacing between them also can change.
The 2nd P type is interrupted island buried regions district 4 and can be connected with the first p type buried layer 3, also can separate.
The concentration of the first n type buried layer 6 and the second n type buried layer 7 can be identical, also can be different.
The concentration of the first N-type well region 8, the 5th N-type well region 11 and the 4th N-type well region 14 can be identical, also can be different.
The concentration of the second N-type well region 10 and the 3rd N-type well region 13 can be identical, also can be different;
The concentration of the first N-type well region 8, the 5th N-type well region 11 and the 4th N-type well region 14 is less than or equal to the concentration of the second N-type well region 10 and the 3rd N-type well region 13.
The isolation structure typical case preparation method of described high-voltage driving circuit is as follows:
The first step: P type silicon substrate is prepared; Growth oxide layer, deposit silicon nitride, photoetching, Implantation N-type impurity, generate the first n type buried layer and the second n type buried layer; Remove silicon nitride, photoetching, Implantation p type impurity generate the first p type buried layer, the 2nd P type is interrupted island buried regions district and the 3rd p type buried layer; Then growing P-type epitaxial loayer.
Second step: P type Implantation and annealing form a P type well region and the 2nd P type well region; Then Implantation N-type impurity, forms the first N-type well region, the second N-type well region, the 3rd N-type well region, the 4th N-type well region and the 5th N-type well region; Then grow field oxide, gate oxide.And then depositing polysilicon and etch polysilicon;
The 3rd step: photoetching, Implantation N-type impurity generate N-type contact zone; Photoetching, Implantation p type impurity generate P type contact zone; Then deposit medium isolating oxide layer, contact hole etching, depositing metal and etching metal, if multiple layer metal technique is carried out repeatedly metal deposit, etching technics etc., finally carry out medium Passivation Treatment.
The isolation structure of a LDMOS structure that has been integrated shown in Fig. 2.The isolation structure of two LDMOS structures that has been integrated shown in Fig. 3 is for withstand voltage high-low pressure junction termination structures between two LDMOS structures, and two LDMOS share P type substrates.The isolation structure of multiple LDMOS structures that has been integrated shown in Fig. 4 is for withstand voltage high-low pressure junction termination structures between multiple LDMOS structures, and multiple LDMOS shares P type substrate.

Claims (6)

1. the isolation structure of a high-voltage driving circuit, it is characterized in that: comprise P type substrate (1), in P type substrate (1), be provided with successively the first p type buried layer (3), the 2nd P type interruption island buried regions district (4), the first n type buried layer (6), the 3rd p type buried layer (5), the second n type buried layer (7);
At the surface of P type substrate (1) adjacent P type well region (9), the first N-type well region (8), the second N-type well region (10), the 4th N-type well region (14), the 2nd P type well region (12), the 5th N-type well region (11) and the 3rd N-type well region (13) of being connected with successively;
The one P type well region (9) below is connected with the first p type buried layer (3); The first N-type well region (8) is positioned at the top that the 2nd P type is interrupted island buried regions district (4); The second N-type well region (10) is positioned at the top of the first n type buried layer (6), and coupled; The 2nd P type well region (12) is positioned at the top of the 3rd p type buried layer (5), and coupled; The 3rd N-type well region (13) is positioned at the top of the second n type buried layer (7), and coupled;
In a P type well region (9), be provided with P type contact zone (15) and N-type contact zone (16); In the second N-type well region (10), be provided with N-type contact zone (17); In the 3rd N-type well region (13), be provided with P type contact zone (18) and N-type contact zone (19); On P type contact zone (18) and N-type contact zone (19), be provided with metal (20), and be connected with N-type contact zone (17) by metal (20).
2. the isolation structure of high-voltage driving circuit according to claim 1, is characterized in that: described the 2nd P type is interrupted island buried regions district (4) and is connected or separates with the first p type buried layer (3).
3. the isolation structure of high-voltage driving circuit according to claim 1 and 2, it is characterized in that: described the 2nd P type is interrupted island buried regions district (4) and consists of the little buried structure of several P types, the number of little buried structure is more than or equal to 1, and size and the mutual spacing of little buried structure are identical or different.
4. the isolation structure of high-voltage driving circuit according to claim 3, is characterized in that: it is identical by the width of the little buried regions of several P types that described the 2nd P type is interrupted island buried regions district (4), and spacing gradual change increases and be adjustable.
5. the isolation structure of high-voltage driving circuit according to claim 1 and 2, is characterized in that: the concentration of the first p type buried layer (3), the 2nd P type interruption island buried regions district (4) and the 3rd p type buried layer (5) is identical or different;
The concentration of the first n type buried layer (6) and the second n type buried layer (7) is identical or different;
The concentration of the first N-type well region (8), the 5th N-type well region (11) and the 4th N-type well region (14) is identical or different;
The concentration of the second N-type well region (10) and the 3rd N-type well region (13) is identical or different.
6. the isolation structure of high-voltage driving circuit according to claim 5, is characterized in that: the concentration of the first N-type well region (8), the 5th N-type well region (11) and the 4th N-type well region (14) is less than or equal to the concentration of the second N-type well region (10) and the 3rd N-type well region (13).
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CN105336780A (en) * 2014-08-06 2016-02-17 旺宏电子股份有限公司 High-voltage semiconductor element
WO2016161841A1 (en) * 2015-04-10 2016-10-13 无锡华润上华半导体有限公司 Laterally diffused metal-oxide-semiconductor field-effect transistor
CN106158963A (en) * 2015-02-18 2016-11-23 旺宏电子股份有限公司 There is semiconductor device and the manufacture method thereof of buried layer
CN104167434B (en) * 2014-07-29 2017-01-04 无锡芯朋微电子股份有限公司 A kind of isolation structure of high-voltage driving circuit and preparation method thereof
US10121889B2 (en) 2014-08-29 2018-11-06 Macronix International Co., Ltd. High voltage semiconductor device
TWI731627B (en) * 2020-03-19 2021-06-21 新唐科技股份有限公司 High voltage integrated circuit structure

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CN104167434B (en) * 2014-07-29 2017-01-04 无锡芯朋微电子股份有限公司 A kind of isolation structure of high-voltage driving circuit and preparation method thereof
CN105336780A (en) * 2014-08-06 2016-02-17 旺宏电子股份有限公司 High-voltage semiconductor element
CN105336780B (en) * 2014-08-06 2018-11-09 旺宏电子股份有限公司 High-voltage semiconductor element
US10121889B2 (en) 2014-08-29 2018-11-06 Macronix International Co., Ltd. High voltage semiconductor device
CN106158963A (en) * 2015-02-18 2016-11-23 旺宏电子股份有限公司 There is semiconductor device and the manufacture method thereof of buried layer
WO2016161841A1 (en) * 2015-04-10 2016-10-13 无锡华润上华半导体有限公司 Laterally diffused metal-oxide-semiconductor field-effect transistor
US10014392B2 (en) 2015-04-10 2018-07-03 Csmc Technologies Fab2 Co., Ltd. Laterally diffused metal-oxide-semiconductor field-effect transistor
TWI731627B (en) * 2020-03-19 2021-06-21 新唐科技股份有限公司 High voltage integrated circuit structure
CN113497117A (en) * 2020-03-19 2021-10-12 新唐科技股份有限公司 High-voltage integrated circuit structure
CN113497117B (en) * 2020-03-19 2023-05-19 新唐科技股份有限公司 High voltage integrated circuit structure

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