CN104821334A - N-type LDMOS device and process method thereof - Google Patents

N-type LDMOS device and process method thereof Download PDF

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Publication number
CN104821334A
CN104821334A CN201510107015.2A CN201510107015A CN104821334A CN 104821334 A CN104821334 A CN 104821334A CN 201510107015 A CN201510107015 A CN 201510107015A CN 104821334 A CN104821334 A CN 104821334A
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type
ldmos device
region
trap
drift region
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CN104821334B (en
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石晶
钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses an N-type LDMOS device. An N type buried layer is arranged on a P-type substrate, and an N-type deep well is on the N-type buried layer. A P well is in the N-type deep well and comprises a heavily doped P-type region and the source region of the LDMOS device. The surface of the silicon substrate is provided with a gate oxide layer and a polysilicon gate. The N-type deep well also comprises the drain region of the LDMOS device, and the heavily doped P-type region, the source region and the drain region are led out through contact holes. The heavily doped P-type region and the source region in the P well are isolated by an STI field oxide. Two sides of the drain region in the drift region of the LDMOS device are provided with the STI field oxide. The drift region is a hierarchical drift region with different depths formed by injecting different energies. The invention also discloses the process method of the N-type LDMOS device, and the method can be integrated in a BCD process.

Description

N-type LDMOS device and process
Technical field
The present invention relates to semiconductor applications, refer to a kind of N-type LDMOS device especially, the invention still further relates to the process of described N-type LDMOS device.
Background technology
DMOS is high pressure resistant owing to having, and the feature such as high current drive capability and extremely low power dissipation, is widely adopted at present in electric power management circuit.In BCD technique, although DMOS with CMOS is integrated in same chip, but and requirement of low on-resistance withstand voltage due to height, under the prerequisite that the condition of DMOS in background region and drift region and the existing process conditions of CMOS are shared, there is contradiction in its conducting resistance and puncture voltage, often cannot meet the requirement of switching tube application.In LDMOS device, conducting resistance is an important index.Therefore, in order to make high performance LDMOS, need the conducting resistance and the puncture voltage that adopt various method optimised devices.
The structure of the N-type LDMOS of current routine as shown in Figure 1, comprises P type substrate 101 in figure, n type buried layer 102, N-type deep trap 103, P trap 107, gate oxide 10,8, polysilicon gate 109, heavily doped N-type district (source region) 111 and heavily doped N-type district (drain region) 115.This structure is not optimized the Electric Field Distribution of device, and the electric field strength on surface is higher, and puncture voltage is not ideal enough.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of N-type LDMOS device, improves drift region Potential Distributing, improves the puncture voltage of device.
For solving the problem, the invention provides a kind of N-type LDMOS device, P type substrate has n type buried layer, buried regions is N-type deep trap; Have P trap in described N-type deep trap, include the source region of heavily doped P-type district and described LDMOS device in P trap, surface of silicon has gate oxide and polysilicon gate; Also there is in described N-type deep trap the drain region of LDMOS device, go between heavily doped P-type district, source region and drain region extraction by contact hole; Heavily doped P-type district in described P trap and isolating with STI field oxygen between source region, in the drift region of LDMOS device, both sides, drain region have STI field oxygen, and drift region is the layering drift region of the different depth formed with different Implantation Energy.
Further, described STI field oxygen, or be LOCOS.
Further, described drift region divides energy injection to be formed with segmentation, and the distance range at the bottom margin of distance STI field, two sections of drift regions oxygen near raceway groove side or beak place, LOCOS raceway groove side is 0.1 ~ 0.3 μm; Low-yield injection scope is 50 ~ 150keV, and high-energy injects scope 300 ~ 600keV.
For solving the problem, the process of N-type LDMOS device of the present invention, comprises following steps:
1st step, P type substrate forms n type buried layer;
2nd step, deposit one deck epitaxial loayer on n type buried layer;
3rd step, lithographic definition forms STI field oxygen;
4th step, trap injection zone is opened in photoetching, injects and forms P trap, and injects the low-yield drift region of formation and high-energy drift region respectively;
5th step, thermal oxidation generates gate oxide, and depositing polysilicon also etches formation polysilicon gate; Make side wall; Ion implantation forms source region and the drain region of heavily doped P-type district and described LDMOS device;
6th step, completes contact hole technique, makes electrode.
Further, the P type low resistivity substrate of the substrate that adopts of described 1st step to be electrical resistivity range be 0.007 ~ 0.013 Ω cm.
Further, described 4th step, drift region first time Implantation Energy is 50 ~ 150keV, and second time Implantation Energy is 300 ~ 600keV.
N-type LDMOS device of the present invention, adopt the isolation of STI field oxygen, drift region adopts high low-energy difference to inject the drift region forming layering, avoids the STI corner areas of most easy to reach breakdown electric field, thus improve the Potential Distributing of drift region, reduce electric field strength.The process of N-type LDMOS device of the present invention, can inherit in BCD technique, utilize original process conditions in platform, when additionally not increasing mask plate and when utilizing original injection condition, by means of only the litho pattern of adjusting device structure, under making device keep the prerequisite of better characteristic, improve puncture voltage.
Accompanying drawing explanation
Fig. 1 is the structural representation of conventional n-type LDMOS device.
Fig. 2 ~ Fig. 7 is present invention process step schematic diagram.
Fig. 8 is present invention process flow chart of steps.
Description of reference numerals
101 is P type substrate, and 102 is n type buried layers, and 103 is N-type deep traps, 104 is STI field oxygen, and 105,106 is N-type drift region, and 107 is P traps, 108 is gate oxides, and 109 is polysilicon gates, and 110 is side walls, 111 is source regions, 112 is heavily doped P-type districts, and 113 is contact holes, and 114 is electrode (lead-in wires), 115 is drain regions, and a, b are distances.
Embodiment
N-type LDMOS device of the present invention, as shown in Figure 7, P type substrate 101 has n type buried layer 102, buried regions 102 is N-type deep trap 103; Have the source region 111 including heavily doped P-type district 112 and described LDMOS device in P trap 107, P trap 107 in described N-type deep trap 103, surface of silicon has gate oxide 108 and polysilicon gate 109; Also have the drain region 115 of LDMOS device in described N-type deep trap 103, heavily doped P-type district 112, source region 111 and drain region 115 are drawn by contact hole 113 by lead-in wire 114; Heavily doped P-type district 112 in described P trap 107 and isolating with STI field oxygen 104 between source region 111, in the drift region of LDMOS device, both sides, drain region 115 have STI field oxygen 104, drift region is the layering drift region of the different depth formed with different Implantation Energy, inject as more low-yield the drift region 105 formed, and higher-energy injects the drift region 106 formed.
Described STI field oxygen, also can replace and adopt LOCOS.As shown in Figure 7, the distance a at the bottom margin of distance STI field, two sections of drift regions oxygen near raceway groove side or beak place, LOCOS raceway groove side and b scope are 0.1 ~ 0.3 μm.
The process of N-type LDMOS device of the present invention, comprises following steps:
1st step, in electrical resistivity range be 0.007 ~ 0.013 Ω cm P type substrate on form n type buried layer, as shown in Figure 2.
2nd step, deposit one deck epitaxial loayer on n type buried layer, as shown in Figure 3.
3rd step, as shown in Figure 4, utilizes active area photoetching, opens shallow slot region at N-type deep trap 103, etching Chang Yang district; Shallow slot district fill oxide; STI field oxygen 104 is formed after etching and grinding.Or adopt LOCOS technique to form isolation.
4th step, trap injection zone is opened in photoetching, injects and forms P trap 107, and injects the drift region 106 of the drift region 105 and high-energy injection forming low-yield injection respectively.Low-yield drift region 105 ion implantation energy scope is 50 ~ 150keV, high-energy drift region 106 ion implantation energy scope 300 ~ 600keV, as shown in Figure 5.
5th step, as shown in Figure 6, thermal oxidation generates gate oxide 108, and depositing polysilicon also etches formation polysilicon gate 109; Make side wall 110; Ion implantation forms source region 111 and the drain region 115 of heavily doped P-type district 112 and described LDMOS device.
6th step, completes contact hole 113 technique, and make electrode 114, resulting devices completes as shown in Figure 7.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. a N-type LDMOS device, P type substrate has n type buried layer, buried regions is N-type deep trap; Have P trap in described N-type deep trap, include the source region of heavily doped P-type district and described LDMOS device in P trap, surface of silicon has gate oxide and polysilicon gate; Also there is in described N-type deep trap the drain region of LDMOS device, go between heavily doped P-type district, source region and drain region extraction by contact hole; It is characterized in that: the heavily doped P-type district in described P trap and isolating with STI field oxygen between source region, in the drift region of LDMOS device, both sides, drain region have STI field oxygen, and drift region is the layering drift region of the different depth formed with different Implantation Energy.
2. N-type LDMOS device as claimed in claim 1, is characterized in that: described STI field oxygen, or is LOCOS.
3. N-type LDMOS device as claimed in claim 1 or 2, it is characterized in that: described drift region divides energy injection to be formed with segmentation, the distance range at the bottom margin of distance STI field, two sections of drift regions oxygen near raceway groove side or beak place, LOCOS raceway groove side is 0.1 ~ 0.3 μm; Low-yield injection scope is 50 ~ 150keV, and high-energy injects scope 300 ~ 600keV.
4. manufacture the process of N-type LDMOS device as claimed in claim 1, it is characterized in that: comprise following steps:
1st step, P type substrate forms n type buried layer;
2nd step, deposit one deck epitaxial loayer on n type buried layer;
3rd step, lithographic definition forms STI field oxygen;
4th step, trap injection zone is opened in photoetching, injects and forms P trap, and injects the low-yield drift region of formation and high-energy drift region respectively;
5th step, thermal oxidation generates gate oxide, and depositing polysilicon also etches formation polysilicon gate; Make side wall; Ion implantation forms source region and the drain region of heavily doped P-type district and described LDMOS device;
6th step, completes contact hole technique, makes electrode.
5. the process of N-type LDMOS device as claimed in claim 4, is characterized in that: described 1st step, the P type low resistivity substrate of described substrate to be electrical resistivity range be 0.007 ~ 0.013 Ω cm.
6. N-type LDMOS device as claimed in claim 4, is characterized in that: described 4th step, and drift region first time Implantation Energy is 50 ~ 150keV, and second time Implantation Energy is 300 ~ 600keV.
CN201510107015.2A 2015-03-11 2015-03-11 N-type LDMOS device and process Active CN104821334B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298935A (en) * 2016-08-16 2017-01-04 上海华虹宏力半导体制造有限公司 LDMOS device and manufacture method thereof
CN106449412A (en) * 2016-09-30 2017-02-22 上海华虹宏力半导体制造有限公司 Technological method for switch N type LDMOS device
CN112117332A (en) * 2020-11-02 2020-12-22 上海华虹宏力半导体制造有限公司 LDMOS device and technological method

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US20100148251A1 (en) * 2008-12-11 2010-06-17 Hyon-Chol Lim Semiconductor device and method for manufacturing the same
CN102130164A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Buried layer of LDMOS (laterally diffused metal-oxide semiconductor)
US20130181287A1 (en) * 2012-01-17 2013-07-18 Globalfoundries Singapore Pte. Ltd. High voltage device
CN103632974A (en) * 2012-08-24 2014-03-12 上海华虹宏力半导体制造有限公司 Manufacturing method for improving in-plane uniformity of P type LDMOS surface channel device
CN103681791A (en) * 2012-09-05 2014-03-26 上海华虹宏力半导体制造有限公司 NLDMOS device and manufacture method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100148251A1 (en) * 2008-12-11 2010-06-17 Hyon-Chol Lim Semiconductor device and method for manufacturing the same
CN102130164A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Buried layer of LDMOS (laterally diffused metal-oxide semiconductor)
US20130181287A1 (en) * 2012-01-17 2013-07-18 Globalfoundries Singapore Pte. Ltd. High voltage device
CN103632974A (en) * 2012-08-24 2014-03-12 上海华虹宏力半导体制造有限公司 Manufacturing method for improving in-plane uniformity of P type LDMOS surface channel device
CN103681791A (en) * 2012-09-05 2014-03-26 上海华虹宏力半导体制造有限公司 NLDMOS device and manufacture method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298935A (en) * 2016-08-16 2017-01-04 上海华虹宏力半导体制造有限公司 LDMOS device and manufacture method thereof
CN106298935B (en) * 2016-08-16 2019-08-13 上海华虹宏力半导体制造有限公司 LDMOS device and its manufacturing method
CN106449412A (en) * 2016-09-30 2017-02-22 上海华虹宏力半导体制造有限公司 Technological method for switch N type LDMOS device
CN112117332A (en) * 2020-11-02 2020-12-22 上海华虹宏力半导体制造有限公司 LDMOS device and technological method
CN112117332B (en) * 2020-11-02 2023-08-22 上海华虹宏力半导体制造有限公司 LDMOS device and process method

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