CN105140303A - Junction field effect transistor and preparation method thereof - Google Patents
Junction field effect transistor and preparation method thereof Download PDFInfo
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- CN105140303A CN105140303A CN201410241307.0A CN201410241307A CN105140303A CN 105140303 A CN105140303 A CN 105140303A CN 201410241307 A CN201410241307 A CN 201410241307A CN 105140303 A CN105140303 A CN 105140303A
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Abstract
The present invention discloses a junction field effect transistor which comprises a P type substrate, a P type buried layer, N type buried layers arranged at two sides of the P type buried layer, an N type epitaxial layer, a first isolation structure, a second isolation structure, a third isolation structure and a fourth isolation structure which are arranged on the N type epitaxial layer, a source electrode area arranged between the first isolation structure and the second isolation structure, a first N well area arranged under the source electrode area, a gate electrode area arranged between the second isolation structure and the third isolation structure, a drain electrode area arranged between the third isolation structure and the fourth isolation structure, a second well area arranged under the source electrode area, and at least one P type field limit ring which is arranged above the N type epitaxial layer and is between the source electrode area and the drain electrode area. According to the above junction field effect transistor, the effect of Triple RESURF can be realized, the pinch-off voltage can be reduced effectively, and the purpose of low pinch-off voltage is realized. The invention also discloses the preparation method of the junction field effect transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of junction field effect transistor, also relate to a kind of preparation method of junction field effect transistor.
Background technology
BCD is a kind of monolithic integration process technology, and this technology can prepare bipolar transistor (BipolarJunctionTransistor) CMOS and DMOS device on the same chip.In BCD technique, junction field effect transistor (JunctionFieldEffectTransistor, JFET) be a very important class device, use junction field effect transistor very easily can build startup (start-up) module and constant-current source module.For junction field effect transistor, its pinch-off voltage (pinch-offvoltage) is one of very crucial parameter.The pinch-off voltage of traditional junction field effect transistor is higher.
Summary of the invention
Based on this, be necessary for the problems referred to above, a kind of junction field effect transistor with low pinch-off voltage is provided.
A kind of preparation method of junction field effect transistor is also provided.
A kind of junction field effect transistor, comprising: P type substrate; Be placed in the p type buried layer in described P type substrate and n type buried layer; Described n type buried layer is placed in the both sides of described p type buried layer respectively; Be placed in the N-type epitaxy layer on described n type buried layer and described p type buried layer surface; Be placed in the isolation structure in described N-type epitaxy layer; Described isolation structure comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure; Be placed in the source area between described first isolation structure and described second isolation structure; Be placed in the N well region below described source area; Be placed in the gate regions between described second isolation structure and described 3rd isolation structure; Be placed in the drain region between described 3rd isolation structure and described 4th isolation structure; Be placed in the 2nd N well region below described drain region; Also comprise and being placed in described N-type epitaxy layer and at least one P type field limiting ring between described source area and described drain region.
Wherein in an embodiment, described P type field limiting ring comprises the P type field limiting ring be placed in below described gate regions, to be placed in described N-type epitaxy layer and the 2nd P type field limiting ring be positioned at below described second isolation structure; And to be placed in described N-type epitaxy layer and the 3rd P type field limiting ring be positioned at below described 3rd isolation structure.
Wherein in an embodiment, a described P type field limiting ring, described 2nd P type field limiting ring and described 3rd P type field limiting ring are floating field limiting ring.
Wherein in an embodiment, also comprise the first field plate being placed in described second isolation structure surface and the second field plate being placed in described 3rd isolation structure surface.
Wherein in an embodiment, one end of described first field plate is positioned at the vertical direction at a described P type field limiting ring edge, and the distance of the other end and described 2nd P type field limiting ring is greater than zero; One end of described second field plate is positioned at the vertical direction at a described P type field limiting ring edge, and the distance of the other end and described 3rd P type field limiting ring is greater than zero.
Wherein in an embodiment, described first field plate and described second field plate are floating field plate, and described first field plate and described second field plate are polysilicon material.
Wherein in an embodiment, the doping content of described N-type epitaxy layer is higher than described P type substrate.
Wherein in an embodiment, the doping content of described P type substrate is 1 × 10
14~ 1 × 10
15㎝
-3, the doping content of described N-type epitaxy layer is 1 × 10
16~ 1 × 10
17㎝
-3; The doping content of a described N well region and described 2nd N well region is 7 × 10
16~ 3 × 10
17㎝
-3.
Wherein in an embodiment, described junction field effect transistor is circular or racetrack structure.
A preparation method for junction field effect transistor, comprises the following steps: provide P type substrate; Inject N-type impurity ion and p type impurity ion respectively, after pushing away trap, form n type buried layer and p type buried layer; Described n type buried layer is placed in the both sides of described p type buried layer respectively; Extension forms N-type epitaxy layer; The doping content of described N-type epitaxy layer is higher than the doping content of described P type substrate; Implanting p-type foreign ion in described N-type epitaxy layer, forms at least one P type field limiting ring after pushing away trap; Isolation structure is formed on the surface of described N-type epitaxy layer; Described isolation structure comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure; Inject N-type impurity ion in N-type epitaxy layer respectively between described first isolation structure and described second isolation structure, between described 3rd isolation structure and described 4th isolation structure, push away after trap becomes knot and form a N well region and the 2nd N well region; Source area, drain region is formed respectively to injecting N-type impurity ion in a described N well region and described 2nd N well region; In N-type epitaxy layer between described second isolation structure and described 3rd isolation structure, implanting p-type foreign ion forms gate regions.
Above-mentioned junction field effect transistor, by introducing n type buried layer and p type buried layer in P type substrate, form the PN junction of gradual gradient, and P type field limiting ring/N-type epitaxy layer, N-type epitaxy layer/p type buried layer, n type buried layer/P type substrate the PN junction face of TripleRESURF, effectively can reduce pinch-off voltage, realize the object of low pinch-off voltage.Simultaneously can also increase longitudinal direction, having lateral depletion, Potential Distributing evenly, improve the high pressure blocking ability of device.
Accompanying drawing explanation
Fig. 1 is the profile of the junction field effect transistor in an embodiment;
Fig. 2 is the vertical view of the junction field effect transistor in an embodiment;
Fig. 3 is the flow chart of the preparation method of junction field effect transistor in an embodiment.
Embodiment
For enabling object of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.In the present description and drawings, reference marker N and P distributing to layer or region represents that these layers or region comprise a large amount of electronics or hole respectively.Further, the concentration of the reference marker+and-expression dopant of distributing to N or P is higher or lower than the concentration be not assigned to like this in the layer of mark.In the description and accompanying drawing of preferred embodiment hereafter, similar assembly is assigned similar reference marker and this place omits its redundant description.
A kind of junction field effect transistor, comprising: P type substrate; Be placed in the p type buried layer in described P type substrate and n type buried layer.Wherein, n type buried layer is placed in the both sides of p type buried layer respectively.Junction field effect transistor also comprises the N-type epitaxy layer being placed in n type buried layer and p type buried layer surface; Be placed in the isolation structure in N-type epitaxy layer.Wherein, isolation structure comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure.Junction field effect transistor also comprises the source area be placed between the first isolation structure and the second isolation structure; Be placed in the N well region below source area; Be placed in the gate regions between the second isolation structure and the 3rd isolation structure; Be placed in the drain region between the 3rd isolation structure and the 4th isolation structure; Be placed in the 2nd N well region below drain region; And to be placed in N-type epitaxy layer and at least one P type field limiting ring between source area and drain region.
Above-mentioned junction field effect transistor, by introducing n type buried layer and p type buried layer in P type substrate, form the PN junction of gradual gradient, achieve the effect of triple reduction surface field (TripleRESURF), effectively can reduce pinch-off voltage, slow down concentration gradient, increase longitudinal, having lateral depletion, Potential Distributing evenly, and then improve the high pressure blocking ability of device.
Figure 1 shows that the cutaway view of the junction field effect transistor in a specific embodiment.
As shown in Figure 1, a kind of junction field effect transistor, it comprises P type substrate 102 and the n type buried layer be placed in P type substrate 102 and p type buried layer 104.In the present embodiment, the doping content of P type substrate 102 is 1 × 10
14~ 1 × 10
15㎝
-3.N type buried layer comprises the n type buried layer 106 and 108 being arranged at p type buried layer 102 both sides respectively.The doping content of p type buried layer 104 and n type buried layer is 1 × 10
17~ 1 × 10
18㎝
-3.N type buried layer and p type buried layer 104 by ion implantation and through high temperature push away trap formed.N-epitaxial loayer 110 is formed on the surface of p type buried layer 104 and n type buried layer.Particularly, the doping content of N-epitaxial loayer 110 is a little more than the doping content of P type substrate 102.In the present embodiment, the doping content of N-epitaxial loayer 110 is 1 × 10
16~ 1 × 10
17㎝
-3.
N-epitaxial loayer 110 is provided with multiple isolation structure, comprises the first isolation structure 112, second isolation structure 114, the 3rd isolation structure 116 and the 4th isolation structure 118.Multiple isolation structure isolates the extraction location of the source electrode (S) of junction field effect transistor, grid (G) and drain electrode (D).Particularly, isolation structure is silica material.Be source area 130 between the first isolation structure 112 and the second isolation structure 114; Be gate regions 132 between second isolation structure 114 and the 3rd isolation structure 116; Be drain region 134 between the 3rd isolation structure 116 and the 4th isolation structure 118.Source area 130, gate regions 132 and drain region 134 are respectively as the extraction location of source electrode, grid and drain electrode.In the present embodiment, the dopant type of source area 130 and drain region 134 is N+ type, and the dopant type of gate regions 132 is P+ type.Source area 130, gate regions 132 and drain region 134 are formed by the mode of ion implantation, and its doping content is 1 × 10
19~ 1 × 10
20㎝
-3.
On N-epitaxial loayer 110 and the below being positioned at source area 130 is provided with a N well region 120.On N-epitaxial loayer 110 and the below being positioned at drain region 134 is provided with the 2nd N well region 122.The doping content of the one N well region 120 and the 2nd N well region 122 is 7 × 10
16~ 3 × 10
17㎝
-3.Multiple P-field limiting ring is also provided with on N-epitaxial loayer 110 and between source area 130 and drain region 134.Particularly, P-field limiting ring is floating field limiting ring, and its doping content is 1 × 10
16~ 1 × 10
17㎝
-3.Multiple P-field limiting ring is spaced apart, and diminishes gradually from 134 to gate regions, drain region 132 ring spacing, and ring width becomes large gradually.In the present embodiment, P-field limiting ring comprises a P-field limiting ring 124, the 2nd P-field limiting ring 126 and the 3rd P-field limiting ring 128.Wherein, a P-field limiting ring 124 is positioned at the below of gate regions 132.2nd P-field limiting ring 126 is positioned at the below of the second isolation structure 114.3rd P-field limiting ring 128 is positioned at the below of the 3rd isolation structure 116.P-field limiting ring can strengthen exhausting N-epitaxial loayer 110, thus contributes to the concentration and the resistance to pressure that promote N-epitaxial loayer 110, reduces specific on-resistance simultaneously.In other examples, the quantity of P-field limiting ring can set as required, is not limited to the number in the present embodiment.
Above-mentioned junction field effect transistor, it is by introducing p type buried layer 104 and n type buried layer, PN junction is formed between P-field limiting ring and N-epitaxial loayer 110, between N-epitaxial loayer 110 and p type buried layer 104 and between n type buried layer and P type substrate 102, achieve the effect of TripleRESURF, effectively can reduce pinch-off voltage, reach the object of low pinch-off voltage.Simultaneously can also slow down concentration gradient, increase longitudinally, having lateral depletion, Potential Distributing evenly, improve the high pressure blocking ability of device.Such as, when D end is for high pressure, by drain region 134 and the 2nd N well region 122, current potential is introduced on N-epitaxial loayer 110, n type buried layer.Transversely N-epitaxial loayer 110 and multiple P-field limiting ring exhaust mutually, meet RESURF effect, and what enhance transversely is withstand voltage.In longitudinal direction, n type buried layer and P type substrate 102, p type buried layer 104 are formed and mutually exhaust, then depletion layer extends to N-epitaxial loayer 110 from the bottom to top, formed generally and the three-dimensional of N-epitaxial loayer 110 is exhausted, the concentration of N-epitaxial loayer 110 is promoted, reduces the specific on-resistance of junction field effect transistor.
In the present embodiment, above-mentioned junction field effect transistor also comprises the first field plate 136 being arranged at the second isolation structure 114 surface respectively and the second field plate 138 being arranged at the 3rd isolation structure 116 surface.Particularly, the first field plate 136 and the second field plate 138 are floating field plate, and it is polysilicon material.In the present embodiment, one end of the first field plate 136 is positioned at the vertical direction at P-field limiting ring 124 edge, and the other end and the 2nd P-field limiting ring 126 have certain spacing a.Same, one end of the second field plate 138 is positioned at the vertical direction at P-field limiting ring 124 edge, and the other end and the 3rd P-field limiting ring 128 have certain spacing.In the present embodiment, employing floating field plate dynamically can respond to the current potential between G, D, thus exhausts the enhancing that N-epitaxial loayer 110 produces in various degree, ensure that the reliability of device.Such as, during junction field effect transistor conducting, if the current potential of D end is+700V, G end is 0V, and the field plate being in floating can induce the absolute potential of D end on space length, as+30V, then the relative potentials of D end is then-670V, therefore can strengthen exhausting N-epitaxial loayer 110, the radius of curvature at the knot face place of P-field limiting ring and N-epitaxial loayer 110 is expanded, reduce the gathering of electric field.Meanwhile, leave certain distance a between field plate and P-field limiting ring, after can guaranteeing photoetching, field plate does not fall in P-field limiting ring region.Field plate exhausts mutual superposition to exhausting of N-epitaxial loayer 110 with P-field limiting ring to N-epitaxial loayer 110, strengthens exhausting N-epitaxial loayer 110, promotes the resistance to pressure of N-epitaxial loayer 110, reduces the specific on-resistance of device.
In the present embodiment, junction field effect transistor is circular or racetrack structure, as shown in Figure 2.Fig. 2 is the vertical view of the junction field effect transistor in an embodiment, and it is racetrack structure, along A-A ＇ line cutaway view as shown in Figure 1.Adopt device architecture that is circular or racetrack to be easy to telescoping components width flexibly, the turning electric field simultaneously reducing strip structure is assembled, and is easily widely used.
Above-mentioned junction field effect transistor, can also realize constant current function.Specific works principle is: when D end moment plus high-pressure, by the effect of TripleResurf, all knot faces realize exhausting completely.Simultaneously, field plate can be uniformly distributed the intensive electric field concentrated between gate regions 132/P-field limiting ring and N-epitaxial loayer 110, depletion layer extends to D end, completely evenly drop to electronegative potential from D-S electromotive force, realizes high pressure block function (the present invention can realize 700V high pressure and block).V simultaneously
gsfor 0V, junction field effect transistor self character allows electric current to flow through, and forms pressure drop in S end dead resistance.Along with electric current increases, V
gsbe negative gradually, the grid formed by gate regions 132/P-field limiting ring and p type buried layer 104 is the longitudinal interface of vertical depletion gradually, and electric current diminishes and then affects pressure drop and diminishes, and balance when pressure drop and electric current are formed, pinch-off voltage regional stability, realizes constant current function.
Figure 3 shows that the preparation method of a kind of junction field effect transistor in an embodiment, comprise the following steps.
S310, provides P type substrate.
In the present embodiment, the doping content of P type substrate is 1 × 10
14~ 1 × 10
15㎝
-3.
S320, injects N-type impurity ion and p type impurity ion respectively, forms n type buried layer and p type buried layer after pushing away trap.
Particularly, the n type buried layer of formation and the doping content of p type buried layer are 1 × 10
17~ 1 × 10
18㎝
-3.N type buried layer lays respectively at the both sides of p type buried layer.
S330, extension forms N-type epitaxy layer.
In the present embodiment, the epitaxial loayer of formation is N-epitaxial loayer, and its doping content is slightly higher than the concentration of P type substrate.Particularly, the doping content of N-epitaxial loayer is 1 × 10
16~ 1 × 10
17㎝
-3.
S340, implanting p-type foreign ion in N-type epitaxy layer, forms at least one P type field limiting ring after pushing away trap.
Particularly, the P type field limiting ring of formation is P-type.The P-field limiting ring formed is floating field limiting ring, and its doping content is 1 × 10
16~ 1 × 10
17㎝
-3.
S350, forms isolation structure on the surface of N-type epitaxy layer.
The isolation structure formed comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure.Multiple isolation structure isolates the extraction location of the source electrode (S) of junction field effect transistor, grid (G) and drain electrode (D).In the present embodiment, isolation structure is silica material.
S360, forms a N well region and the 2nd N well region.
Inject N-type impurity ion in N-type epitaxy layer respectively between the first isolation structure and the second isolation structure and between the 3rd isolation structure and the 4th isolation structure and form a N well region and the 2nd N well region.The doping content of the one N well region and the 2nd N well region is 7 × 10
16~ 3 × 10
17㎝
-3.
S370, forms gate regions, source area and drain region.
Source area, drain region is formed respectively to injecting N-type impurity ion in a N well region and the 2nd N well region.Wherein source area and drain region are N+ type, and source area is positioned at above a N well region, and drain region is positioned at above the 2nd N well region.In N-type epitaxy layer between the second isolation structure and the 3rd isolation structure, implanting p-type foreign ion forms the gate regions of P+ type.In the present embodiment, the doping content of the gate regions of formation, source area and drain region is 1 × 10
19~ 1 × 10
20㎝
-3.
After forming gate regions, source area and drain region by ion implantation, also need to carry out annealing and completing last part technology, form complete device architecture, thus the bottom vertical realizing longitudinally knot is withstand voltage and horizontal PN cylinder knot is withstand voltage.
By the junction field effect transistor that above-mentioned junction field effect transistor prepares, P type substrate is introduced n type buried layer and p type buried layer, form the PN junction of gradual gradient, achieve the effect of triple reduction surface field TripleRESURF, effectively can reduce pinch-off voltage, slow down concentration gradient, increase longitudinal, having lateral depletion, Potential Distributing evenly, improve the high pressure blocking ability of device.
In other examples, the preparation method of above-mentioned junction field effect transistor, also comprises step between step S360 and S370: form the first field plate and the second field plate respectively on the surface of the second isolation structure, the 3rd isolation structure.Particularly, the first field plate and the second field plate are floating field plate, and it is polysilicon material.In the present embodiment, the P-field limiting ring of formation is for comprising a P-field limiting ring, the 2nd P-field limiting ring and the 3rd P-field limiting ring.Wherein, a P-field limiting ring is positioned at the below of gate regions.2nd P-field limiting ring is positioned at the below of the second isolation structure.3rd P-field limiting ring is positioned at the below of the 3rd isolation structure
The one end of the first field plate formed is positioned at the vertical direction at a P-field limiting ring edge, and the other end and the 2nd P-field limiting ring have certain spacing.Same, one end of the second field plate of formation is positioned at the vertical direction at a P-field limiting ring edge, and the other end and the 3rd P-field limiting ring have certain spacing.Formation floating field plate dynamically can respond to the current potential between G, D, thus exhausts the enhancing that N-epitaxial loayer produces in various degree, ensure that the reliability of device.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a junction field effect transistor, is characterized in that, comprising: P type substrate; Be placed in the p type buried layer in described P type substrate and n type buried layer; Described n type buried layer is placed in the both sides of described p type buried layer respectively; Be placed in the N-type epitaxy layer on described n type buried layer and described p type buried layer surface; Be placed in the isolation structure in described N-type epitaxy layer; Described isolation structure comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure; Be placed in the source area between described first isolation structure and described second isolation structure; Be placed in the N well region below described source area; Be placed in the gate regions between described second isolation structure and described 3rd isolation structure; Be placed in the drain region between described 3rd isolation structure and described 4th isolation structure; Be placed in the 2nd N well region below described drain region; Also comprise and being placed in described N-type epitaxy layer and at least one P type field limiting ring between described source area and described drain region.
2. junction field effect transistor according to claim 1, it is characterized in that, described P type field limiting ring comprises the P type field limiting ring be placed in below described gate regions, to be placed in described N-type epitaxy layer and the 2nd P type field limiting ring be positioned at below described second isolation structure; And to be placed in described N-type epitaxy layer and the 3rd P type field limiting ring be positioned at below described 3rd isolation structure.
3. junction field effect transistor according to claim 2, is characterized in that, a described P type field limiting ring, described 2nd P type field limiting ring and described 3rd P type field limiting ring are floating field limiting ring.
4. junction field effect transistor according to claim 2, is characterized in that, also comprises the first field plate being placed in described second isolation structure surface and the second field plate being placed in described 3rd isolation structure surface.
5. junction field effect transistor according to claim 4, is characterized in that, one end of described first field plate is positioned at the vertical direction at a described P type field limiting ring edge, and the distance of the other end and described 2nd P type field limiting ring is greater than zero; One end of described second field plate is positioned at the vertical direction at a described P type field limiting ring edge, and the distance of the other end and described 3rd P type field limiting ring is greater than zero.
6. the junction field effect transistor according to claim 4 or 5, is characterized in that, described first field plate and described second field plate are floating field plate, and described first field plate and described second field plate are polysilicon material.
7. junction field effect transistor according to claim 1, is characterized in that, the doping content of described N-type epitaxy layer is higher than described P type substrate.
8. junction field effect transistor according to claim 1, is characterized in that, the doping content of described P type substrate is 1 × 10
14~ 1 × 10
15㎝
-3, the doping content of described N-type epitaxy layer is 1 × 10
16~ 1 × 10
17㎝
-3; The doping content of a described N well region and described 2nd N well region is 7 × 10
16~ 3 × 10
17㎝
-3.
9. according to the arbitrary described junction field effect transistor of claim 1 ~ 8, it is characterized in that, described junction field effect transistor is circular or racetrack structure.
10. a preparation method for junction field effect transistor, comprises the following steps:
P type substrate is provided;
Inject N-type impurity ion and p type impurity ion respectively, after pushing away trap, form n type buried layer and p type buried layer; Described n type buried layer is placed in the both sides of described p type buried layer respectively;
Extension forms N-type epitaxy layer; The doping content of described N-type epitaxy layer is higher than the doping content of described P type substrate;
Implanting p-type foreign ion in described N-type epitaxy layer, forms at least one P type field limiting ring after pushing away trap;
Isolation structure is formed on the surface of described N-type epitaxy layer; Described isolation structure comprises the first isolation structure, the second isolation structure, the 3rd isolation structure and the 4th isolation structure;
Inject N-type impurity ion in N-type epitaxy layer respectively between described first isolation structure and described second isolation structure, between described 3rd isolation structure and described 4th isolation structure, push away after trap becomes knot and form a N well region and the 2nd N well region;
Source area, drain region is formed respectively to injecting N-type impurity ion in a described N well region and described 2nd N well region; In N-type epitaxy layer between described second isolation structure and described 3rd isolation structure, implanting p-type foreign ion forms gate regions.
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