CN103745988B - Isolation structure of high-voltage driving circuit - Google Patents
Isolation structure of high-voltage driving circuit Download PDFInfo
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- CN103745988B CN103745988B CN201410005662.8A CN201410005662A CN103745988B CN 103745988 B CN103745988 B CN 103745988B CN 201410005662 A CN201410005662 A CN 201410005662A CN 103745988 B CN103745988 B CN 103745988B
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- 238000002955 isolation Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 9
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
Abstract
The invention discloses an isolation structure of a high-voltage driving circuit. The isolation structure comprises a P type substrate, wherein a first P type buried layer, a second P type intermittent island buried layer area, a third P type buried layer, a first N type buried layer and a second N type buried layer; the second P type intermittent island buried layer area is located between the first P type buried layer and the first N type buried layer; the third P type buried layer is located between the first N type buried layer and the second N type buried layer. According to the isolation structure, the problem that the peak value of the surface electric field of the transverse PN junction of RESURFLDMOS is overhigh is solved, and the reliability of the isolation structure is improved.
Description
Technical field
The present invention relates to power semiconductor integrated circuit fields, more accurately say, be related to a kind of high-voltage driving circuit every
From structure.
Background technology
High-voltage driving circuit can be used for various fields, as the electron rectifier in Motor drive, fluorescent lamp and power supply pipe
Reason etc..In high-voltage driving circuit, level shift circuit is the key component of whole circuit, and the high pressure of composition level shift circuit is exhausted
Electricity coupling between the electric property of edge gate field-effect transistor ldmos and high pressure ldmos can affect the performance of shift circuit, high pressure
The high current of ldmos source and drain terminal and big voltage also can cause the ghost effect in whole other regions of integrated circuit thus affecting
The electric property of whole drive circuit, thus the electric property of level shift circuit mesohigh ldmos and high pressure ldmos every
From the important content of high-voltage driving circuit performance and technical study beyond doubt, in high-voltage driving circuit, the design of isolation structure is always
It is the key of high-voltage driving circuit design, but the pressure and big difficult point of Leakage Current two is faced with isolation structure design technology.
High-voltage driving circuit is that novel high-pressure power device, high-low pressure logic control circuit and protection circuit are integrated in single silicon chip
On circuit, the advantage due in its system: high reliability and stability and low-power consumption, volume, weight and cost, high pressure drive
Dynamic circuit has great significance to miniaturization, intellectuality and the energy-saving of realizing the devices such as household electrical appliance, automotive electronics.High pressure
Drive circuit can be divided into high lateral circuit, low-side circuitry and height knot termination environment again, for preventing high-tension circuit to circuit about
Impact, the mutual crosstalk between the cross influence between high voltage power device and high-tension circuit and device, high-voltage driving circuit
Isolation technology be that high-voltage driving circuit is normal, effectively work basis, be also the key forming HLV compatible IC technique platform
Part.
In high pressure ldmos in conventional isolation structures, as shown in figure 5, the p-type well region at source region and substrate zone place and high pressure
N-shaped well region constitutes the horizontal pn-junction in resurf system, due to not having other conductive layers to affect around this pn-junction, can only be mutual
Exhaust, at the surface of this pn-junction, structural curvature is larger in addition, therefore this pn-junction surface peak electric field is very high, if there being extraneous conduction
Under the influence of ion entrance situation, puncture and be susceptible to here, thus easily bringing integrity problem in long use.
Content of the invention
Present invention aim at provide a kind of for the isolation structure in high-voltage driving circuit, solve resurfldmos
Laterally the too high problem of pn-junction peak surface electric field, improves the reliability of isolation structure.
The present invention for achieving the above object, adopts the following technical scheme that
A kind of isolation structure of high-voltage driving circuit, including p-substrate, be provided with p-substrate the first p-type buried regions,
Two p-type interruption island buried regions areas, the 3rd p-type buried regions, the first N-shaped buried regions, the second N-shaped buried regions, and the second p-type interruption island buried regions
Area is located between the first p-type buried regions and the first N-shaped buried regions, the 3rd p-type buried regions be located at the first N-shaped buried regions and the second N-shaped buried regions it
Between.It is provided with the first p-type well region on the surface of p-substrate, be connected with the first p-type buried regions below the first p-type well region.In p-substrate
Surface be provided with the first N-shaped well region, the first N-shaped well region is connected with the first p-type well region, and be located at second p-type interruption island buried regions
The top in area.It is additionally provided with the second N-shaped well region on the surface of p-substrate, the second N-shaped well region is connected with the first N-shaped well region, and is located at
The top of the first N-shaped buried regions.It is additionally provided with the second p-type well region and the 3rd N-shaped well region, the second p-type well region position on the surface of p-substrate
In the top of the 3rd p-type buried regions, the 3rd N-shaped well region is located at the top of the second N-shaped buried regions.In the second N-shaped well region and the second p-type trap
It is provided with the 4th N-shaped well region between area, between the 3rd N-shaped well region and the second p-type well region, be provided with the 5th N-shaped well region.In the first p-type
It is provided with the first p-type contact area and the first N-shaped contact zone in well region.It is provided with the second N-shaped contact zone in the second N-shaped well region.?
It is provided with the second p-type contact area and the 3rd N-shaped contact zone in three N-shaped well regions.In the second p-type contact area and the 3rd N-shaped contact zone
It is provided with metal, and be connected with the second N-shaped contact zone by metal.
First p-type buried regions, the second p-type interruption island buried regions area and the concentration of the 3rd p-type buried regions can identical it is also possible to not
With.
Second p-type interruption island buried regions area is made up of the little buried structure of several p-types, and the number of the little buried structure of p-type is big
In 1, the size of the little buried structure of p-type can change, and the spacing between them can also change.
Preferred: described second p-type interruption island buried regions area (4) is identical by several width, the p-type that spacing gradual change increases
Little buried regions composition.
Second p-type interruption island buried regions area can be connected it is also possible to separate with the first p-type buried regions.
The concentration of the first N-shaped buried regions and the second N-shaped buried regions can identical it is also possible to different.
The concentration of the first N-shaped well region, the 5th N-shaped well region and the 4th N-shaped well region can identical it is also possible to different.
The concentration of the second N-shaped well region and the 3rd N-shaped well region can identical it is also possible to different.
The concentration of the first N-shaped well region, the 5th N-shaped well region and the 4th N-shaped well region is less than or equal to the second N-shaped well region and the 3rd n
The concentration of type well region.
Isolation structure for high-voltage driving circuit is mutually compatible with existing process, and compared with other isolation technologies existing,
The present invention has the advantage that
The present invention adds p-type buried regions below the p-type well region that source region and substrate zone are located, and below high pressure N-shaped well region
Add a series of island p-type buried regions, and the width of this serial island p-type buried regions is identical, spacing gradual change increases and adjustable.P-type trap
The p-type buried regions auxiliary p-type well region introducing below area is exhausted with high pressure N-shaped well region, so that electric field line is disperseed thus reducing surface peak
Electric field；And a series of island p-type buried regions can make the body of the composition of the p-type buried regions and high pressure N-shaped well region introducing below p-type well region
The peak value electric field value that interior pn-junction produces reduces and moves to drain region, thus surface field also decreases, as shown in Figure 6.Solve
Resurf ldmos horizontal pn-junction peak surface electric field too high problem, improves the reliability of isolation structure.
Brief description
Fig. 1 is the high-voltage driving circuit isolation structure cross-sectional view comprising high pressure ldmos in the present invention.
Fig. 2 is the high-voltage driving circuit isolation structure plan comprising a high pressure ldmos in the present invention.
Fig. 3 is the high-voltage driving circuit isolation structure plan comprising two high pressure ldmos in the present invention.
Fig. 4 is the high-voltage driving circuit isolation structure plan comprising multiple high pressure ldmos in the present invention.
Fig. 5 is conventional high-tension drive circuit isolation structure cross-sectional view.
Fig. 6 be the present invention high-voltage driving circuit isolation structure in ldmos surface field and conventional high-tension drive circuit every
Ldmos surface field contrast schematic diagram in structure；
In figure proposed structure is present configuration, and traditional structure is traditional structure,
Electric filed is electric field.
Specific embodiment
A kind of isolation structure of high-voltage driving circuit as shown in Figure 1, including p-substrate 1, is provided with first in p-substrate 1
P-type buried regions 3, the second p-type interruption island buried regions area 4, the 3rd p-type buried regions 5, the first N-shaped buried regions 6, the second N-shaped buried regions 7, and second
P-type interruption island buried regions area 4 is located between the first p-type buried regions and the first N-shaped buried regions 6, and the 3rd p-type buried regions 5 buries positioned at the first N-shaped
Between layer 6 and the second N-shaped buried regions 7.It is provided with the first p-type well region 9, the first p-type well region 9 lower section and first on the surface of p-substrate 1
P-type buried regions 3 is connected.It is provided with the first N-shaped well region 8 on the surface of p-substrate 1, the first N-shaped well region 8 is connected with the first p-type well region 9,
And it is located at the top that the second p-type is interrupted island buried regions area 4.It is additionally provided with the second N-shaped well region 10, the 2nd n on the surface of p-substrate 1
Type well region 10 is connected with the first N-shaped well region 8, and is located at the top of the first N-shaped buried regions 6.It is additionally provided with the surface of p-substrate 1
Two p-type well regions 12 and the 3rd N-shaped well region 13, the second p-type well region 12 is located at the top of the 3rd p-type buried regions 5, the 3rd N-shaped well region 13
Top positioned at the second N-shaped buried regions 7.It is provided with the 4th N-shaped well region 14 between the second N-shaped well region 10 and the second p-type well region 12,
It is provided with the 5th N-shaped well region 11 between 3rd N-shaped well region 13 and the second p-type well region 12.It is provided with the first p-type in the first p-type well region 9
Contact zone 15 and the first N-shaped contact zone 16.It is provided with the second N-shaped contact zone 17 in the second N-shaped well region 10.In the 3rd N-shaped well region
It is provided with the second p-type contact area 18 and the 3rd N-shaped contact zone 19 in 13.In the second p-type contact area 18 and the 3rd N-shaped contact zone 19
It is provided with metal 20, and be connected with the second N-shaped contact zone 17 by metal 20.
First p-type buried regions 3, second p-type interruption island buried regions area 4 can be identical with the concentration of the 3rd p-type buried regions 5, also may be used
With difference.
Second p-type interruption island buried regions area 4 is made up of the little buried structure of several p-types, and the number of the little buried structure of p-type is big
In 1, the size of the little buried structure of p-type can change, and the spacing between them can also change.
Second p-type interruption island buried regions area 4 can be connected it is also possible to separate with the first p-type buried regions 3.
First N-shaped buried regions 6 and the concentration of the second N-shaped buried regions 7 can identical it is also possible to different.
First N-shaped well region 8, the 5th N-shaped well region 11 and the concentration of the 4th N-shaped well region 14 can identical it is also possible to different.
Second N-shaped well region 10 and the concentration of the 3rd N-shaped well region 13 can identical it is also possible to different；
The concentration of the first N-shaped well region 8, the 5th N-shaped well region 11 and the 4th N-shaped well region 14 is less than or equal to the second N-shaped well region 10
Concentration with the 3rd N-shaped well region 13.
The isolation structure exemplary manufacturing process of described high-voltage driving circuit is as follows:
The first step: p-type silicon substrate prepares；Growth oxide layer, deposit silicon nitride, photoetching, ion implanting p-type impurity, generate
First N-shaped buried regions and the second N-shaped buried regions；Remove silicon nitride, photoetching, ion implanting n-type impurity generate the first p-type buried regions, the 2nd p
Type interruption island buried regions area and the 3rd p-type buried regions；Then grow p-type epitaxial layer.
Second step: p-type ion implanting and annealing form the first p-type well region and the second p-type well region；Then ion implanting N-shaped
Impurity, forms the first N-shaped well region, the second N-shaped well region, the 3rd N-shaped well region, the 4th N-shaped well region and the 5th N-shaped well region；Then give birth to
Long field oxide layer, gate oxide.And then depositing polysilicon and etches polycrystalline silicon；
3rd step: photoetching, ion implanting p-type impurity generate N-shaped contact zone；Photoetching, ion implanting n-type impurity generate p-type
Contact zone；Then medium isolating oxide layer, contact hole etching, deposit metal and etching metal are deposited, if multiple layer metal work
Skill, then carry out multiple Metal deposition, etching technics etc., finally carries out dielectric passivation process.
Shown in Fig. 2 is the isolation structure being integrated with a ldmos structure.Shown in Fig. 3 is to be integrated with two ldmos knots
The isolation structure of structure, is for pressure high-low pressure junction termination structures between two ldmos structures, and two ldmos share p
Type substrate.Shown in Fig. 4 is the isolation structure being integrated with multiple ldmos structures, is for resistance between multiple ldmos structures
The high-low pressure junction termination structures of pressure, and multiple ldmos shares p-substrate.
Claims (6)
1. a kind of isolation structure of high-voltage driving circuit it is characterised in that: include p-substrate (1), in p-substrate (1) successively
Be provided with the first p-type buried regions (3), the second p-type interruption island buried regions area (4), the first N-shaped buried regions (6), the 3rd p-type buried regions (5), the
Two N-shaped buried regions (7)；
It is connected with the first p-type well region (9), the first N-shaped well region (8), the second N-shaped trap the surface of p-substrate (1) is adjacent successively
Area (10), the 4th N-shaped well region (14), the second p-type well region (12), the 5th N-shaped well region (11) and the 3rd N-shaped well region (13)；
It is connected with the first p-type buried regions (3) below first p-type well region (9)；First N-shaped well region (8) is located at the second p-type interruption island
The top in buried regions area (4)；Second N-shaped well region (10) is located at the top of the first N-shaped buried regions (6), and coupled；Second p-type trap
Area (12) is located at the top of the 3rd p-type buried regions (5), and coupled；3rd N-shaped well region (13) is located at the second N-shaped buried regions (7)
Top, and coupled；
It is provided with the first p-type contact area (15) and the first N-shaped contact zone (16) in the first p-type well region (9)；In the second N-shaped well region
(10) it is provided with the second N-shaped contact zone (17) in；It is provided with the second p-type contact area (18) and the 3rd N-shaped in the 3rd N-shaped well region (13)
Contact zone (19)；Second p-type contact area (18) and the 3rd N-shaped contact zone (19) are provided with metal (20), and pass through metal
(20) it is connected with the second N-shaped contact zone (17).
2. high-voltage driving circuit according to claim 1 isolation structure it is characterised in that: described second p-type interruption island
Shape buried regions area (4) is connected with the first p-type buried regions (3) or separates.
3. high-voltage driving circuit according to claim 1 and 2 isolation structure it is characterised in that: described second p-type interruption
Island buried regions area (4) is made up of the little buried structure of several p-types, and the number of the little buried structure of p-type is more than 1, the little buried structure of p-type
Size and mutual spacing identical or different.
4. high-voltage driving circuit according to claim 3 isolation structure it is characterised in that: described second p-type interruption island
Shape buried regions area (4) is identical by several width, the composition of the little buried regions of p-type that spacing gradual change increases.
5. high-voltage driving circuit according to claim 1 and 2 isolation structure it is characterised in that: the first p-type buried regions (3),
Second p-type is interrupted island buried regions area (4) and the concentration of the 3rd p-type buried regions (5) is identical or different；
The concentration of the first N-shaped buried regions (6) and the second N-shaped buried regions (7) is identical or different；
The concentration of the first N-shaped well region (8), the 5th N-shaped well region (11) and the 4th N-shaped well region (14) is identical or different；
The concentration of the second N-shaped well region (10) and the 3rd N-shaped well region (13) is identical or different.
6. high-voltage driving circuit according to claim 5 isolation structure it is characterised in that: the first N-shaped well region (8),
The concentration of five N-shaped well regions (11) and the 4th N-shaped well region (14) is less than or equal to the second N-shaped well region (10) and the 3rd N-shaped well region (13)
Concentration.
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| CN105336780B (en) * | 2014-08-06 | 2018-11-09 | 旺宏电子股份有限公司 | High-voltage semiconductor element |
| US10121889B2 (en) | 2014-08-29 | 2018-11-06 | Macronix International Co., Ltd. | High voltage semiconductor device |
| US9520492B2 (en) * | 2015-02-18 | 2016-12-13 | Macronix International Co., Ltd. | Semiconductor device having buried layer |
| CN106158921B (en) | 2015-04-10 | 2019-07-23 | 无锡华润上华科技有限公司 | Has the transverse diffusion metal oxide semiconductor field effect pipe of RESURF structure |
| TWI731627B (en) * | 2020-03-19 | 2021-06-21 | 新唐科技股份有限公司 | High voltage integrated circuit structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| KR100374627B1 (en) * | 2000-08-04 | 2003-03-04 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having a high breakdown voltage isolation region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
Non-Patent Citations (1)
| Title |
|---|
| 基于1μm 600V BCD工艺的高压栅驱动电路;黎俐等;《微电子学》;20130831;第43卷(第4期);第484-487页 * |
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