CN103840008B - Based on high-voltage LDMOS device and the manufacturing process of BCD technique - Google Patents
Based on high-voltage LDMOS device and the manufacturing process of BCD technique Download PDFInfo
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- CN103840008B CN103840008B CN201410126232.1A CN201410126232A CN103840008B CN 103840008 B CN103840008 B CN 103840008B CN 201410126232 A CN201410126232 A CN 201410126232A CN 103840008 B CN103840008 B CN 103840008B
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000407 epitaxy Methods 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a kind of high-voltage LDMOS device based on BCD technique and manufacturing process, high-voltage LDMOS device comprises substrate, substrate is N-type substrate, it N-type substrate is p type buried layer, it p type buried layer is N-type thin epitaxy layer, N trap is positioned at the side of N-type thin epitaxy layer, N trap is the P type light dope top layer covered by field oxide near the side of polysilicon, another side is N-type input horizon, N-type input horizon extends upwardly to drain electrode, P trap is positioned at another side of N-type thin epitaxy layer, the middle top of P trap is p-type place, p-type place has short circuit N-type input horizon and short circuit P type input horizon, the junction of short circuit N-type input horizon and short circuit P type input horizon extends upwardly to source electrode, there is grid oxic horizon the junction of N trap and P trap, it grid oxic horizon is polysilicon, the external grid of polysilicon. the withstand voltage zone length of LDMOS device of the present invention is less, can ensure that voltage breakdown significantly reduces the conducting resistance of device when constant.
Description
Technical field
The present invention relates to a kind of high-voltage LDMOS device and manufacturing process, particularly relate to a kind of high-voltage LDMOS device based on BCD technique and manufacturing process.
Background technology
BCD is a kind of single-chip integration Technology, and this kind of technology can make bipolar tube bipolar, CMOS and DMOS device on the same chip, is called BCD technique. LDMOS and LDMOS, high-voltage LDMOS device is the normal device adopted in high-voltage power integrated circuit, for meeting resistance to high pressure, realize the requirement of the aspects such as power control, is usually used in radio frequency power circuit.
What the substrate material of the existing high-voltage LDMOS device based on BCD technique was selected is p-substrate, P type substrate grows N-type epitaxy layer, and adopting singleresurf technology withstand voltage to improve, the LDMOS device performance of this kind of structure is not high, and under the prerequisite meeting voltage, conducting resistance is bigger.
Summary of the invention
The object of the present invention is just to provide a kind of high performance high-voltage LDMOS device based on BCD technique and manufacturing process to solve the problem.
The present invention is achieved through the following technical solutions above-mentioned purpose:
A kind of high-voltage LDMOS device based on BCD technique, comprise substrate, described substrate is N-type substrate, it N-type substrate is p type buried layer, it p type buried layer is N-type thin epitaxy layer, N trap is positioned at the side of N-type thin epitaxy layer, N trap is the P type light dope top layer covered by field oxide near the side of polysilicon, another side is N-type input horizon, N-type input horizon extends upwardly to drain electrode, P trap is positioned at another side of N-type thin epitaxy layer, the middle top of P trap is p-type place, p-type place has short circuit N-type input horizon and short circuit P type input horizon, the junction of short circuit N-type input horizon and short circuit P type input horizon extends upwardly to source electrode, there is grid oxic horizon the junction of N trap and P trap, it grid oxic horizon is polysilicon, the external grid of polysilicon.
Based on the manufacturing process that the high-voltage LDMOS device of BCD technique adopts, comprise the following steps:
(1) selecting to be doped to the N-type substrate of phosphorus, thickness is 0��1000um;
(2) carrying out boron to inject to form p type buried layer, energy is 0��1000kev, and dosage is 1e11��1e15/cm2;
(3) carrying out epitaxy on p type buried layer and obtain N-type thin epitaxy layer, thickness is 0��30um;
(4) carrying out phosphorus respectively to inject and boron injection, phosphorus injects energy 300kev, dosage 4e12/cm2, boron injects energy 100kev, dosage 1e13/cm2, at 1100 degree of temperature, then carry out n 2 annealing form N trap and P trap, the degree of depth of trap can with buried regions break-through;
(5) carrying out boron injection, energy is 100Kev, and dosage is 1e12/cm2, at 1000 degree of temperature, then carry out n 2 annealing form P type light dope top layer;
(6) adopting two step ion implantations to form p-type place, the first ion implantation energy is 1��200kev, and dosage is 1e11��1e15/cm2, the 2nd step ion implantation is that boron injects, and energy is 1��300kev, and dosage is 1e11��1e15/cm2;
(7) grid oxic horizon growth;
(8) polysilicon deposit, adopt LPCVD(LowPressureChemicalVaporDeposition, low pressure chemical vapour deposition) mode, square resistance scope is 1��100ohm/square;
(9) carry out N-type respectively to inject and the injection of P type, to form the ohmic contact of source electrode, drain electrode;
(10) deposited oxide layer, as inter-level dielectric;
(11) the aluminium electrode of source/drain is done;
(12) passivation layer deposit, film layer structure is PETEOS and PESIN, wherein, PETEOS refers to and adopts PECVD(PlasmaEnhancedChemicalVaporDeposition, plasma enhanced chemical vapor deposition) mode, being starting material taking TEOS, the silicon oxide layer film grown out, PESIN refers to the silicon nitride film adopting the mode of PECVD to grow out.
The useful effect of the present invention is:
LDMOS device of the present invention adopts the N-type epitaxy layer of regrowth light dope in the dense doped substrate of N-type, and it is withstand voltage to adopt OVLD technology to improve, compared with traditional LDMOS device, under prerequisite withstand voltage on an equal basis, the withstand voltage zone length of LDMOS device of the present invention is less, can ensure that voltage breakdown significantly reduces the conducting resistance of device when constant.
Accompanying drawing explanation
Fig. 1 is the structural representation of conventional high-tension LDMOS device;
Fig. 2 is the structural representation of high-voltage LDMOS device of the present invention;
Fig. 3 is structural representation after forming N trap and P trap in the high-voltage LDMOS device course of processing of the present invention;
Fig. 4 is structural representation after forming grid oxic horizon and polysilicon in the high-voltage LDMOS device course of processing of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 2, high-voltage LDMOS device based on BCD technique of the present invention, comprise substrate, described substrate is N-type substrate N-substrate, N-type substrate N-substrate is p type buried layer P-bury, it p type buried layer P-bury is N-type thin epitaxy layer, N trap N-well is positioned at the side of N-type thin epitaxy layer, N trap N-well is the P type light dope top layer P-top covered by field oxide oxide near the side of polysilicon poly, another side is N-type input horizon n+, N-type input horizon n+ extends upwardly to drain electrode drain, P trap P-well is positioned at another side of N-type thin epitaxy layer, the middle top of P trap P-well is p-type place P-field, p-type place P-field has short circuit N-type input horizon n+ and short circuit P type input horizon p+, the junction of short circuit N-type input horizon n+ and short circuit P type input horizon p+ extends upwardly to source electrode source, there is grid oxic horizon gateoxide the junction of N trap N-well and P trap P-well, grid oxic horizon gateoxide is polysilicon poly, the external grid gate of polysilicon poly.Fig. 2 also show the localized oxide locos of silicon.
The manufacturing process that high-voltage LDMOS device based on BCD technique of the present invention adopts, comprises the following steps:
(1) selecting to be doped to the N-type substrate N-substrate of phosphorus, thickness is 0��1000um;
(2) carrying out boron to inject to form p type buried layer P-bury, energy is 0��1000kev, and dosage is 1e11��1e15/cm2;
(3) carrying out epitaxy on p type buried layer P-bury and obtain N-type thin epitaxy layer, thickness is 0��30um;
(4) carrying out phosphorus respectively to inject and boron injection, phosphorus injects energy 300kev, dosage 4e12/cm2, boron injects energy 100kev, dosage 1e13/cm2, then carry out at 1100 degree of temperature n 2 annealing formed N trap N-well and P trap P-well, the degree of depth of trap can with buried regions break-through; Form the high-voltage LDMOS device after N trap N-well and P trap P-well as shown in Figure 3;
(5) carrying out boron injection, energy is 100Kev, and dosage is 1e12/cm2, at 1000 degree of temperature, then carry out n 2 annealing form P type light dope top layer P-top;
(6) adopting two step ion implantations to form p-type place P-field, the first ion implantation energy is 1��200kev, and dosage is 1e11��1e15/cm2, the 2nd step ion implantation is that boron injects, and energy is 1��300kev, and dosage is 1e11��1e15/cm2;
(7) growth of grid oxic horizon gateoxide;
(8) polysilicon poly deposit, adopts the mode of LPCVD, and square resistance scope is 1��100ohm/square; Form the high-voltage LDMOS device after grid oxic horizon gateoxide and polysilicon poly as shown in Figure 4;
(9) carry out N-type respectively to inject and the injection of P type, to form the ohmic contact of source electrode, drain electrode;
(10) deposited oxide layer locos, as inter-level dielectric;
(11) the aluminium electrode of source/drain is done;
(12) passivation layer deposit, film layer structure is PETEOS and PESIN; The high-voltage LDMOS device finally obtained is as shown in Figure 2.
As shown in Figure 1, the substrate material of conventional high-tension LDMOS device is p-substrate P-substrate, p-substrate P-substrate is p-type buried regions p-bury, and grow N-type epitaxy layer N-epi on p-substrate P-substrate, the LDMOS device performance of this kind of structure is not high, and under the prerequisite meeting voltage, conducting resistance is bigger.
Claims (1)
1. the manufacturing process that the high-voltage LDMOS device based on BCD technique adopts, the described high-voltage LDMOS device based on BCD technique comprises substrate, described substrate is N-type substrate, it N-type substrate is p type buried layer, it p type buried layer is N-type thin epitaxy layer, N trap is positioned at the side of N-type thin epitaxy layer, N trap is the P type light dope top layer covered by field oxide near the side of polysilicon, another side is N-type input horizon, N-type input horizon extends upwardly to drain electrode, P trap is positioned at another side of N-type thin epitaxy layer, the middle top of P trap is p-type place, p-type place has short circuit N-type input horizon and short circuit P type input horizon, the junction of short circuit N-type input horizon and short circuit P type input horizon extends upwardly to source electrode, there is grid oxic horizon the junction of N trap and P trap, it grid oxic horizon is polysilicon, the external grid of polysilicon, it is characterized in that: described manufacturing process comprises the following steps:
(1) selecting to be doped to the N-type substrate of phosphorus, thickness is 0��1000um;
(2) carrying out boron to inject to form p type buried layer, energy is 0��1000kev, and dosage is 1e11��1e15/cm2;
(3) carrying out epitaxy on p type buried layer and obtain N-type thin epitaxy layer, thickness is 0��30um;
(4) carrying out phosphorus respectively to inject and boron injection, phosphorus injects energy 300kev, dosage 4e12/cm2, boron injects energy 100kev, dosage 1e13/cm2, at 1100 degree of temperature, then carry out n 2 annealing form N trap and P trap, the degree of depth of trap can with buried regions break-through;
(5) carrying out boron injection, energy is 100Kev, and dosage is 1e12/cm2, at 1000 degree of temperature, then carry out n 2 annealing form P type light dope top layer;
(6) adopting two step ion implantations to form p-type place, the first ion implantation energy is 1��200kev, and dosage is 1e11��1e15/cm2, the 2nd step ion implantation is that boron injects, and energy is 1��300kev, and dosage is 1e11��1e15/cm2;
(7) grid oxic horizon growth;
(8) polysilicon deposit, adopts the mode of LPCVD, and square resistance scope is 1��100ohm/square;
(9) carry out N-type respectively to inject and the injection of P type, to form the ohmic contact of source electrode, drain electrode;
(10) deposited oxide layer, as inter-level dielectric;
(11) the aluminium electrode of source/drain is done;
(12) passivation layer deposit, film layer structure is PETEOS and PESIN.
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| US10229993B2 (en) * | 2016-03-14 | 2019-03-12 | Maxin Integrated Products, Inc. | LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods |
| CN109524395B (en) * | 2017-09-19 | 2020-09-11 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| TWI709196B (en) * | 2018-12-21 | 2020-11-01 | 新唐科技股份有限公司 | Semiconductor device and method for forming the same |
| CN110518070B (en) * | 2019-09-03 | 2022-11-15 | 深圳第三代半导体研究院 | Silicon carbide LDMOS device suitable for monolithic integration and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
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| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
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