CN102104068A - Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof - Google Patents
Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof Download PDFInfo
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- CN102104068A CN102104068A CN2009102019694A CN200910201969A CN102104068A CN 102104068 A CN102104068 A CN 102104068A CN 2009102019694 A CN2009102019694 A CN 2009102019694A CN 200910201969 A CN200910201969 A CN 200910201969A CN 102104068 A CN102104068 A CN 102104068A
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Abstract
The invention discloses an array structure of a power MOS (Metal Oxide Semiconductor) transistor. A grid electrode positioned on the drain terminal of the power MOS transistor is separated into two segments; and traps with same conduction type and body region are both arranged below each segment of the grid electrode and a source terminal. The invention also discloses a preparation method of the array structure of the power MOS transistor, comprising the following steps of: carrying out ion implantation on an epitaxial layer to form a trap, wherein the conduction type of the trap is the same as a body region of the power MOS transistor; after polycrystalline silicon is deposited, etching to remove the polycrystalline silicon positioned above the source region; carrying out the ion implantation to form the source region, and then etching to remove the polycrystalline silicon and the grid oxide positioned above the drain terminal and between the two traps and gate oxide and retain the polycrystalline silicon positioned above the traps. In the array structure, the on-state resistance of a power MOS device is far less than that of a general VDMOS (Vertical Double Diffused Metal Oxide Semiconductor) at same cut-off breakdown-resistant voltage when the power MOS device is lower than 100 V by utilizing a high-density trap array structure.
Description
Technical field
The present invention relates to a kind of structure of power MOS transistor.The invention still further relates to a kind of preparation method of power MOS transistor.
Background technology
In semiconductor integrated circuit, the array structure that has more advanced super knot (superjunction) power MOS transistor now is for being provided with a trap below source electrode, the conduction type of this trap is identical with the tagma, and the degree of depth is deeper than the tagma, and the adjacent shared same grid of two MOS transistor.In the structure of a kind of power MOS transistor like this, integration density is not high, and is much smaller than general VDMOS (vertical double-diffused MOS), but very little even completely lose to this superiority of the application below the 100V at high-voltage applications scope on state resistance.And the parasitic capacitance between grid and the drain electrode need be reduced by structure and process modification.
Summary of the invention
Technical problem to be solved by this invention provides a kind of structure of power MOS transistor, and it can improve the integration density of power MOS transistor.
For solving the problems of the technologies described above, the structure of power MOS transistor of the present invention, two sections of being set to separate for the grid on the power MOS transistor drain terminal, and be provided with the conduction type trap identical below every section grid below and the source terminal with the tagma.
The preparation method of power MOS transistor of the present invention, for: ion injects and forms trap on epitaxial loayer, and the conduction type of trap is identical with the tagma in the described power MOS transistor; After the polysilicon deposit, etching is removed the polysilicon of top, source region; And after ion injects the formation source region, carry out etching to remove the polysilicon of drain terminal top between two traps, keep the polysilicon that is positioned at the trap top.
In the structure of the present invention, utilize highdensity trap array structure, make device of the present invention when 100V is following, identical by breakdown voltage resistant following, on state resistance is much smaller than general VDMOS.Among the preparation method of the present invention, utilize two step grid etch that the grid polycrystalline silicon on the drain terminal is carved and remove simultaneously, reduce the parasitic capacitance between grid and the drain electrode.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is a power MOS transistor array structure schematic diagram of the present invention;
Fig. 2 is the structural representation after trap forms among the preparation method of the present invention;
Fig. 3 is the structural representation behind the etching polysilicon on the source region among the preparation method of the present invention;
Fig. 4 is the schematic diagram that the tagma is injected among the preparation method of the present invention;
Fig. 5 is the schematic diagram that the source region is injected among the preparation method of the present invention;
Fig. 6 is the structural representation behind the etching polysilicon of drain terminal top among the preparation method of the present invention;
Fig. 7 is the structural representation behind the contact hole etching among the preparation method of the present invention;
Current direction schematic diagram when Fig. 8 is power MOS transistor conducting of the present invention;
Fig. 9 be power MOS transistor of the present invention by the time voltage direction schematic diagram that descends.
Embodiment
The structure of power MOS transistor of the present invention, be set to separate for gate common on original power MOS transistor drain terminal two sections, being respectively single transistor uses, and every section grid below all is provided with the conduction type trap identical with the tagma with the source terminal below, the degree of depth of this trap is deeper than the tagma, is positioned at epitaxial loayer.In an instantiation, the degree of depth of trap can be 0.5～10 micron, and width can be 0.1～5 micron, and the distance between trap and the trap is preferably identical.
The preparation method of power MOS transistor of the present invention is specially:
1) define earlier the figure of trap with photoetching process, the back is adopted the ion of a step or multistep different-energy to inject on epitaxial loayer and is formed the trap (see figure 2).The conduction type of this trap is identical with the tagma in the power MOS transistor, and the degree of depth of trap is deeper than the tagma.Injection is gone photoresist can increase rapid thermal annealing afterwards and is activated the injection ion.The degree of depth of trap is preferably identical with width, and trap is preferably also identical with the spacing of trap.The ion dose that is injected is 10
12～10
15Atom/cm
2, the injection energy is 10KeV～2000KeV.The temperature of annealing in process is 400～1200 degrees centigrade, and the processing time is 10 seconds～1 hour.
2) follow deposit grid oxygen and polysilicon on epitaxial loayer.After the polysilicon deposit, etching is removed the polysilicon and the grid oxygen (see figure 3) of top, source region; Etching technics is existing conventional polysilicon and grid oxygen etching technics, makes the trap top that is positioned at the source end not have polysilicon after the etching, and the grid oxygen under the position of this removal polysilicon can not removed, and can partly remove yet or remove fully.
3) carry out ion afterwards and inject formation tagma and source region.Earlier for adopting the ion implantation technology of band angle, adopt the autoregistration ion implantation technology, forming the tagma (see figure 4) in the epitaxial loayer in the zone that does not have polysilicon to cover, then is to adopt the autoregistration ion implantation technology equally, forms the source region (see figure 5) in the epitaxial loayer that does not have polysilicon to cover.Two secondary ions can carry out annealing in process after injecting.
4) then etching is removed the polysilicon of drain terminal top between two traps, and keeps the polysilicon (see figure 6) that is positioned at above-mentioned two traps top.Grid oxygen under the position of this removal polysilicon can not removed, and can partly remove yet or remove fully.
5) be film between illuvium then, and film forms contact hole between etch layer, wherein the contact hole of source electrode need be etched to the place, tagma.
Be common process such as contact hole filling, finally form the power MOS transistor structure shown in 1 thereafter.Power MOS transistor structure of the present invention, when conducting, electric current flows to source electrode along the direction of arrow shown in Figure 8 from drain electrode; And when ending, voltage descends from drain-to-source along the direction of arrow shown in Figure 9.This power MOS construction is integrated more power MOS transistor under the situation that does not reduce puncture voltage, has reduced the on state resistance of whole power device.Because the area of drain electrode end grid polycrystalline silicon is less, the parasitic capacitance of grid～drain electrode end is corresponding to be reduced, and has so improved the operating frequency of power MOS transistor, reduces power consumption.
Claims (7)
1. the structure of a power MOS transistor is characterized in that: two sections of being set to separate of the grid on the described power MOS transistor drain terminal, and be provided with the conduction type trap identical below every section grid below and the source end with the tagma.
2. structure according to claim 1 is characterized in that: described well depth is positioned at epitaxial loayer in the tagma.
3. structure according to claim 2 is characterized in that: the degree of depth of described trap is 0.5～10 micron, and width is 0.1～5 micron.
4. the preparation method of the described power MOS transistor structure of claim 1 is characterized in that: ion injects and forms trap on epitaxial loayer, and the conduction type of described trap is identical with the tagma in the described power MOS transistor; After the polysilicon deposit, etching is removed the polysilicon of top, source region; And after ion injects the formation source region, carry out etching to remove the polysilicon of drain terminal top between two traps, keep the polysilicon that is positioned at described trap top.
5. preparation method according to claim 4 is characterized in that: described trap is finished by the ion injection of a step or multistep different-energy, and the ion dose that is injected is 10
12～10
15Atom/cm
2, the injection energy is 10KeV～2000KeV.
6. preparation method according to claim 4 is characterized in that: carry out annealing in process after the injection, the temperature of annealing in process is 400～1200 degrees centigrade, and the processing time is 10 seconds～1 hour.
7. preparation method according to claim 4 is characterized in that: also be included in the etching in end in contact hole, follow-up source, the contact hole etching of described source electrode is to the tagma.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009102019694A CN102104068A (en) | 2009-12-18 | 2009-12-18 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
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| CN2009102019694A CN102104068A (en) | 2009-12-18 | 2009-12-18 | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254828A (en) * | 2011-07-18 | 2011-11-23 | 无锡新洁能功率半导体有限公司 | Method for making semiconductor device with super junction structure and rapid reverse recovery characteristic |
| CN102254937A (en) * | 2011-08-08 | 2011-11-23 | 深圳深爱半导体股份有限公司 | Vertical double-diffused metal-oxide-semiconductor field effect transistor device and manufacturing method thereof |
| CN102332396A (en) * | 2011-10-27 | 2012-01-25 | 博嘉圣（福州）微电子科技有限公司 | Method for designing power vertical double-diffused metal-oxide-semiconductor field effect transistor (VDMOSFET) structure |
| CN103236439A (en) * | 2013-04-22 | 2013-08-07 | 无锡新洁能股份有限公司 | VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in novel structure and manufacture method of VDMOS device |
| CN106549056A (en) * | 2015-09-22 | 2017-03-29 | 大中积体电路股份有限公司 | Bigrid groove-type power transistor and its manufacture method |
| CN108878275A (en) * | 2017-05-10 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
-
2009
- 2009-12-18 CN CN2009102019694A patent/CN102104068A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254828A (en) * | 2011-07-18 | 2011-11-23 | 无锡新洁能功率半导体有限公司 | Method for making semiconductor device with super junction structure and rapid reverse recovery characteristic |
| CN102254937A (en) * | 2011-08-08 | 2011-11-23 | 深圳深爱半导体股份有限公司 | Vertical double-diffused metal-oxide-semiconductor field effect transistor device and manufacturing method thereof |
| CN102254937B (en) * | 2011-08-08 | 2013-08-07 | 深圳深爱半导体股份有限公司 | Vertical double-diffused metal-oxide-semiconductor field effect device and manufacturing method thereof |
| CN102332396A (en) * | 2011-10-27 | 2012-01-25 | 博嘉圣（福州）微电子科技有限公司 | Method for designing power vertical double-diffused metal-oxide-semiconductor field effect transistor (VDMOSFET) structure |
| CN103236439A (en) * | 2013-04-22 | 2013-08-07 | 无锡新洁能股份有限公司 | VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in novel structure and manufacture method of VDMOS device |
| CN103236439B (en) * | 2013-04-22 | 2015-06-17 | 无锡新洁能股份有限公司 | VDMOS (vertical double-diffusion metal-oxide-semiconductor) device in novel structure and manufacture method of VDMOS device |
| CN106549056A (en) * | 2015-09-22 | 2017-03-29 | 大中积体电路股份有限公司 | Bigrid groove-type power transistor and its manufacture method |
| CN106549056B (en) * | 2015-09-22 | 2019-07-30 | 大中积体电路股份有限公司 | Bigrid groove-type power transistor and its manufacturing method |
| CN108878275A (en) * | 2017-05-10 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
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Application publication date: 20110622 |