CN102263107A - Semiconductor power device and manufacturing method thereof - Google Patents
Semiconductor power device and manufacturing method thereof Download PDFInfo
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- CN102263107A CN102263107A CN 201010190248 CN201010190248A CN102263107A CN 102263107 A CN102263107 A CN 102263107A CN 201010190248 CN201010190248 CN 201010190248 CN 201010190248 A CN201010190248 A CN 201010190248A CN 102263107 A CN102263107 A CN 102263107A
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Abstract
The invention discloses a trench metal-oxide semiconductor field-effect transistor device which comprises a plurality of closed trench metal-oxide semiconductor field-effect transistor units and a closed unit structure, wherein the plurality of closed trench metal-oxide semiconductor field-effect transistor units are surrounded by trench gates, and the closed unit structure forms a square or rectangle inside an active region. In addition, the terminal area of the device comprises a plurality of trench rings with suspended voltages so as to increase the puncture voltage of the device.
Description
Technical field
The present invention relates to a kind of unit structure of semiconductor power device, device architecture and manufacture method.Be particularly related to a kind of unit structure, device architecture and improved manufacture method of groove metal oxide semiconductor field effect pipe of novelty.
Background technology
Along with the raising of the cell density (cell density) of semiconductor power device, be badly in need of new device architecture to reduce source ohmic leakage (Rds).Simultaneously, in order to make semiconductor power device have range of application more widely, reducing of Rds can not be cost with the reliability and the reduction puncture voltage of sacrificing device.And conventional designing technique and device architecture become when satisfying above-mentioned requirements and have challenge, especially under the cell density of semiconductor power device surpasses per square inch 600,000,000 situation.
In U.S. Patent No. 6,462, in 376, disclosed a kind of DMOS (double-diffused metal oxide semiconductor) device with striped cell (stripe cell) structure that utilizes the manufacturing of tri-layer masking plate (mask) technology, this device adopts has the ditch grooved ring of suspension voltage as the termination environment.Figure 1A and Figure 1B show the vertical view and the sectional view of this device respectively.All there is certain drawback in this device with striped cell structure on cellular construction and technology.At first, the striped cell structure is compared with closed cell (closedcell) structure, and the former has bigger source ohmic leakage (Rds); In addition, utilize the N channel device of this tri-layer masking plate technology manufacturing can make the termination environment of device and groove grid region all form a n+ doped region, and can reduce the reliability of device by the caused breech lock of parasitic N+PN bipolar transistor (latch-up) effect that this n+ doped region forms.When device is opened, being positioned near the active area in groove grid region will at first be unlocked, and then very easily trigger parasitic N+PN bipolar transistor, thereby device is caused potential injury.Simultaneously, because there is higher electric field in device corner, very easily be subjected to the damage that causes by the N+PN bipolar transistor that triggers this parasitism.For this reason, introduce one deck source region mask plate usually and near the trench gate of device corner, form a dummy argument (dummy cell) that does not have the n+ doped region.In non-clamper inductive switch (UIS) test, can produce damage because of voltge surge in device corner, the dummy argument of corner can be avoided the appearance of this damage at this moment.
In addition, also there is the another one shortcoming in the prior art: because n+ doped region and P type tagma all formed before trench gate, when the cell density of device surpasses per square inch 1.12 hundred million unit (when just the unit interval of device is lowered to 2.4 microns), break-through (punch-through) problem almost is inevitable.This is because the generation of break-through problem comes from the poly-partially phenomenon of the boron of sacrificial oxide layer and gate oxide.Near the boron of assembling channel region can cause the reduction of channel region doping content, and then makes the possibility of drain-source reverse bias lower channel district's break-through increase.
Therefore, the new unit structure that can solve an above-mentioned difficult problem and design limit, device architecture and technology manufacturing process, for the manufacturing of semiconductor power device, especially particularly important to the design and the manufacturing of groove type power mos field effect transistor (MOSFET).Particularly, if can overcome above-mentioned technical barrier in the lower gate resistance of maintenance, the cell density of trench semiconductor power device can also further increase so.
Summary of the invention
The above-mentioned obstacle of the prior art with other is solved by power semiconductor of the present invention.
According to embodiments of the invention, a kind of semiconductor power device is provided, comprising:
(a) a plurality of power transistor cell that are positioned at the sealing of active area, this power transistor unit form are formed on the Semiconductor substrate, and wherein each described power transistor cell is centered on by trench gate, form the closed cell of square or rectangle;
(b) a plurality of ditch grooved rings that are positioned at the termination environment with suspension voltage, described termination environment is formed at around the described active area;
(c) tagma is positioned at described active area and described termination environment;
(d) described trench gate further extend to comprise contact trench grid, these contact trench grid be used to form with the grid metal level between electric the contact, and the width of these contact trench grid is greater than the width of the trench gate that is positioned at described active area;
(e) source region, this source region are positioned at the described active area of the power transistor cell with described sealing, away from the described termination environment with a plurality of suspension ditch grooved rings.
In some preferred embodiments, described power transistor cell further comprises the N raceway groove groove metal oxide semiconductor field effect pipe unit of sealing, and described source region further is included as the source region of N+ doping type, and the source region of this N+ doping type is positioned at described active area and away from described termination environment.In other preferred embodiments, described power transistor cell further comprises the P groove metal oxide semiconductor field effect pipe unit of sealing, and described source region further comprises the source region of P+ doping type, and the source region of this P+ doping type is positioned at described active area and away from described termination environment.
In some preferred embodiments, described semiconductor power device further comprises: one deck covers insulating barrier and a plurality of plough groove type source-body contact zone that passes this insulating barrier of described semiconductor power device, this plough groove type source-body contact zone passes described source region then and extends into described tagma, in this plough groove type source-body contact zone filling source-body contact plunger with form with described source region and described tagma between electric the contact; A plurality of plough groove type gate contact zones that pass described insulating barrier, this plough groove type gate contact zone extends into described contact trench grid, fill in this plough groove type gate contact zone the grid contact plunger with form with described contact trench grid between electric the contact.More preferably, above-mentioned semiconductor power device further comprises source metal level and grid metal level, and the two all is positioned at the upper surface of described insulating barrier, and forms electric the contact respectively with between described source-body contact plunger and the described grid contact plunger.
In some preferred embodiments, the termination environment of described semiconductor power device comprises the ditch grooved ring of at least three suspensions.
In some preferred embodiments, the distance between per two adjacent grooves rings of the termination environment of described semiconductor power device equates.In other preferred embodiments, the distance between per two adjacent grooves rings of the termination environment of described semiconductor power device is unequal.
In some preferred embodiments, the power transistor cell of described sealing further comprises the N raceway groove groove metal oxide semiconductor field effect pipe of the sealing on the substrate that is formed at doping red phosphorus.
In some preferred embodiments, described semiconductor power device further comprises the leakage metal level, it is positioned at the lower surface of described Semiconductor substrate, and described trench gate and described source region be positioned at the upper surface of this Semiconductor substrate, is relative between upper surface and the lower surface wherein.
According to another aspect of the present invention, provide another kind of semiconductor power device, having comprised:
(a) the P raceway groove groove metal oxide semiconductor field effect pipe unit of the N raceway groove groove metal oxide semiconductor field effect pipe unit of a plurality of sealings or a plurality of sealings, this groove metal oxide semiconductor field effect pipe unit is centered on by trench gate, is formed with the closed cell structure of square in the source region or rectangle;
(b) described trench gate further extend to comprise contact trench grid, these contact trench grid be used to form with the grid metal level between electric the contact, and the width of these contact trench grid is greater than the width of the trench gate that is positioned at described active area;
(c) be positioned at least 3 ditch grooved rings of termination environment with suspension voltage;
(d) tagma is positioned at described active area and described termination environment;
(e) source region is positioned at described active area and away from described termination environment;
(f) one deck covers insulating barrier and a plurality of plough groove type source-body contact zone that passes this insulating barrier of described semiconductor power device, this plough groove type source-body contact zone passes described source region then and extends into described tagma, in this plough groove type source-body contact zone filling source-body contact plunger with form with described source region and described tagma between electric the contact;
(g) source metal level, morpheme are in the upper surface of described insulating barrier, with electric contact of formation between described source-body contact plunger; With
(h) leak metal level, be positioned at the lower surface of described Semiconductor substrate.
According to another aspect of the present invention, provide a kind of manufacture method of semiconductor power device, having comprised:
(a) power transistor cell of a plurality of sealings of formation, the power transistor cell of each this sealing is centered on by trench gate, forms the closed cell structure of the square or the rectangle that are arranged in active area;
(b) provide one deck source region mask plate to make the source region be formed in the power transistor cell of described sealing and away from contact trench grid and termination environment.
The manufacture method of described semiconductor power device, the wherein said step that the active region mask plate is provided further comprises provides the active region mask plate to make the source region away from the termination environment with a plurality of suspension groove ring structures.
The manufacture method of described semiconductor power device further comprises: form a plough groove type source-body contact zone, this plough groove type source-body contact zone is positioned at the centre of the power transistor cell of described sealing, and pass insulating barrier and described source region that one deck covers described semiconductor power device, extend into the tagma of below, described source region, filling source-body contact plunger in this plough groove type source-body contact zone.More preferably, the manufacture method of described semiconductor power device further comprises: deposit source metal level on described insulating barrier, form with described source-body contact plunger between electric the contact.
In the manufacture method of described semiconductor power device, the step of the power transistor cell of a plurality of sealings of described formation further is included in the step that forms the described groove metal oxide semiconductor field effect pipe of N raceway groove of sealing on the substrate of doping red phosphorus.
In the manufacture method of described semiconductor power device, the step of the power transistor cell of a plurality of sealings that centered on by trench gate of described formation further comprises and forms a plurality of ditch grooved rings.
An advantage of the invention is that the power transistor cell with closed cell structure according to the present invention is compared with the power transistor cell with striped cell structure, the former has higher packaging density and lower Rds.
Another advantage of the present invention is, power transistor cell according to the sealing of the described semiconductor power device of formation of the present invention is surrounded by trench gate, and the centre of the power transistor cell of each sealing all has the source-body contact zone of a plough groove type, meeting the minimum spacing that also guarantees when characteristic size requires between trench gate and the source-body contact zone, this structure has reduced Rds effectively.
Another advantage of the present invention is, in the semiconductor power device that constitutes by the power transistor cell of above-mentioned sealing of the present invention, residing position, source region is away from described contact trench grid, simultaneously also away from the termination environment of turning, edge and the device of device, thereby improved the reliability of device.
Another advantage of the present invention is, in above-mentioned semiconductor power device of the present invention, the preparation in tagma and source region is carried out after trench gate forms, and has therefore avoided in the trench etch process damage that may cause device, while also to prevent the break-through problem that is caused by this damage.
Another advantage of the present invention is, adopts a plurality of suspension groove ring structures according to the termination environment of above-mentioned groove metal oxide semiconductor field effect tube of the present invention, improved the puncture voltage of terminal.Owing to saved the tagma mask plate, manufacturing cost is minimized simultaneously.
Another advantage of the present invention is, in making N channel groove metallic oxide semiconductor field effect tube, preferably adopt the substrate that mixes by red phosphorus, make the resistivity of substrate be lower than the substrate of traditional arsenic doping, this method has further reduced the source ohmic leakage, has improved the performance of groove metal oxide semiconductor field effect pipe.
The advantage of technical scheme of the present invention and other execution mode will be by the detailed description below in conjunction with accompanying drawing, so that those of ordinary skill in the art understands.
Description of drawings
Figure 1A and Figure 1B are respectively the vertical view and the cutaway view of a groove MOSFET that has the striped cell structure in the prior art.
Fig. 1 C is a chart of analyzing the packaging density of the groove MOSFET with striped cell structure.
Fig. 2 A and Fig. 2 B are respectively cutaway view and the vertical view according to groove MOSFET of the present invention.
Fig. 2 C is the curve chart of groove MOSFET termination environment puncture voltage and ditch grooved ring number relation.
Fig. 3 A is for analyzing the chart have according to the packaging density of the groove MOSFET of closed cell structure of the present invention.
Fig. 3 B is packaging density and a cell size curve chart relatively between striped cell structure and the closed cell structure.
Fig. 4 A is according to the cutaway view of the method for groove MOSFET of the present invention shown in the shop drawings 2A to Fig. 4 E.
Embodiment
Illustrate in greater detail the present invention with reference to the accompanying drawings, wherein show the preferred embodiments of the present invention.The present invention can embody in a different manner, should not be confined to embodiment described herein.For example, N-channel MOS FET device is quoted in the explanation here more, but clearly other device also is possible.
Show according to a preferred embodiment of the present invention cutaway view and vertical view respectively with reference to Fig. 2 A and 2B.Among this embodiment, a N raceway groove groove metal oxide semiconductor field effect pipe (MOSFET) device 100 forms on N+ substrate 105, and has N type epitaxial loayer 110.This MOSFET device comprises trench gate 120, and this trench gate is positioned at the groove that an inner surface is lined with gate insulation layer 115.P type tagma 125 is between trench gate 120, and this P type tagma 125 comprises N+ source region 130, and this N+ type source region 130 is near the upper surface in P type tagmas 125 and round trench gate 120.The upper surface of epitaxial loayer is covered by one deck NSG or BPSG insulating barrier 135.Source metal level 140-S and grid metal level 140-G are positioned at the top of insulating barrier 135.
In order further to improve and the contacting of N+ source region 130, this device has adopted a plurality of plough groove types source-body contact zone, and in groove one deck by Ti filling tungsten plug 145 on the barrier layer that constitutes of TiN.Simultaneously, these plough groove type source-body contact zones pass NSG or BPSG insulating barrier 135 and N+ source region 130 and electric contact of P type tagma 125 formation.In addition, the body contact zone 150 that below, bottom, these plough groove type sources-body contact zone has a p+ to mix is to strengthen electric contact the between tungsten plug 145 and N+ source region 130 and the P type tagma 125.Afterwards, the resistance layer 155 of falling of one deck low-resistivity is covered in the upper surface of device to contact these plough groove type source-body contact zones, and at this resistance layer 155 upper surfaces fall, form one deck by Al, Al-Cu, AlCuSi or Ni/Ag, Al/NiAu, the top metal layer 140-S that AlCu/NiAu or AlCuSi/NiAu form, this metal level is used as trace layer.Therefore, the conductive layer 155 of low-resistivity is sandwiched between the top of top metal layer 140-S and plough groove type source-body contact zone, since such one, owing to increased the area of electric contact, contact resistance is minimized.
With the termination environment position adjacent, the contact trench grid 120-W of a broad is arranged, form electric the contact by the tungsten plug in the plough groove type gate contact zone 146 with grid metal level 140-G.N+ source region 130 is away from the contact trench grid 120-W of this broad, simultaneously away from the termination environment relative with active area to improve the reliability of device.
For further reduction source ohmic leakage Rds, designed a kind of cellular construction of sealing, its vertical view is shown in Fig. 2 B.Active area comprises a plurality of MOSFET unit, for example, and closed cell 151 and around the trench gate 120 of closed cell 151.N+ source region 130 is away from the contact trench grid 120-W of broad, away from the turning and the edge of device, simultaneously away from the reliability of termination environment with the raising device.Because the termination environment has the ditch grooved ring 120-R of suspension, the puncture voltage of device is improved, shown in Fig. 2 C.Can describe as the back, mask plate has been used in the manufacturing of device 100 4 times, after the growth of the etching groove that is formed on trench gate, sacrificial oxide layer and the grid oxic horizon in P type tagma 125 and N+ source region 130, therefore can avoid the appearance of break-through problem.And why can avoid the break-through problem, and be because this manufacture craft can effectively be avoided in the growth course of sacrificial oxide layer and grid oxic horizon, the poly-partially phenomenon of boron that produces to the diffusion process of oxide layer by near the platform channel region.Fig. 2 C is depicted as the curve chart that concerns between the ditch grooved ring 120-R that shows puncture voltage (BV) and suspend.Describe as Fig. 2 C, owing to used the ditch grooved ring that suspends more than 3, and the groove rim bearing of each suspension is subjected to the bias voltage of about 10V, and the breakdown potential of device has been pressed with the raising that is showing, in the conventional semiconductors power device, it is the same using dull and stereotyped resulting puncture voltage.
The closed cell structure has the another one advantage in the groove MOSFET described in the invention, and promptly this closed cell structure has higher packaging density and littler unit interval.Fig. 1 C and Fig. 3 A are depicted as the contrast of packaging density between striped cell structure and the closed cell structure.Fig. 3 B further shows between striped cell structure and the closed cell structure, and the analysis between packaging density and the unit interval relatively.The result of these two comparisons clearly demonstrates closed cell structure described in the invention and has higher packaging density and littler unit interval.
The process of the groove MOSFET shown in the shop drawings 2A will be described below, with reference to Fig. 4 A～4E, the N doped epitaxial layer 110 of at first on the substrate 105 that N+ mixes, growing.Trench mask plate (not shown) is provided subsequently; and the epitaxial loayer silicon materials are never removed in the place of mask protection, with the groove 108 that is formed for being manufactured with the source region trench gate, near the contact trench 108-W of the broad of termination environment and the groove 108-R of termination environment ditch grooved ring.In a preferred embodiment, the N+ substrate can be preferably red phosphorus and mix, because the solid solubility of red phosphorus in silicon is higher than the solubility of arsenic in silicon, can obtain less resistivity so use red phosphorus to mix.For the substrate of arsenic doping, maximum resistivity can reach 3mohm-cm, and still for the substrate of red phosphorus doping, resistivity is about 1.5mohm-cm or littler.
Subsequently, growth one deck sacrificial oxide layer (not shown) covers the inner surface of groove 108,108-W and 108-R, is used for eliminating the infringement that the process at etching groove may cause silicon epitaxy layer.This sacrificial oxide layer is removed subsequently, and another layer oxide layer 115 of growing on its position, and this oxide layer 115 becomes the grid oxic horizon of finishing device, shown in Fig. 4 A.
In Fig. 4 B, groove 108,108-W and 108-R are filled by polysilicon layer, and the upper surface of epitaxial loayer also is capped, and with N+ type dopant this polysilicon that mixes.Subsequently, this polysilicon is returned to be carved, for example, and by multi crystal silicon chemical mechanical polishing method or polysilicon dry etching.At this moment, active area trench gate 120, the trench gate 120-W of broad that is used to connect the grid metal level and the ditch grooved ring 120-R of termination environment form.Next, make P type tagma 125 be formed at epitaxial loayer 110 by the injection of P type ion with in the high temperature diffusion.
In Fig. 4 C, at first apply one deck source region mask plate 128, be diffused in the formation N+ source region, 125 tops, P type tagma 130 of active area subsequently by injection of high concentration N type ion and high temperature.Here why apply source region mask plate 128, purpose is to make the contact trench grid 120-W of source region 130 away from the broad that will link to each other with the grid metal level.And, source region 130 simultaneously also away from termination environment and device corner to guarantee the reliability of device.
In Fig. 4 D, after removing source region mask plate 128, at the upper surface difference deposit unadulterated silication glass of one deck (NSG) and the insulating barrier 135 of one deck boron-phosphorosilicate glass (BPSG) of device to form a bed thickness.Afterwards, on this insulating barrier 135, apply one deck contact trench mask plate (not shown), and the part of etching and the not masked plate protection of removal, to form contact trench.For example, source-body contact trench 145-1 by oxide layer etching break-through BPSG and NSG layer 135, makes source-body contact trench extend into source region 130 and tagma 125 by silicon etching earlier then; Grid contact trench 146-1 by oxide layer etching break-through insulating barrier 135, extends among the trench gate 120-W of broad the grid contact trench by etching polysilicon earlier then.Above-mentioned oxide layer etching and silicon etching can be dry etchings, so that the critical dimension (CD) of source-body contact trench and grid contact trench can be well controlled.Subsequently, the upper surface of device being carried out the BF2 ion injects and forms source-body contact zone 150 that the p+ that is positioned at source-below, body contact trench 145-1 bottom mixes.
In Fig. 4 E, first deposit one deck Ti/TiN forms one deck barrier layer at contact trench inner surface and insulating barrier 135 upper surfaces, fills contact trench with tungsten plug then.Subsequently, the Ti/TiN and the tungsten of deposit is returned quarter, make Ti/N and tungsten plug only be present in contact trench 145-1 and the 146-1 to form source-body contact plunger 145 and grid contact plunger 146 respectively.Afterwards, thus make it cover insulating barrier 135 and the conduction surface that increases electric current that links to each other with the contact zone of plough groove type reduces contact resistance at device upper surface deposit one deck low resistivity metal layer 155.The metal level 155 of above-mentioned low-resistivity can be made up of Ti or Ti/TiN and guarantees good electric contact performance.Next,, apply layer of metal mask plate (not shown) simultaneously, will not have the metal level of masked plate protection to remove, make it become source region metal level 140-S and grid metal level 140-G at the metal level of metal level 155 upper surface deposit one decks by the Ti/Al alloy composition.
Although various embodiment have been described at this, be appreciated that without departing from the spirit and scope of the present invention, by above-mentioned guidance, can make various modifications to the present invention.For example; can form structure of phase conduction type and the various semiconductor regions of opposite conduction type described in the literary composition or the like with method of the present invention; all should be included within the scope of desire protection of the present invention, protection scope of the present invention should be as the criterion according to the content that claim defined.
Claims (18)
1. semiconductor power device comprises:
A plurality of power transistor cell that are positioned at the sealing of active area, this power transistor cell are formed on the Semiconductor substrate, and wherein each described power transistor cell is centered on by trench gate, form the closed cell of square or rectangle;
A plurality of ditch grooved rings that are positioned at the termination environment with suspension voltage, described termination environment is formed at around the described active area;
The tagma is positioned at described active area and described termination environment;
Described trench gate further extend to comprise contact trench grid, these contact trench grid be used to form with the grid metal level between electric the contact, and the width of these contact trench grid is greater than the width of the trench gate that is positioned at described active area;
Source region, this source region are positioned at the described active area of the power transistor cell with described sealing, away from the described termination environment with a plurality of suspension ditch grooved rings.
2. semiconductor power device according to claim 1, the power transistor cell of wherein said sealing further comprises the N raceway groove groove metal oxide semiconductor field effect pipe unit of sealing, and described source region further comprises the source region of N+ doping type, and the source region of this N+ doping type is positioned at described active area and away from described termination environment.
3. semiconductor power device according to claim 1, the power transistor cell of wherein said sealing further comprises the P raceway groove groove metal oxide semiconductor field effect pipe unit of sealing, and described source region further comprises the source region of P+ doping type, and the source region of this P+ doping type is positioned at described active area and away from described termination environment.
4. semiconductor power device according to claim 1 further comprises:
One deck covers insulating barrier and a plurality of plough groove type source-body contact zone that passes this insulating barrier of described semiconductor power device, this plough groove type source-body contact zone passes described source region then and extends into described tagma, in this plough groove type source-body contact zone filling source-body contact plunger with form with described source region and described tagma between electric the contact; With
A plurality of plough groove type gate contact zones that pass described insulating barrier, this plough groove type gate contact zone extends into described contact trench grid, fill in this plough groove type gate contact zone the grid contact plunger with form with described contact trench grid between electric the contact.
5. semiconductor power device according to claim 4 further comprises:
Source metal level and grid metal level all are positioned at the upper surface of described insulating barrier, form electric the contact respectively with between described source-body contact plunger and the described grid contact plunger.
6. semiconductor power device according to claim 1 comprises the ditch grooved ring of at least 3 suspensions in the wherein said termination environment.
7. semiconductor power device according to claim 1, wherein the distance between per two adjacent grooves rings of described termination environment equates.
8. semiconductor power device according to claim 1, wherein the distance between per two the adjacent grooves rings in described termination environment is unequal.
9. semiconductor power device according to claim 1, the power transistor cell of wherein said sealing further comprise the N raceway groove groove metal oxide semiconductor field effect pipe unit of the sealing on the substrate that is formed at doping red phosphorus.
10. semiconductor power device according to claim 1 further comprises:
Leak metal level, be positioned at the lower surface of described Semiconductor substrate, and described trench gate and described source region be positioned at the upper surface of this Semiconductor substrate, wherein upper surface is relative with lower surface.
11. a groove metal oxide semiconductor field effect pipe comprises:
The P raceway groove groove metal oxide semiconductor field effect pipe unit of the N raceway groove groove metal oxide semiconductor field effect pipe unit of a plurality of sealings or a plurality of sealings, this groove metal oxide semiconductor field effect pipe unit is centered on by trench gate, is formed with the closed cell structure of square in the source region or rectangle;
Described trench gate further extend to comprise contact trench grid, these contact trench grid be used to form with the grid metal level between electric the contact, and the width of these contact trench grid is greater than the width of the trench gate that is positioned at described active area;
Be positioned at least 3 ditch grooved rings of termination environment with suspension voltage;
The tagma is positioned at described active area and described termination environment;
The source region is positioned at described active area and away from described termination environment;
One deck covers insulating barrier and a plurality of plough groove type source-body contact zone that passes this insulating barrier of described semiconductor power device, this plough groove type source-body contact zone passes described source region then and extends into described tagma, in this plough groove type source-body contact zone filling source-body contact plunger with form with described source region and described tagma between electric the contact;
The source metal level is positioned at the upper surface of described insulating barrier, and forms electric the contact between described source-body contact plunger; With
Leak metal level, be positioned at the lower surface of described Semiconductor substrate.
12. semiconductor power device according to claim 11, the N raceway groove groove metal oxide semiconductor field effect pipe unit of wherein said sealing is formed on the substrate of doping red phosphorus.
13. the manufacture method of a semiconductor power device comprises:
Form the power transistor cell of a plurality of sealings, the power transistor cell of each this sealing is centered on by trench gate, forms the closed cell structure of the square or the rectangle that are arranged in active area;
Provide one deck source region mask plate to make the source region be formed in the power transistor cell of described sealing and away from contact trench grid and termination environment.
14. the manufacture method of semiconductor power device according to claim 13, the wherein said step that the active region mask plate is provided further comprises provides the active region mask version to make the source region away from the termination environment with a plurality of suspension groove ring structures.
15. the manufacture method of semiconductor power device according to claim 14 further comprises:
Form a plough groove type source-body contact zone, this plough groove type source-body contact zone is positioned at the centre of the power transistor cell of described sealing, and pass insulating barrier and described source region that one deck covers described semiconductor power device, extend into the tagma of below, described source region, filling source-body contact plunger in this plough groove type source-body contact zone.
16. the manufacture method of semiconductor power device according to claim 15 further comprises:
Deposit source metal level on described insulating barrier, form with described source-body contact plunger between electric the contact.
17. the manufacture method of semiconductor power device according to claim 13, the step of the power transistor cell of a plurality of sealings of wherein said formation further is included on the substrate of doping red phosphorus, forms the N raceway groove groove metal oxide semiconductor field effect pipe unit of sealing.
18. further comprising, the manufacture method of semiconductor power device according to claim 13, the step of the power transistor cell of a plurality of sealings that centered on by trench gate of wherein said formation form a plurality of ditch grooved rings.
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| CN103295911A (en) * | 2013-05-13 | 2013-09-11 | 成都瑞芯电子有限公司 | Power MOSFET (metal-oxide-semiconductor field effect transistor) trench terminal structure and manufacturing method thereof |
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| CN103928513A (en) * | 2013-01-15 | 2014-07-16 | 无锡华润上华半导体有限公司 | Groove DMOS device and manufacturing method thereof |
| CN110429130A (en) * | 2019-08-31 | 2019-11-08 | 电子科技大学 | The groove profile device terminal structure of charge balance |
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| CN103515416A (en) * | 2012-06-26 | 2014-01-15 | 比亚迪股份有限公司 | Chip structure and manufacturing method thereof |
| CN103515416B (en) * | 2012-06-26 | 2016-11-23 | 比亚迪股份有限公司 | A kind of chip structure and preparation method thereof |
| CN103928513A (en) * | 2013-01-15 | 2014-07-16 | 无锡华润上华半导体有限公司 | Groove DMOS device and manufacturing method thereof |
| WO2014110977A1 (en) * | 2013-01-15 | 2014-07-24 | 无锡华润上华半导体有限公司 | Trench dmos device and manufacturing method thereof |
| US9401422B2 (en) | 2013-01-15 | 2016-07-26 | Csmc Technologies Fabi Co., Ltd. | Trench DMOS device with reduced gate resistance and manufacturing method thereof |
| CN103928513B (en) * | 2013-01-15 | 2017-03-29 | 无锡华润上华半导体有限公司 | A kind of trench-dmos devices and preparation method thereof |
| CN103280452A (en) * | 2013-05-13 | 2013-09-04 | 成都瑞芯电子有限公司 | Quantum-field distributed Trench MOSFET (metallic oxide semiconductor field effect transistor) trench termination structure and manufacturing method |
| CN103295911A (en) * | 2013-05-13 | 2013-09-11 | 成都瑞芯电子有限公司 | Power MOSFET (metal-oxide-semiconductor field effect transistor) trench terminal structure and manufacturing method thereof |
| CN110429130A (en) * | 2019-08-31 | 2019-11-08 | 电子科技大学 | The groove profile device terminal structure of charge balance |
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