CN102901524A - Low-noise low-offset voltage hall sensor - Google Patents
Low-noise low-offset voltage hall sensor Download PDFInfo
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- CN102901524A CN102901524A CN2011102141797A CN201110214179A CN102901524A CN 102901524 A CN102901524 A CN 102901524A CN 2011102141797 A CN2011102141797 A CN 2011102141797A CN 201110214179 A CN201110214179 A CN 201110214179A CN 102901524 A CN102901524 A CN 102901524A
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Abstract
The invention provides a low-noise low-offset voltage hall sensor which comprises hall elements, wherein the hall elements are circular, and each hall element comprises an N type epitaxial layer deposited on an N type wafer and a circular high-voltage P trap isolating ring formed on the N type wafer. According to the hall sensor with the structure, the four circular hall elements are connected with one another in parallel and centrally and symmetrically arranged and designed, so that the offset voltage can be greatly reduced, and the consistency of the hall elements can be improved.
Description
Technical field
The present invention relates to Hall element, specifically, relate to the Hall element that reduces Hall element offset voltage and shielding noise.
Background technology
As everyone knows, adopt Hall element that silicon materials make can with the microelectronic integrated circuit technical compatibility, can consist of together various functional circuits with various guarantee circuit and signal processing circuit are integrated.Hall element has a very wide range of applications in commercial production, communications and transportation and daily life.Many experts are absorbed in the offset voltage that reduces Hall element, the consistance that improves Hall, raising Hall coefficient, sensitivity, the technology that noise decrease disturbs studied.Wherein, be one of important technology that improves the Hall element performance by improvement Hall element layout design.
In order to reduce offset voltage, in the layout design of Hall element, extensively adopt the layout-design of four square Hall element arrays of symmetry, as depicted in figs. 1 and 2.Such layout-design can make the mismatches such as offset error, mechanical pressure cancel each other, and reduces offset voltage.Most Hall element mainly is to make with square configuration.But because the heterogeneity of square Hall element in photoetching, etching, diffusion and ion implantation process can not guarantee that the height of device is consistent.The matching of square Hall element does not have the matching of circular Hall element good, and the bad coupling of square Hall element has increased the offset voltage of Hall element.
The noise of Hall element also is Layout Design Engineer's problems of concern always.Present Hall element layout design widespread use P type shading ring noise isolation.But because the P+ injection is more shallow, noise is easy to cross shading ring, disturbs the normal operation of Hall element.
Summary of the invention
The object of the present invention is to provide a kind of Hall element of low-noise low-offset voltage, so that Hall element has higher Hall coefficient, less noise, lower offset voltage.
In order to achieve the above object, the present invention adopts following technical scheme:
The Hall element of low-noise low-offset voltage comprises Hall element, and described Hall element is circular, is included in the N-type epitaxial loayer that deposit forms on the N-type wafer and the circular shading ring that forms at the N-type wafer.
The Hall element of said structure owing to adopting four layout-designs that circular Hall element is connected in parallel, greatly reduces offset voltage, improves the consistance of Hall element.Compare with the Hall element layout design in past, the present invention mainly contains the technological improvement of three aspects::
The first, noise decrease disturbs.Many layout design personnel are at the artwork distributing that carries out Hall element, normally Hall element are placed in the middle of the chip, all around around the circuit devcie of Hall element service.What do not allow to ignore is, when the circuit devcie that produces large noise during near Hall element, noise crosstalk interference can have a strong impact on the normal operation of Hall element.People have two kinds of methods usually for the impact of noise decrease: or allow Hall device and Hall element all around keep certain distance as far as possible, or around Hall element, surround wider epitaxial loayer.The invention provides a kind of technology of new shielding noise Hall element, adopted high pressure P trap shading ring, circle hole protection ring and a metal screen layer, noise decrease disturbs and noise coupling greatly.
The second, reduce offset voltage.Circular figure can balance out device in plate-making, and photoetching is injected, the heterogeneity in the diffusion process, the consistance of retainer member height, thereby the offset voltage of reduction device.In the layout design of Hall element, adopt the Central Symmetry layout-design of four Hall element arrays, the mismatches such as offset error, mechanical pressure are cancelled each other, reduce offset voltage.
The 3rd, improve Hall coefficient, adopt circular configuration to reduce the equiva lent impedance of hall plate, improved the electric current that flows to ground in the hall plate from power supply.According to the Hall coefficient computing formula as can be known, this will improve the Hall coefficient of hall plate.The Hall coefficient computing formula is R
H=ρ u
n, wherein, R
HBe Hall coefficient, ρ is average resistivity, u
nMobility for electronics.
The invention provides the Central Symmetry layout-design that four circular Hall elements are connected in parallel, greatly reduce offset voltage, improved Hall coefficient, Hall element consistance, reduced offset voltage.
Description of drawings
Fig. 1 is traditional Hall element plane structure chart;
Fig. 2 is four traditional Hall element plane structure charts that are connected in parallel;
Fig. 3 is the magnetic direction schematic diagram that Hall element can detect;
Fig. 4 is the sectional view of Hall element of the present invention;
Fig. 5 is the plane structure chart of Hall element of the present invention;
Fig. 6 is Wen's bridge equivalent circuit diagram;
Fig. 7 is four of the present invention circular Hall element plane structure charts that are connected in parallel.
Description of symbols among the figure
The pre-buried regions of 1-P type
2-N type epitaxial loayer
3-high pressure P trap shading ring
4-low pressure P trap
The 5-P+ injection region
6-high pressure N trap
7-low pressure N trap
The 8-N+ injection region
Four leading-out terminals of H1, H2, H3, H4-hall device
Epitaxial electric resistance between R1-hall device leading-out terminal H1 and the H4
Epitaxial electric resistance between R2-hall device leading-out terminal H1 and the H2
Epitaxial electric resistance between R3-hall device leading-out terminal H3 and the H4
Epitaxial electric resistance between R4-hall device leading-out terminal H2 and the H3
The Vdd-power supply
The Vh-Hall voltage
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing and embodiment.
Figure 3 shows that the magnetic direction that Hall element can detect.2 input terminals of hall device link to each other with positive negative potential respectively, and when not existing magnetic field or magnetic field intensity very weak, the voltage difference between two lead-out terminals of Hall element is approximately zero; When changing perpendicular to the magnetic field intensity on hall device plane or direction, there is the voltage difference about a hundreds of microvolt between two lead-out terminals of Hall element.Change by the voltage difference that detects between the Hall element lead-out terminal, as the finger of changes of magnetic field not.
With reference to Fig. 4, Fig. 5, a kind of structure that reduces Hall element offset voltage and shielding noise of the present invention has adopted shading ring 3, high pressure N trap 6 to do the Nepi contact, and round-shaped Hall element and noisemetallic screen layer.
Figure 4 shows that the longitudinal sectional drawing of Hall element of the present invention.The left and right sides of sectional view is that high pressure P trap 3 and p type buried layer 1 form isolation structure, and N-type epitaxial loayer 2 has consisted of the Hall plane in the sectional view.Hall element comprises: form p type buried layer 1 at the N-type wafer; Deposit N-type epitaxial loayer 2 on the N-type wafer; Generate high pressure P trap 3 and low pressure P trap 4 in p type buried layer 1 diffusion, high pressure P trap 3 and p type buried layer 1 form up and down to isolation; Generate high pressure N trap 6 and low pressure N trap 7 in 2 diffusions of N-type epitaxial loayer; Form N+ injection region 8, P+ injection region 5 (being included in the P+ injection region that N-type epitaxial loayer 2 forms); Depositing metal is drawn the terminal of Hall element, deposit protective seam after P+ injection region 8, the N+ injection region 5 of correspondence peel off oxide to form contact hole.
Figure 5 shows that the floor map of Hall element of the present invention.Shading ring by p type buried layer 1, high pressure P trap 3, low pressure P trap 4 and P+ injection region 5 consist of links to each other with a clean fixed level by top-level metallic, can avoid outside noise hall device inside, as far as possible noise reduction.
Figure 6 shows that Wen's bridge equivalent electrical circuit.Under dc state, Hall element can be regarded as Wen's bridge that is made of distributed resistance.During ideal situation, R1=R2=R3=R4.When magnetic fields is arranged in Hall element, will produce induced potential at the two ends of H2 and H4, this induced potential just can remove the driver output circuit through amplification, control after processing.
Fig. 7 is four of the present invention circular Hall element plane structure charts that are connected in parallel.Four are connected in parallel such as Fig. 4, circular Hall element shown in Figure 5.
The forming step of said structure is: form the N-type wafer; Form p type buried layer at the N-type wafer; Deposit N-type epitaxial loayer on the N-type wafer; Generate high pressure P trap and low pressure P trap in the p type buried layer diffusion, high pressure P trap and p type buried layer directly join; Generate high pressure N trap and low pressure N trap in the diffusion of N-type epitaxial loayer; Form N+ injection region, P+ injection region, be included in the heavily doped P+ of N-type epitaxial loayer zone deposit; Depositing metal is drawn the terminal of hall device, deposit protective seam after P+ injection region, the N+ injection region of correspondence peel off oxide to form contact hole.Outside the deep trap shading ring of Hall element, add the P+ injection region shading ring of a circle ground connection in addition.
Characteristics of the present invention are to adopt BCD technique to make Hall element, have lower noise, lower offset voltage, higher Hall coefficient.Principal feature is:
(1) the present invention has adopted round-shaped Hall element;
(2) the present invention has adopted high pressure P trap shading ring;
(3) the present invention has adopted high pressure N trap to do the Nepi contact;
The description of above embodiment mainly is for ultimate principle of the present invention and principal character are described.The present invention is not limited to the description scope of above-described embodiment, in the scope of appended claims of the present invention, can make variously replenish, change and replacing.
Claims (7)
1. the Hall element of low-noise low-offset voltage comprises Hall element, it is characterized in that, described Hall element is circular, is included in the N-type epitaxial loayer that deposit forms on the N-type wafer and the circular high pressure P trap shading ring that forms at the N-type wafer.
2. the Hall element of low-noise low-offset voltage according to claim 1, it is characterized in that, described shading ring is included in the p type buried layer that forms on the N-type wafer, in high pressure P trap and low pressure P trap and the P+ injection region in described low pressure P trap that the p type buried layer diffusion generates.
3. the Hall element of low-noise low-offset voltage according to claim 2 is characterized in that, comprises that also four form the diffusion region of circumference uniform distribution.
4. the Hall element of low-noise low-offset voltage according to claim 3 is characterized in that, described diffusion region is included in high pressure N trap and the low pressure N trap that diffusion generates on the described N-type epitaxial loayer, and the N+ injection region in described low pressure N trap.
5. the Hall element of low-noise low-offset voltage according to claim 4 is characterized in that, also is included in corresponding described P+ injection region, N+ injection region and peels off oxide and form the Hall element terminal that depositing metal is drawn behind the contact hole.
6. the Hall element of low-noise low-offset voltage according to claim 1 is characterized in that, is provided with a circle in the P+ injection region of the ground connection of described N-type epi region formation outside described shading ring.
7. the Hall element of low-noise low-offset voltage according to claim 1 is characterized in that, the mask layer of described high pressure P trap is than the large 0.05um of mask layer of p type buried layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102141797A CN102901524A (en) | 2011-07-28 | 2011-07-28 | Low-noise low-offset voltage hall sensor |
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| CN2011102141797A CN102901524A (en) | 2011-07-28 | 2011-07-28 | Low-noise low-offset voltage hall sensor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093137A (en) * | 2014-05-09 | 2015-11-25 | 英飞凌科技股份有限公司 | Vertical hall effect-device |
| CN109188317A (en) * | 2018-09-14 | 2019-01-11 | 浙江红果微电子有限公司 | The hall device of flat magnetic field induction |
| CN110319858A (en) * | 2019-06-21 | 2019-10-11 | 深圳市梓晶微科技有限公司 | A kind of low imbalance Hall sensor of low-power consumption |
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| CN101290946A (en) * | 2007-04-19 | 2008-10-22 | 上海钜胜微电子有限公司 | Method and device for decreasing offset voltage of Hall integrated circuit |
| US20090108839A1 (en) * | 2007-10-29 | 2009-04-30 | Udo Ausserlechner | Integrated circuit with stress sensing element |
| CN101459217A (en) * | 2007-12-14 | 2009-06-17 | 上海华虹Nec电子有限公司 | Hall disc |
| CN201732791U (en) * | 2010-08-12 | 2011-02-02 | 四川和芯微电子股份有限公司 | Transverse diffusion metallic oxide semiconductor structure |
| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
| CN202134578U (en) * | 2011-05-19 | 2012-02-01 | 上海腾怡半导体有限公司 | Integrated Hall device |
| CN202167545U (en) * | 2011-07-28 | 2012-03-14 | 上海腾怡半导体有限公司 | Hall sensor with low noise and low offset voltage |
| CN102790072A (en) * | 2011-05-19 | 2012-11-21 | 上海腾怡半导体有限公司 | Integrated hall device and fabrication method thereof |
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2011
- 2011-07-28 CN CN2011102141797A patent/CN102901524A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4253107A (en) * | 1978-10-06 | 1981-02-24 | Sprague Electric Company | Integrated circuit with ion implanted hall-cell |
| CN101290946A (en) * | 2007-04-19 | 2008-10-22 | 上海钜胜微电子有限公司 | Method and device for decreasing offset voltage of Hall integrated circuit |
| US20090108839A1 (en) * | 2007-10-29 | 2009-04-30 | Udo Ausserlechner | Integrated circuit with stress sensing element |
| CN101459217A (en) * | 2007-12-14 | 2009-06-17 | 上海华虹Nec电子有限公司 | Hall disc |
| CN102130164A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Buried layer of LDMOS (laterally diffused metal-oxide semiconductor) |
| CN201732791U (en) * | 2010-08-12 | 2011-02-02 | 四川和芯微电子股份有限公司 | Transverse diffusion metallic oxide semiconductor structure |
| CN202134578U (en) * | 2011-05-19 | 2012-02-01 | 上海腾怡半导体有限公司 | Integrated Hall device |
| CN102790072A (en) * | 2011-05-19 | 2012-11-21 | 上海腾怡半导体有限公司 | Integrated hall device and fabrication method thereof |
| CN202167545U (en) * | 2011-07-28 | 2012-03-14 | 上海腾怡半导体有限公司 | Hall sensor with low noise and low offset voltage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105093137A (en) * | 2014-05-09 | 2015-11-25 | 英飞凌科技股份有限公司 | Vertical hall effect-device |
| CN105093137B (en) * | 2014-05-09 | 2018-01-30 | 英飞凌科技股份有限公司 | Vertical Hall effect device |
| CN109188317A (en) * | 2018-09-14 | 2019-01-11 | 浙江红果微电子有限公司 | The hall device of flat magnetic field induction |
| CN110319858A (en) * | 2019-06-21 | 2019-10-11 | 深圳市梓晶微科技有限公司 | A kind of low imbalance Hall sensor of low-power consumption |
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Application publication date: 20130130 |