WO2018098648A1 - 集成电路封装方法以及集成封装电路 - Google Patents

集成电路封装方法以及集成封装电路 Download PDF

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Publication number
WO2018098648A1
WO2018098648A1 PCT/CN2016/107832 CN2016107832W WO2018098648A1 WO 2018098648 A1 WO2018098648 A1 WO 2018098648A1 CN 2016107832 W CN2016107832 W CN 2016107832W WO 2018098648 A1 WO2018098648 A1 WO 2018098648A1
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Prior art keywords
substrate
circuit
layer
component
conductive
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PCT/CN2016/107832
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English (en)
French (fr)
Inventor
胡川
刘俊军
郭跃进
普莱克爱德华⋅鲁道夫
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深圳修远电子科技有限公司
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Priority to US16/465,233 priority Critical patent/US11335664B2/en
Priority to PCT/CN2016/107832 priority patent/WO2018098648A1/zh
Priority to CN201680090831.XA priority patent/CN110024110A/zh
Publication of WO2018098648A1 publication Critical patent/WO2018098648A1/zh

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Definitions

  • the invention belongs to the field of electronics, and in particular relates to an integrated circuit packaging method and an integrated package circuit.
  • a chip In a conventional integrated circuit system, a chip is separately packaged and then mounted on a circuit board together with other electronic components.
  • various materials By connecting to the circuit port of the substrate by bonding or flip-chip, and then connecting to the circuit board, various materials are used in a large amount, the process is complicated, the production cost is high, and it is easy to use a large number of materials with different characteristics. A variety of thermomechanical stresses are induced at the interface of each material.
  • inter-chip data communication and circuit connections between the chip and other electronic components need to pass through the chip pins and electronic device device pins as well as the circuitry inside the board. There must be sufficient space between the chips and between the chips and other electronic components, and the geometry of the entire system is constrained and cannot be sufficiently miniaturized.
  • the present invention overcomes the defects of the prior art, and provides an integrated circuit packaging method and an integrated package circuit, which has a simple manufacturing process and low cost, and reduces the volume while improving the reliability of the integrated package circuit.
  • An integrated circuit packaging method includes: a top surface of a substrate, or a bottom surface of the substrate, or a circuit layer in the substrate, the circuit layer has a circuit pin, the substrate is provided with a connection through hole, and the connection through hole
  • the circuit pins are butted to mount components on the substrate, and the components have device pins on one side of the substrate, so that the device pins are docked with the first opening of the connection vias,
  • the second opening of the connection via defines a conductive layer in the connection via, the conductive layer electrically connecting the device pin to the circuit pin.
  • the second opening through the connecting through hole is made in the connecting through hole
  • the conductive bonding material is fed into the connecting through hole from the second opening of the connecting through hole, and the conductive bonding material is adhered to the inner wall of the connecting through hole and The conductive layer is formed on the device pins.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste, or a conductive metal paste.
  • the conductive bonding material is disposed in the connecting via hole by screen printing during the process of forming a conductive layer in the connecting via hole through the second opening of the connecting via.
  • the conductive layer is formed by electroplating during the process of forming a conductive layer in the connection via through the second opening of the connection via.
  • an adhesive film is disposed between the component and the substrate, and the adhesive film pastes the component into the Said substrate.
  • a chemical solvent creates additional vias in the adhesive film, the additional vias interfacing the connection vias with the device pins, the conductive layer extending into the additional vias.
  • a protective layer is provided on an inner wall of the connecting through hole for protecting the substrate when the additional through hole is formed.
  • the integrated circuit packaging method further includes: after the conductive layer is formed, providing an encapsulation layer on the substrate, wherein the two components are packaged by the encapsulation layer and the substrate; or After the component is placed on the substrate and the conductive layer is formed, an encapsulation layer is disposed on the substrate, and the two components are packaged by the encapsulation layer and the substrate.
  • the components are at least two.
  • the integrated circuit packaging method further includes disposing an encapsulation layer on the substrate, at least two of the components being packaged by the encapsulation layer and the substrate.
  • the component is a chip or an electronic component, and at least two of the components include at least one chip and at least one electronic component.
  • the component is a chip, or an electronic component.
  • the substrate is a flexible circuit board.
  • the substrate comprises at least two layers of flexible circuit boards stacked in a stack.
  • An integrated package circuit comprising: a component, the component is provided with a device pin; a substrate, a top surface of the substrate, or a bottom surface of the substrate, or a circuit layer disposed in the substrate, the circuit
  • the layer is provided with a circuit pin
  • the substrate is provided with a connection via
  • the connection via is docked with the circuit pin; wherein the component is mounted on the substrate, the device pin is facing the substrate,
  • the first opening of the connection via is docked with the device pin
  • the second opening of the connection via is an operation window
  • the connection via is provided with a conductive layer, and the conductive layer places the device pin Electrically connected to the circuit pins.
  • the substrate is a flexible circuit board, or the substrate comprises at least two layers of flexible circuit boards stacked.
  • the circuit layer is a functional circuit, or the circuit layer itself constitutes an electronic component.
  • the component is mounted on a top surface of the substrate, a top surface of the substrate is provided with the circuit layer, and an insulating medium is disposed between the component and the substrate, The insulating medium is provided with an additional through hole in communication with the first opening of the connecting through hole, and the conductive layer extends into the additional through hole to be electrically connected to the device pin.
  • the top surface of the substrate is provided with a circuit layer, or/and the bottom surface of the substrate is provided with a circuit layer, or/and the circuit layer is provided in the substrate, and the device pins are at least Two of the device pins are electrically connected to at least one of the circuit layers, and one of the device pins is electrically connected to at least one of the remaining circuit layers.
  • the integrated circuit packaging method comprises: a top surface of the substrate, or a bottom surface of the substrate, or a circuit layer in the substrate, wherein the circuit layer has a circuit pin, and the circuit layer can be prepared in advance on the substrate, or in the integrated circuit
  • the circuit layer is formed on the substrate during packaging, and the circuit pin may be a connection portion directly led out by the circuit layer, or may be an extension pin electrically connected to the connection portion, as long as the circuit pin can be used to connect the circuit Layer electrical connections are available.
  • the substrate is provided with a connection through hole, and a connection through hole on the substrate. If necessary, the connection through hole may be formed on the substrate in advance, and then packaged, or sealed.
  • a connection via is formed on the substrate during the mounting process.
  • connection via is docked with the circuit pin to place components on the substrate.
  • the component When the component is placed on the substrate, the component may be fixed to the substrate or may not be fixed.
  • the component has a device pin facing one side of the substrate, and the device pin of the component includes, but is not limited to, a connection portion that is internally led out of the component, and an extension pin that is electrically connected to the connection portion, as long as the device pin can be connected to the element.
  • the device can be electrically connected.
  • the circuit pins are electrically connected, and the device pins are located on a top surface of the substrate, and the circuit layer can be electrically connected relatively easily with the top surface; the second opening of the through hole can be used to connect components and circuits from the bottom surface of the substrate.
  • Layer electrical connections prevent components from blocking the device pins, providing the possibility of implementing more complex wiring designs;
  • connection via is docked with the device pin, and the device pin is at least partially located near the first opening of the connection via or deep into the via, so that the conductive layer can be electrically connected to the device pin;
  • the circuit pin and the connection are The hole is docked, and the circuit pin is at least partially located near the first opening of the connection through hole, or near the second opening, or in the vicinity of the inner wall of the connection through hole, so that the conductive layer can be electrically connected to the circuit pin;
  • the component can be a chip or an electronic Components (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas).
  • the component may be fixed to the substrate by connecting a via hole or a conductive layer, or the component may be fixed to the substrate by other means including but not limited to bonding, molding a plastic package.
  • this new system package can reduce the overall thickness of the substrate and components and increase the density of package integration, because there is no need to reserve a gap between the substrate and the components (in principle, there is no need to reserve a gap, but according to Need to be able to set other materials on the substrate and components); components can be chips or electronic components, data communication between chips, or between chips and electronic components, can be implemented in the substrate, no need to bypass to thicker In the implementation of the circuit board, this will increase the bandwidth and speed of data communication; the single chip package itself does not require heating and soldering steps; more importantly, the material used in the entire system package is greatly reduced and easier. Process optimization to reduce encapsulation in the encapsulation layer, such as molded materials In the high-temperature processing of encapsulation,
  • the present invention realizes electrical connection between the first chip and the circuit layer by opening a connection via hole on the substrate, and the conductive layer is provided. In the connection through hole, no additional space is occupied, and the overall volume after packaging can be greatly reduced. In particular, the ability to reliably use a flexible circuit board as a substrate is a great advantage.
  • the conductive bonding material is fed into the connecting through hole from the second opening of the connecting through hole,
  • the conductive bonding material is bonded to the inner wall of the connection via and the device lead to form the conductive layer.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste or a conductive metal paste, and one or more types may be selected according to the process requirements or the material of the substrate, the size of the inner wall of the connecting through hole, and the nature of the surface material.
  • the process of placing a conductive bonding material to form a conductive connecting channel may use common soldering processes, including surface cleaning, flux spraying, precision placement of solder balls and heat treatment using a ball machine, and more special chemical surfaces. Cleaning, surface treatment, precision spraying of solder paste, conductive paste or conductive metal paste, followed by heat treatment to form mechanical and electrical connections.
  • the conductive bonding material is disposed in the connecting via hole by screen printing during the process of forming a conductive layer in the connecting via hole through the second opening of the connecting via.
  • Screen printing is a commonly used method for manufacturing circuit layers. Screening is used to make conductive layers.
  • the equipment is universal and can be synchronized with the production of circuit layers, saving process flow and further reducing costs.
  • the conductive layer is formed by electroplating in the process of forming a conductive layer in the connection via hole through the second opening of the connection via hole, and good electrical conductivity can be obtained. Electroplating can better control the thickness of the conductive layer to achieve the desired conductivity.
  • an adhesive film is disposed between the component and the substrate, and the adhesive film adheres the component to the substrate.
  • connection via hole passing through the second opening of the connection via hole in the process of forming a conductive layer in the connection via hole, through the second opening of the connection via hole, using laser sintering, plasma cleaning, or chemical solvent in the
  • the adhesive film is formed with additional vias that interface the connection vias with the device leads, and the conductive layer extends into the additional vias. Make additional vias to prevent the adhesive film from blocking the electrical connections of the device leads, conductive layers, and circuit pins. Laser melting, plasma cleaning, or chemical solvent etching may be employed as needed.
  • a protective layer is disposed on the inner wall of the connecting through hole, and the protective layer is used to protect the substrate when the additional through hole is formed.
  • the additional via hole can be used, but not limited to the process of chemical etching or drilling. In this case, it is necessary to pass through the connection via hole, which may damage the inner wall of the connection via hole, thereby causing damage to the substrate and the circuit layer.
  • the protective layer protects the inner wall of the connecting through hole from damage.
  • the protective layer may be a material that facilitates electrical connection of the conductive layer, and the protective layer may be in contact with the circuit pins to facilitate electrical connection between the circuit pins and the conductive layer.
  • the protective layer may be a metal film which is pre-sputtered or vapor-deposited on the inner wall of the connection via, so that the material of the inner wall of the connection via is protected from being exposed to the etching solvent or ions during the chemical etching process.
  • a thin metal layer can also improve the electrical conductivity of the conductive layer that is subsequently plated in the connection via.
  • an encapsulation layer is disposed on the substrate, and the two components are packaged by the encapsulation layer and the substrate; or, the component is placed on the substrate
  • an encapsulation layer is disposed on the substrate, and the two components are sealed.
  • the layer and the substrate are packaged. Encapsulation of the components by the encapsulation layer protects the components from environmental influences, and the encapsulation layer can cover the substrate, protect the substrate and the circuit layer on the substrate, and avoid bending and scratching. On the other hand, the components can be fixed to the substrate by the encapsulation layer without additional procedures for fixing the components.
  • the components are at least two.
  • the integrated circuit packaging method is applicable to two or more components. Further, two or more components can be operated at the same time, and the above components are mounted on the substrate to realize electrical connection between the components and the circuit layer, thereby improving efficiency, cut costs.
  • the component is a chip or an electronic component.
  • the integrated circuit packaging method is suitable for packaging of chips or electronic components, including but not limited to independent resistors, capacitors, inductors, diodes, or transistors, including but not limited to die, wafer, or packaged integrated chip . Chips or electronic components can be packaged using the same equipment and process flow to reduce costs.
  • the integrated circuit package method further includes disposing an encapsulation layer on the substrate, at least two of the components being packaged by the encapsulation layer and the substrate.
  • the purpose of the encapsulation layer is mainly to protect the components from external environmental factors such as the influence of water vapor and electromagnetic radiation on the electrical properties of the components. At the same time, it also fixes the relative position of multiple components on the substrate to ensure the stability of the electrical connection. In this invention, after curing, it acts more as a support plate, so that we can then conveniently make the conductive layer of the inner wall of the connection via hole on the substrate.
  • the component is a chip or an electronic component
  • at least two of the components include at least one chip and at least one electronic component. Chips and electronic components can be packaged at the same time to increase efficiency and reduce costs.
  • the substrate is a flexible circuit board; or the substrate comprises at least two layers of flexible circuit boards stacked.
  • the component is mounted on the substrate by the integrated circuit packaging method, and the electrical connection between the component and the circuit layer on the substrate is realized.
  • the substrate is a flexible circuit board or a multilayer flexible circuit board, the overall flexibility can be maintained, and the utility model can be used for Wear equipment, etc.
  • An integrated package circuit comprising: a component, the component being provided with a device pin; a substrate, a top surface of the substrate, or a bottom surface of the substrate, or a circuit layer disposed in the substrate, the circuit The layer is provided with a circuit pin, the substrate is provided with a connection via, and the connection via is connected to the circuit pin.
  • the component is mounted on the substrate, the device pin faces the substrate, the first opening of the connection via is docked with the device pin, and the second opening of the connection via is operated a conductive layer is disposed in the connection via, and the conductive layer electrically connects the device pin and the circuit pin.
  • the conductive layer is formed by connecting the through holes, and the manufacturing process is simple and the cost is low, thereby ensuring the performance of the integrated package circuit.
  • the substrate is a flexible circuit board, or the substrate comprises at least two layers of flexible circuit boards stacked.
  • the overall flexibility can be maintained, and it can be used for a wearable device or the like.
  • the circuit layer is a functional circuit, the circuit layer has a certain electronic function; or the circuit layer itself constitutes an electronic component, including but not limited to an antenna.
  • the circuit layer of the integrated package circuit structure has a wide application range and can realize integration of various functions.
  • the component is mounted on a top surface of the substrate, the top surface of the substrate is provided with the circuit layer, an insulating medium is disposed between the component and the substrate, and the insulating medium is provided with an additional a via hole communicating with the first opening of the connection via hole, and the conductive layer extending into the additional via hole is electrically connected to the device pin.
  • An insulating medium is disposed between the component and the substrate to prevent the component from affecting the circuit layer or other conductive structure on the top surface of the substrate. When the device has more than two device pins, some of the device pins pass through the present invention.
  • the integrated circuit package method is connected to the substrate or the circuit layer, and the insulating medium can prevent the influence of the other device pins on the substrate or the circuit layer. Further, the insulating medium can be selected as a viscous material, and the component is bonded and fixed to the substrate.
  • the top surface of the substrate is provided with a circuit layer, or / and the bottom surface of the substrate is provided with a circuit layer, or / and the circuit layer is provided in the substrate
  • the device pins are at least two, one of The device pins are electrically coupled to at least one of the circuit layers, and one of the device pins is electrically coupled to at least one of the remaining circuit layers.
  • the substrate is provided with two or more circuit layers, and the components are electrically connected to at least two different circuit layers through different device pins to expand the circuit function.
  • FIG. 1 is a first schematic diagram of an integrated circuit package method according to an embodiment of the present invention.
  • FIG. 2 is a second schematic diagram of an integrated circuit package method according to an embodiment of the present invention.
  • FIG. 3 is a third schematic diagram of an integrated circuit package method according to an embodiment of the present invention.
  • FIG. 4 is a fourth schematic diagram of an integrated circuit package method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 5 of an integrated circuit package method according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 1 of an integrated circuit packaging method according to Embodiment 2 of the present invention.
  • FIG. 7 is a second schematic diagram of an integrated circuit packaging method according to Embodiment 2 of the present invention.
  • FIG. 8 is a third schematic diagram of an integrated circuit packaging method according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram 4 of an integrated circuit packaging method according to Embodiment 2 of the present invention.
  • FIG. 10 is a first schematic diagram of a method for packaging an integrated circuit according to a third embodiment of the present invention.
  • FIG. 11 is a second schematic diagram of an integrated circuit package method according to Embodiment 3 of the present invention.
  • FIG. 12 is a third schematic diagram of a method for packaging an integrated circuit according to a third embodiment of the present invention.
  • FIG. 13 is a fourth schematic diagram of a method for packaging an integrated circuit according to a third embodiment of the present invention.
  • the integrated package circuit includes: a component 200 and a substrate 100.
  • the component 200 is mounted on the top surface of the substrate 100.
  • the top surface and the bottom surface of the substrate 100 are respectively provided with circuit layers 110a and 110b.
  • the insulating medium 300 is disposed between the component 200 and the substrate 100. (In this embodiment, the insulating medium 300 is simultaneously provided. Also a sticky film).
  • the component 200 is provided with device pins 210a, 210b, the device pins 210a, 210b are facing the substrate 100, the circuit layers 110a, 110b are provided with circuit pins, and the substrate 100 is provided with connection vias 120a, 120b, and the connection vias 120a, 120b Docking with the circuit pins, the first opening 120c connecting the through holes 120a, 120b abuts the device pins 210a, 210b, and connects the through holes 120a,
  • the second opening 120d of 120b is an operation window, and the insulating medium 300 (adhesive film) is provided with an additional through hole, and the additional through hole communicates with the first opening 120c of the connecting through hole 120a, 120b, and the connecting through hole 120a, 120b is provided
  • the insulating medium 300 separates the component 200 from the substrate 100.
  • the insulating medium 300 adheresive film
  • the insulating medium 300 can prevent the component 200 from affecting the circuit layer 110a, 110b or other conductive structures on the top surface of the substrate 100.
  • the pins 210a and 210b affect the substrate 100 or the circuit layers 110a and 110b.
  • the insulating medium 300 is also an adhesive film, and the insulating medium 300 (adhesive film) bonds the component 200 to the substrate 100.
  • the component 200 is placed on the substrate 100 by means of bonding, and the component 200 is placed on the substrate 100 to fix the component 200 to the substrate 100, thereby saving steps, improving efficiency, and reducing cost.
  • the insulating medium 300 only functions as the isolation component 200 and the substrate 100.
  • the component 200 is fixed to the substrate 100 by another method, and the component 200 may be attached to the substrate 100 by using an adhesive film.
  • the adhesive film does not function to isolate the component 200 from the substrate 100.
  • the integrated circuit packaging method includes: as shown in FIG. 1 and FIG. 2, the top surface and the bottom surface of the substrate 100 respectively have circuit layers 110a and 110b, and the circuit layers 110a and 110b have circuit pins.
  • the circuit layers 110a and 110b are formed on the substrate 100 in advance, but the circuit layers 110a and 110b may be formed on the substrate 100 during the integrated circuit package.
  • the circuit pins may be directly connected to the circuit layers 110a and 110b.
  • the extension pin may be electrically connected to the connection portion, and may be electrically connected to the circuit layers 110a and 110b through circuit pins.
  • the device pins 210a, 210b of the component 200 include, but are not limited to, a connection portion drawn inside the component 200 and an extension pin electrically connected to the connection portion, as long as the device pins 210a, 210b can be electrically connected to the component 200.
  • the device pins 210a, 210b are interfaced with the first openings 120c of the connection vias 120a, 120b.
  • the substrate 100 is provided with connection vias 120a and 120b.
  • the connection vias 120a and 120b are connected to the circuit pins.
  • the connection vias 120a and 120b are formed in advance on the substrate 100, but are not limited thereto. Advance The connection vias 120a, 120b are formed on the substrate 100, and then the integrated circuit package is formed.
  • the connection vias 120a, 120b may also be formed on the substrate 100 during the integrated circuit package process.
  • one surface of the device 200 on which the device leads 210a and 210b are provided is coated with an adhesive film (not limited to this embodiment, the adhesive film can be applied to the substrate 100), and the component 200 has device pins.
  • One side of 210a and 210b faces the substrate 100, and the component 200 is placed on the substrate 100.
  • the adhesive film mounts the component 200 on the substrate 100.
  • the adhesive film is at the same time the insulating medium 300, and is not limited to the embodiment, and the adhesive film bonding component 200 may not be used.
  • an additional through hole is formed in the adhesive film by laser sintering, plasma cleaning, or a chemical solvent, and the additional through hole will connect the through holes 120a, 120b with Device pins 210a, 210b are docked to prevent the adhesive film from blocking the electrical connections of device pins 210a and 210b, conductive layers 400a and 400b, and circuit pins.
  • conductive layers 400a, 400b are formed in the connection vias 120a, 120b through the second openings 120d connecting the via holes 120a, 120b, and the conductive layers 400a, 400b protrude into the additional via holes, and the conductive layers 400a, 400b
  • the device pins 210a, 210b are electrically connected to the circuit pins; the device pins 210a, 210b are located on the top surface of the substrate 100, and the components 200 can be transferred from the bottom surface of the substrate 100 by the second openings 120d connecting the vias 120a, 120b.
  • the device pins 210a, 210b are electrically coupled to the circuit layers 110a, 110b, thus avoiding the occlusion of the device pins 210 from the top of the device pins 210a, 210b.
  • Packaging according to the above method can reduce the cost of the integrated circuit package and save packaging time. Moreover, the overall thickness of the substrate 100 and the component 200 is reduced, and even no gap is required between the substrate 100 and the component 200 (in principle, no gap is required, but other components can be disposed on the substrate 100 and the component 200 as needed. Material); the step of heat welding is not required, especially for the packaging of the ultra-thin chip 200 and the flexible circuit board, the overall thermo-mechanical stress distribution of the system caused by large temperature changes, and the influence on the performance of the component 200 can be avoided.
  • an encapsulation layer is disposed on the substrate 100, and the component 200 is packaged by the encapsulation layer and the substrate 100.
  • the conductive layers 400a and 400b are formed.
  • an encapsulation layer is disposed on the substrate 100, and the two components 200 are packaged by the encapsulation layer and the substrate 100.
  • the component 200 is encapsulated by an encapsulation layer to protect components 200, and the encapsulation layer can cover the substrate 100, protect the substrate 100 and the circuit layers 110a, 110b on the substrate 100 to avoid bending and scratching.
  • the component 200 can be fixed to the substrate 100 by an encapsulation layer without requiring an additional program to fix the component 200.
  • connection vias 120a, 120b are mated with the device pins 210a, 210b, and the device pins 210a, 210b are at least partially located adjacent to the first opening 120c of the connection vias 120a, 120b or deep into the vias 120a, 120b, such that The conductive layers 400a, 400b can be electrically coupled to the device pins 210a, 210b; the circuit pins are mated with the connection vias 120a, 120b, the circuit pins being at least partially located adjacent the first opening 120c of the connection vias 120a, 120b, or a second The vicinity of the opening 120d or the vicinity of the inner wall of the connecting vias 120a, 120b, so that the conductive layers 400a, 400b can be electrically connected to the circuit pins; the component 200 can be a chip or electronic components (including but not limited to resistors, capacitors) or other electronic Devices (including but not limited to antennas). The component 200 may be fixed to the substrate 100 through the connection vias 120a,
  • the conductive bonding material is sent from the second openings 120d of the connection vias 120a, 120b.
  • the conductive vias 120a, 120b are connected to the vias 120a, 120b, and the conductive bonding material is bonded to the inner walls of the connection vias 120a, 120b and the device pins 210a, 210b to form the conductive layers 400a, 400b.
  • the back surface of the substrate 100 can be operated without being disturbed by the component 200, and the conductive bonding material is adhered to the connection via 120a by bonding.
  • the inner wall of 120b and the device pins that are connected to the connection vias can form mechanical and electrical connections at the same time after proper heating or chemical treatment, and also ensure stable conductive connection performance.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste, or a conductive metal paste, and the structure shown in FIG. 9 is formed, which can be selected according to the process requirements or the material of the substrate 100 and the properties of the inner walls of the connecting vias 120a and 120b. A combination of one or more.
  • a conductive bonding material is provided in the connection via holes 120a, 120b by screen printing.
  • Screen printing is a common method of manufacturing circuit layers 110a, 110b, using screen printing
  • the conductive layers 400a and 400b are formed by brushing, and the device can be used in common, and can be synchronized with the fabrication of the circuit layers 110a and 110b, thereby saving the process flow and further reducing the cost.
  • the conductive layers 400a, 400b are formed by electroplating to form a layer as shown in FIG. structure. Good electrical conductivity can be obtained, and plating can control the thickness of the conductive layers 400a, 400b to obtain desired electrical conductivity.
  • a plurality of components 200 can be simultaneously mounted on a large panel of a large area, and the batch processing on the large panel further reduces the cost and saves the packaging time.
  • mass production a plurality of sets of components 200 are arranged on a carrier by using a carrier of a large flat plate, the carrier is covered on the top surface of the substrate 100, and the component 200 is attached to the substrate 100 using an adhesive film to separate the carrier from the component 200.
  • the component 200 is mounted on the carrier by a photosensitive or heat sensitive material, the temperature or illumination is changed to disengage the carrier and the component 200), and then the above steps 2-4 are performed, and finally the substrate 100 is cut according to a preset grouping.
  • the adhesive film can be an insulating material at the same time
  • the top surface and the bottom surface of the substrate 100 are respectively provided with circuit layers 110a and 110b, and the chip is electrically connected to the circuit layers 110a and 110b at the same time.
  • the circuit layer 110a is embedded in the substrate 100.
  • the device pins 210a, 210b are electrically connected to the circuit layers 110a, 110b; or the top surface of the substrate 100 is provided with circuit layers 110a, 110b, or / and the bottom surface of the substrate 100 is provided with circuit layers 110a, 110b, or /
  • the circuit board 110 is provided with circuit layers 110a, 110b, and the device pins 210a, 210b are at least two, one of the device pins 210a, 210b is electrically connected to at least one of the circuit layers 110a, 110b, and another device pin 210a 210b is electrically connected to at least one of the remaining circuit layers 110a, 110b.
  • the substrate 100 is provided with two or more circuit layers 110a and 110b.
  • the component 200 is electrically connected to at least
  • the substrate 100 may be a flexible circuit board; or the substrate 100 may include at least two layers of flexible circuit boards.
  • the component 200 is mounted on the substrate 100 by the integrated circuit packaging method, and the electrical connection between the component 200 and the circuit layers 110a and 110b on the substrate 100 is realized. 200.
  • the substrate 100 has a small overall thickness and can maintain overall flexibility, and can be used for a wearable device or the like.
  • the component 200 is a chip or an electronic component.
  • the integrated circuit packaging method is suitable for packaging of chips or electronic components, including but not limited to independent resistors, capacitors, inductors, diodes, or transistors, including but not limited to die, wafer, or packaged integrated chip . Chips or electronic components can be packaged using the same equipment and process flow, reducing costs.
  • the component 200 may be at least two.
  • the integrated circuit packaging method is applicable to two or more components 200. Further, two or more components 200 can be simultaneously operated, and the above components 200 are mounted on the substrate 100 to implement the component 200 and the circuit layer 110a. 110b electrical connection to improve efficiency and reduce costs.
  • the component 200 is at least two, it may be that at least two components 200 include at least one chip and at least one electronic component. Chips and electronic components can be packaged at the same time to increase efficiency and reduce costs.
  • an encapsulation layer is provided on the substrate 100, it is optional to package a single component 200 or package two or more components 200.
  • the purpose of the encapsulation layer is mainly to protect the components from external environmental factors such as the influence of water vapor and electromagnetic radiation on the electrical properties of the components. At the same time, it also fixes the relative position of multiple components on the substrate to ensure the stability of the electrical connection. In this invention, after curing, it acts more as a support plate, so that we can then conveniently make the conductive layer of the inner wall of the connection via hole on the substrate.
  • two or more encapsulation layers may be disposed on one substrate 100, and the encapsulation layers may have a gap between each other to provide a larger curvature, so that the whole of the substrate 100, the component 200, and the encapsulation layer is more flexible.
  • the substrate 100 is a flexible circuit board or a substantially two or more flexible circuit boards, the integrated package circuit can maintain such flexibility, so that the integrated package circuit can be applied to, for example, a wearable device that needs to remain flexible. occasion.
  • the circuit layers 110a, 110b are functional circuits, and the circuit layers 110a, 110b have certain electronic functions; or the circuit layers 110a, 110b themselves constitute electronic components, including but not limited to antennas.
  • the circuit layers 110a, 110b of the integrated package circuit structure have a wide range of applications, and can realize integration of various functions.
  • Protective layers 121a and 121b are provided on the inner walls of the connection vias 120a and 120b, and the protective layers 121a and 121b are used to protect the substrate 100 when the additional via holes are formed.
  • the protective layers 121a and 121b may be formed on the substrate 100 in advance before the integrated circuit package is completed.
  • the protective layers 121a and 121b may be formed before the conductive layers 400a and 400b are formed.
  • the additional via holes may be formed by using, but not limited to, a chemical etching or a drilling process. In this case, it is necessary to pass through the connection via holes 120a, 120b, which may damage the material of the inner wall of the connection via holes 120a, 120b, and thus the substrate 100.
  • the circuit layers 110a, 110b cause damage, and the protective layers 121a, 121b can protect the inner walls of the connection vias 120a, 120b from damage during the process of making the connection vias or the additional vias.
  • the protective layers 121a, 121b may be materials that facilitate the electrical connection of the conductive layers 400a, 400b. At this time, the protective layers 121a, 121b may be in contact with the circuit pins to facilitate the circuit pins and the conductive layers 400a, 400b. Electrical connection.
  • connection vias 120a, 120b are provided with an auxiliary layer for assisting in the fabrication of the conductive layers 400a, 400b, so that the conductive layers 400a, 400b are better electrically connected to the device pins 210a, 210b, the circuit pins, Or better attached to the inner wall of the connecting through holes 120a, 120b.
  • the inner walls of the connection vias 120a, 120b are provided with protective layers 121a, 121b, and the protective layers 121a, 121b are also auxiliary layers, and the protective layers 121a, 121b (auxiliary layers) are used. It is made of the same material as the circuit layers 110a and 110b.
  • the circuit layers 110a and 110b are made of copper
  • the protective layers 121a and 121b (auxiliary layers) are also made of copper, which further improves the electrical connection performance.
  • the present invention is not limited to this embodiment, and other materials may be used as needed, and the protective layers 121a, 121b or the auxiliary layers for auxiliary electrical connection may be separately provided. As shown in FIG.
  • the protective layers 121a, 121b are electrically connected to the circuit layers 110a, 110b; as shown in FIG. 7, the component 200 is placed on the substrate 100, and the adhesive film (insulation) The medium 300) is attached to the substrate 100; as shown in FIG. 8, an auxiliary via is formed in the adhesive film (insulating material); as shown in FIG. 9, a conductive layer 400a is formed in the connecting vias 120a, 120b, 400b, conductive layers 400a, 400b electrically connect device pins 210a, 210b and circuit pins.
  • the conductive layers 400a and 400b shown in FIG. 9 are formed by soldering balls. However, the conductive layers 400a and 400b are formed by a method of soldering balls.
  • the conductive layers 400a and 400b may be formed by electroplating. Refer to Figure 13 for the shape of the conductive layer obtained.
  • the auxiliary layer (protective layer 121a, 121b) is directly connected to the circuit pin, the electrical connection effect is good, and the circuit pin can be extended to reduce the volume of the conductive layers 400a, 400b, which is beneficial to the fabrication of the conductive layers 400a, 400b, and is also advantageous for the fabrication of the conductive layers 400a, 400b. cut costs.
  • connection vias 120a, 120b are further fabricated during the packaging process, including the steps of:
  • the top surface and the bottom surface of the substrate 100 have circuit layers 110a and 110b, respectively, and the circuit layers 110a and 110b have circuit pins.
  • one surface of the component 200 on which the device leads 210a and 210b are provided is coated with an adhesive film (not limited to this embodiment, the adhesive film can be applied to the substrate 100), and the component 200 has a device pin.
  • One side of 210a and 210b faces the substrate 100, and the component 200 is placed on the substrate 100. At this time, the adhesive film mounts the component 200 on the substrate 100.
  • connection via holes 120a, 120b are formed on the substrate 100, and the device pins 210a, 210b are butted to the first openings 120c of the connection vias 120a, 120b, and the second vias 120a, 120b are connected.
  • the opening 120d is adapted to form conductive layers 400a, 400b in the connection vias 120a, 120b, and to form additional vias in the adhesive film.
  • the additional vias interface the connection vias 120a, 120b with the device leads 210a, 210b.
  • conductive layers 400a, 400b are formed in the connection vias 120a, 120b through the second openings 120d connecting the via holes 120a, 120b, and the conductive layers 400a, 400b protrude into the additional via holes, and the conductive layers 400a, 400b Device pins 210a, 210b are electrically coupled to circuit pins.
  • the circuit layers 110a and 110b are formed on the substrate 100 in advance.
  • the circuit layers 110a and 110b are not limited thereto.
  • the circuit layers 110a and 110b may be formed on the substrate 100 during integrated circuit packaging according to the needs of wiring and cost reduction.
  • the conductive layers 400a, 400b are formed by electroplating. It is also possible to pre-produce a part of the circuit layers 110a, 110b, and to form another part of the circuit layers 110a, 110b on the substrate 100 during the integration of the integrated circuit.
  • an auxiliary layer is formed by a sputtering or evaporation process.
  • the process of forming the conductive layers 400a, 400b by electroplating further includes sputtering before plating Or the evaporation process produces an auxiliary layer and then electroplating.
  • the sputtered or evaporated auxiliary layer is better electrically connected to the circuit leads, and the plated conductive layers 400a, 400b are attached to the auxiliary layer.
  • Sputtering or vapor deposition of the auxiliary layer can improve the quality of the plating on the one hand, and can better achieve the electrical connection between the conductive layers 400a, 400b and the circuit pins on the other hand.
  • a mold release layer is provided on the bottom surface of the substrate 100, and the mold release layer has a mold groove having a contour with the circuit layers 110a and 110b.
  • connection via holes 120a and 120b are formed, the conductive layers 400a and 400b are formed and a circuit is formed in the mold groove.
  • the layers 110a and 110b are formed by, for example, electroplating to form the conductive layers 400a and 400b, and the circuit layers 110a and 110b are formed in the mold grooves while plating.

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Abstract

一种集成电路封装方法以及集成封装电路，其中集成电路封装方法包括：基板（100）的顶面、或者基板（100）的底面、或者基板（100）内具有电路层（110a、110b），所述电路层（110a、110b）具有电路引脚，所述基板（100）设有连接通孔（120a、120b），所述连接通孔（120a、120b）与所述电路引脚对接，将元器件（200）安放于所述基板（100），所述元器件（200）朝向所述基板（100）的一面具有器件引脚（210a、210b），使所述器件引脚（210a、210b）与所述连接通孔（120a、120b）的第一开口（120c）对接，通过所述连接通孔（120a、120b）的第二开口（120d）在所述连接通孔（120a、120b）内制作导电层（400a、400b），所述导电层（400a、400b）将所述器件引脚（210a、210b）与所述电路引脚电连接。制作工艺简单、成本低，在提升集成封装电路可靠性的同时减小体积。

Description

集成电路封装方法以及集成封装电路 技术领域
本发明属于电子领域，具体涉及一种集成电路封装方法以及集成封装电路。
背景技术
传统的集成电路***，需要将芯片单独封装后，再与其它电子元件等一起安装于电路板上。通过以键合或者倒装的方式连接到基板的电路端口上，再接入到电路板上，各种材料使用量大，工艺复杂，生产成本高；而且使用大量特性各异的材料，也容易在各材料界面诱发多种热机械应力的问题。
并且，芯片间数据通讯以及芯片和其它电子元件之间的电路连接需要通过芯片引脚和电子元件器件引脚以及电路板内部的电路。芯片之间以及芯片和其它电子元件之间必须留有足够空间，整个***的几何尺寸也因而受到约束，不能充分小型化。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种集成电路封装方法以及集成封装电路，制作工艺简单、成本低，在提升集成封装电路可靠性的同时减小体积。
其技术方案如下：
一种集成电路封装方法，包括：基板的顶面、或者基板的底面、或者基板内具有电路层，所述电路层具有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接，将元器件安放于所述基板，所述元器件朝向所述基板的一面具有器件引脚，使所述器件引脚与所述连接通孔的第一开口对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，所述导电层将所述器件引脚与所述电路引脚电连接。
在其中一个实施例中，通过所述连接通孔的第二开口在所述连接通孔内制 作导电层的过程中，将导电粘接材料从所述连接通孔的第二开口送入所述连接通孔内，使所述导电粘接材料粘接于所述连接通孔的内壁和所述器件引脚上构成所述导电层。
在其中一个实施例中，所述导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆。
在其中一个实施例中，通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，采用丝网印刷在所述连接通孔内设置所述导电粘接材料。
在其中一个实施例中，通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，采用电镀的方式制作所述导电层。
在其中一个实施例中，将所述元器件安装于所述基板的过程中，在所述元器件与所述基板之间设置粘装膜，所述粘装膜将所述元器件粘贴于所述基板。
在其中一个实施例中，通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，通过所述连接通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述连接通孔与所述器件引脚对接，所述导电层伸入所述附加通孔内。
在其中一个实施例中，在所述连接通孔的内壁设有保护层，所述保护层用于在制作所述附加通孔时保护所述基板。
在其中一个实施例中，集成电路封装方法还包括：在制作所述导电层后，在所述基板上设置封装层，两个所述元器件被所述封装层和所述基板包裹封装；或者，在将所述元器件安放于所述基板后、制作所述导电层形之前，在所述基板上设置封装层，两个所述元器件被所述封装层和所述基板包裹封装。
在其中一个实施例中，所述元器件为至少两个。
在其中一个实施例中，集成电路封装方法还包括,在所述基板上设置封装层，至少两个所述元器件被所述封装层和所述基板包裹封装。
在其中一个实施例中，所述元器件为芯片或电子元件，至少两个所述元器件当中，包括至少一个芯片和至少一个电子元件。
在其中一个实施例中，所述元器件为芯片、或电子元件。
在其中一个实施例中，所述基板为柔性电路板。
在其中一个实施例中，所述基板包括至少两层层叠设置的柔性电路板。
一种集成封装电路，包括：元器件，所述元器件设有器件引脚；基板，所述基板的顶面、或者所述基板的底面、或者所述基板内设有电路层，所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；其中，所述元器件安装于基板，所述器件引脚朝向所述基板，所述连接通孔的第一开口与所述器件引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述器件引脚和所述电路引脚电连接。
在其中一个实施例中，所述基板为柔性电路板、或所述基板包括至少两层层叠设置的柔性电路板。
在其中一个实施例中，所述电路层为功能电路，或者所述电路层本身构成电子元件。
在其中一个实施例中，所述元器件安装于所述基板的顶面，所述基板的顶面设有所述电路层，所述元器件与所述基板之间设有绝缘介质，所述绝缘介质设有附加通孔，所述附加通孔与所述连接通孔的第一开口相连通，所述导电层伸入所述附加通孔与所述器件引脚电连接。
在其中一个实施例中，所述基板的顶面设有电路层、或/和所述基板的底面设有电路层、或/和所述基板内设有电路层，所述器件引脚为至少两个，其中一个所述器件引脚至少与其中一个所述电路层电连接，另有一个所述器件引脚至少与余下另一个所述电路层电连接。
本发明的有益效果在于：
1、集成电路封装方法包括：基板的顶面、或者基板的底面、或者基板内具有电路层，所述电路层具有电路引脚，可以预先在基板制作好所述电路层，也可以在集成电路封装时再在基板上制作所述电路层，电路引脚可以是电路层直接引出的连接部，也可以是和所述连接部电连接的扩展引脚，只要通过电路引脚能够和所述电路层电连接均可。所述基板设有连接通孔，基板上的连接通孔，根据需要，可以预先在基板上制作好连接通孔、再进行封装，也可以在封 装过程中在基板上制作连接通孔。所述连接通孔与所述电路引脚对接，将元器件安放于所述基板。将元器件安放于所述基板时，可以将元器件固定于基板上，也可以不固定。所述元器件朝向所述基板的一面具有器件引脚，元器件的器件引脚包括但不限于元器件内部引出的连接部、与连接部电连接的扩展脚，只要通过器件引脚能够和元器件电连接均可。使所述器件引脚与所述连接通孔的第一开口对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，所述导电层将所述器件引脚与所述电路引脚电连接，器件引脚位于基板的顶面，与顶面所述电路层可以相对容易地电连接；通过连接通孔的第二开口，可以从基板的底面将元器件与电路层电连接，避免元器件将器件引脚挡住，提供了实现更复杂布线设计的可能；
其中，连接通孔与器件引脚对接，器件引脚至少部分位于连接通孔的第一开口附近、或深入连接通孔内，使得导电层可以与器件引脚电连接；电路引脚和连接通孔对接，电路引脚至少部分位于连接通孔的第一开口附近、或第二开口附近、或连接通孔内壁的附近，使得导电层可以与电路引脚电连接；元器件可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。元器件可以通过连接通孔、导电层固定于所述基板，也可以是，元器件通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板。
与传统芯片封装工艺相比，如此可以简化集成电路***封装的工艺、降低成本；进一步地，可以在很大面积的大面板上同时安装多个元器件，在大面板上的并行批量处理进一步减低成本、节约封装时间。并且，这种新型的***封装，可以降低基板和元器件构成的整体的厚度、提高封装集成的密度，因为基板和元器件甚至之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板与元器件设置其他材料)；元器件可以是芯片或者电子元件，芯片之间、或者芯片和电子元器件之间的数据通讯，可以在基板内实现，不需要绕行至更厚的电路板中实现，这对于数据通讯的带宽和速度都会有提高；单个芯片封装本身，则不需要加热焊接的步骤；更重要的是，整个***的封装中，使用材料种类大大减少，更容易工艺优化，以减少在封装层包裹封装，譬如模压材 料包封的高温处理工程中，热机械应力的强度，这对导入超薄芯片、引入柔性电路板来说，意义重大。
另一方面，与传统的电子封装采用金属导线实现芯片与基板电路层的电连接相比，本发明通过在基板上开设连接通孔的方式实现第一芯片与电路层的电连接，导电层设于连接通孔内，不占用额外空间，可以大幅减小封装后整体的体积。特别是，能够可靠使用柔性电路板作为基板是一个很大的优势。
2、通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，将导电粘接材料从所述连接通孔的第二开口送入所述连接通孔内，使所述导电粘接材料粘接于所述连接通孔的内壁和所述器件引脚上构成所述导电层。采用从第二开口送入导电粘接材料的方式，可以在基板的底面进行操作，而不会被元器件干扰。通过使用导电性的粘接材料，在连接通孔内把顶层的元器件牢固地粘接到基板上避免器件脱落的同时，形成从元器件的器件引脚到基板导电层的导电通道，以获得好的导电连接性能。
3、所述导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆，可以根据工艺需要或者基板材质、连接通孔内壁的尺寸、表面材料性质，选择一种或多种的组合。放入导电粘接材料形成导电性连接通道的工艺，可能使用常见的焊接工艺，包括表面清洁、助焊剂喷涂、使用置球机精密放置焊球和热处理等步骤；也可能使用更特别的化学表面清洁，表面处理，精密喷涂焊锡膏、导电胶或导电金属浆，然后热处理以形成机械和电连接。
4、通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，采用丝网印刷在所述连接通孔内设置所述导电粘接材料。丝网印刷是电路层常用制作方法，采用丝网印刷的方式制作导电层，设备通用、可以和电路层的制作同步进行，节约工艺流程，进一步降低成本。
5、通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，采用电镀的方式制作所述导电层，可以获得很好的导电性能。电镀可以更好地控制导电层的厚度，获得理想的导电性能。
6、将所述元器件安装于所述基板的过程中，在所述元器件与所述基板之间设置粘装膜，所述粘装膜将所述元器件粘贴于所述基板。采用粘装膜粘贴的方式，将元器件安放于基板上，就可以实现元器件固定于基板，节约步骤、提高效率、降低成本。粘装膜可以是绝缘的，这样在即使基板顶面设有电路层的情况下，元器件引脚也能与所述基板顶面的电路层电绝缘，也因而在元器件之间保持电绝缘，只在之后做有导电通孔处形成电连接。使用绝缘性粘装膜粘接元器件与基板，配合导电通孔的制作，提供了在放置元器件之后再布线形成电路的可能，而不再需要通过另外的电路板中的电路来进行元器件之间的数据通讯。
7、通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，通过所述连接通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述连接通孔与所述器件引脚对接，所述导电层伸入所述附加通孔内。制作附加通孔，避免粘装膜阻碍器件引脚、导电层、以及电路引脚的电连接。根据需要可以采用激光烧熔、等离子清洁、或化学溶剂蚀刻的方法。
8、在所述连接通孔的内壁设有保护层，所述保护层用于在制作所述附加通孔时保护所述基板。制作所述附加通孔，可以使用但不限于化学蚀刻、或钻孔的工艺，此时需要穿过连接通孔，可能会对连接通孔的内壁造成损伤，进而对基板、电路层造成损伤，保护层可以保护连接通孔的内壁不受损伤。进一步的，保护层可以是有助于导电层电连接的材料，此时保护层可以与电路引脚接触，有助于电路引脚与导电层的电连接。譬如，所述保护层可以是金属薄膜，被预先溅镀或蒸镀在连接通孔的内壁，这样可以在化学蚀刻过程中，保护所述连接通孔内壁材料不至于被暴露于蚀刻溶剂或离子中，而且这样的金属薄层也可以提高随后在连接通孔中电镀的导电层的导电性。
9、在制作所述导电层后，在所述基板上设置封装层，两个所述元器件被所述封装层和所述基板包裹封装；或者，在将所述元器件安放于所述基板后、制作所述导电层形之前，在所述基板上设置封装层，两个所述元器件被所述封 装层和所述基板包裹封装。采用封装层将元器件包封，可以保护元器件少受环境影响，并且封装层可以覆盖基板，保护基板以及基板上的电路层，避免弯折、划伤。另一方面，可以通过封装层将元器件固定于基板，而不需要另外程序将元器件固定。
10、所述元器件为至少两个。本集成电路封装方法适用于两个以上元器件，进一步的，可以同时对两个以上的元器件进行操作，将以上的元器件安装于基板并实现元器件与电路层的电连接，提高效率、降低成本。
11、所述元器件为芯片、或电子元件。本集成电路封装方法适用于芯片或电子元件的封装，电子元件包括但不限于独立的电阻、电容、电感、二极管、或三极管，芯片包括但不限于裸片、晶圆、或者经过封装的集成芯片。可以使用相同的设备、工艺流程对芯片、或者电子元件进行封装，降低成本。
14、集成电路封装方法还包括在所述基板上设置封装层，至少两个所述元器件被所述封装层和所述基板包裹封装。封装层的目的主要是保护元器件不受外界环境因素的影响，譬如水汽、电磁辐射对元器件电性能的影响。同时，它也固定了多个元器件在基板上的相对位置，确保电连接的稳定性。在此发明中，在固化后，它更作为支撑板，让我们随后可以方便地在基板上进行连接通孔内壁导电层的制作。
13、所述元器件为至少两个时，所述元器件为芯片或电子元件，至少两个所述元器件当中，包括至少一个芯片和至少一个电子元件。可以同时对芯片和电子元件进行封装，提高效率，降低成本。
14、所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的柔性电路板。通过本集成电路封装方法将元器件安装于基板，并实现元器件与基板上电路层的电连接，当基板为柔性电路板或多层柔性电路板时，可以保持整体的柔性，可以用于可穿戴设备等。
15、一种集成封装电路，包括：元器件，所述元器件设有器件引脚；基板，基板的顶面、或者所述基板的底面、或者所述基板内设有电路层，所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对 接；其中，所述元器件安装于基板，所述器件引脚朝向所述基板，所述连接通孔的第一开口与所述器件引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述器件引脚和所述电路引脚电连接。通过连接通孔对接，制作导电层，制作工艺简单、成本低，保障集成封装电路的性能。
16、所述基板为柔性电路板、或所述基板包括至少两层层叠设置的柔性电路板。通过本集成封装电路的结构设置，当基板为柔性电路板或多层柔性电路板时，可以保持整体的柔性，可以用于可穿戴设备等。
17、所述电路层为功能电路，电路层具有一定的电子功能；或者所述电路层本身构成电子元件，包括但不限于天线。本集成封装电路结构的电路层适用范围广，可以实现多种功能的集成。
18、所述元器件安装于所述基板的顶面，所述基板的顶面设有所述电路层，所述元器件与所述基板之间设有绝缘介质，所述绝缘介质设有附加通孔，所述附加通孔与所述连接通孔的第一开口相连通，所述导电层伸入所述附加通孔与所述器件引脚电连接。元器件与基板之间设有绝缘介质，避免元器件对基板顶面的电路层或其他导电的结构产生影响，当元器件的器件引脚可以有两个以上，其中部分器件引脚通过本发明的结成电路封装方法与基板或电路层连接，绝缘介质可以避免另外的器件引脚对基板或电路层产生影响。进一步的，可以将绝缘介质选择为粘性材料，将元器件粘贴固定于基板。
19、所述基板的顶面设有电路层、或/和所述基板的底面设有电路层、或/和所述基板内设有电路层，所述器件引脚为至少两个，其中一个所述器件引脚至少与其中一个所述电路层电连接，另有一个所述器件引脚至少与余下另一个所述电路层电连接。基板设有两层以上的电路层，元器件通过不同的器件引脚同时与至少两层不同的电路层电连接，扩展电路功能。
附图说明
图1为本发明实施例一集成电路封装方法示意图一；
图2为本发明实施例一集成电路封装方法示意图二；
图3为本发明实施例一集成电路封装方法示意图三；
图4为本发明实施例一集成电路封装方法示意图四；
图5为本发明实施例一集成电路封装方法示意图五；
图6为本发明实施例二集成电路封装方法示意图一；
图7为本发明实施例二集成电路封装方法示意图二；
图8为本发明实施例二集成电路封装方法示意图三；
图9为本发明实施例二集成电路封装方法示意图四；
图10为本发明实施例三集成电路封装方法示意图一；
图11为本发明实施例三集成电路封装方法示意图二；
图12为本发明实施例三集成电路封装方法示意图三；
图13为本发明实施例三集成电路封装方法示意图四。
附图标记说明：
100、基板，110a、110b、电路层，120a、120b、连接通孔，120c、第一开口，120d、第二开口，121a、121b、保护层，200、元器件，210a、210b、器件引脚，300、绝缘介质，400a、400b、导电层。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
实施例一
本实施例中，如图5所示，集成封装电路包括：元器件200、基板100。元器件200安装于基板100的顶面，基板100的顶面、底面分别设有电路层110a、110b，元器件200与基板100之间设有绝缘介质300(本实施例中，绝缘介质300同时也是粘装膜)。元器件200设有器件引脚210a、210b，器件引脚210a、210b朝向基板100，电路层110a、110b设有电路引脚，基板100设有连接通孔120a、120b，连接通孔120a、120b与电路引脚对接，连接通孔120a、120b的第一开口120c与器件引脚210a、210b对接，连接通孔120a、 120b的第二开口120d为操作窗口，绝缘介质300(粘装膜)设有附加通孔，附加通孔与连接通孔120a、120b的第一开口120c相连通，连接通孔120a、120b内设有导电层400a、400b，导电层400a、400b伸入附加通孔与器件引脚210a、210b电连接。其中，绝缘介质300将元器件200与基板100隔开，绝缘介质300(粘装膜)可以避免元器件200对基板100顶面的电路层110a、110b或其他导电的结构产生影响，当元器件200的器件引脚210a、210b可以有两个以上，其中部分器件引脚210a、210b通过本发明的结成电路封装方法与基板100或电路层110a、110b连接，绝缘介质300可以避免另外的器件引脚210a、210b对基板100或电路层110a、110b产生影响；本实施例中，绝缘介质300也是粘装膜，绝缘介质300(粘装膜)将元器件200粘贴于基板100。采用粘贴的方式将元器件200安放于基板100上，将元器件200安放于基板100的过程就可以将元器件200固定于基板100，节约步骤、提高效率、降低成本。但不限于此，可以是绝缘介质300仅起到隔离元器件200和基板100的作用，采用另外的方法将元器件200固定于基板100，也可以采用粘装膜将元器件200粘贴于基板100，但粘装膜不起到将元器件200与基板100隔离的作用。
本实施例中，集成电路封装方法，包括：如图1、2所示，基板100的顶面、底面分别具有电路层110a、110b，电路层110a、110b具有电路引脚，本实施例中，预先在基板100制作好电路层110a、110b，但不限于此，也可以在集成电路封装时再在基板100上制作电路层110a、110b，电路引脚可以是电路层110a、110b直接引出的连接部，也可以是和连接部电连接的扩展引脚，只要通过电路引脚能够和电路层110a、110b电连接均可。元器件200的器件引脚210a、210b包括但不限于元器件200内部引出的连接部、与连接部电连接的扩展脚，只要通过器件引脚210a、210b能够和元器件200电连接均可。使器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接。基板100设有连接通孔120a、120b，连接通孔120a、120b与电路引脚对接，本实施例中，基板100上预先制作好连接通孔120a、120b，但不限于此，根据需要，可以预先 在基板100上制作好连接通孔120a、120b、再进行集成电路封装，也可以在集成电路封装过程中在基板100上制作连接通孔120a、120b。
如图3所示，元器件200上设有器件引脚210a、210b的一面涂布粘装膜(不限于本实施例，可以在基板100涂布粘装膜)，元器件200具有器件引脚210a、210b的一面朝向基板100，将元器件200安放于基板100，此时，粘装膜将元器件200安装于基板100上。(本实施例中粘装膜同时是绝缘介质300，不限于本实施例，也可以不采用粘装膜粘贴元器件200)
如图4所示，通过连接通孔120a、120b的第二开口120d，使用激光烧熔、等离子清洁、或化学溶剂在粘装膜制作附加通孔，附加通孔将连接通孔120a、120b与器件引脚210a、210b对接，避免粘装膜阻碍器件引脚210a和210b、导电层400a和400b、以及电路引脚的电连接。
如图5所示，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b伸入附加通孔内，导电层400a、400b将器件引脚210a、210b与电路引脚电连接；器件引脚210a、210b位于基板100的顶面，通过连接通孔120a、120b的第二开口120d，可以从基板100的底面将元器件200的器件引脚210a、210b与电路层110a、110b电连接，这样就回避了元器件200对器件引脚210a、210b从顶部的遮挡。
按以上方法封装，可以降低集成电路封装的成本、节约封装时间。并且，降低基板100和元器件200构成的整体的厚度，甚至基板100和元器件200之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板100与元器件200设置其他材料)；不需要进行加热焊接的步骤，特别是针对超薄芯片200、柔性电路板的封装，可以避免较大温度变化所产生的***整体热机械应力分布，以及对元器件200性能的影响。
此外，在制作导电层400a、400b后，在基板100上设置封装层，元器件200被封装层和基板100包裹封装；或者，在将元器件200安放于基板100后、制作导电层400a、400b形之前，在基板100上设置封装层，两个元器件200被封装层和基板100包裹封装。采用封装层将元器件200包封，可以保护元器件 200，并且封装层可以覆盖基板100，保护基板100以及基板100上的电路层110a、110b，避免弯折、划伤。另一方面，可以通过封装层将元器件200固定于基板100，而不需要另外程序将元器件200固定。
其中，连接通孔120a、120b与器件引脚210a、210b对接，器件引脚210a、210b至少部分位于连接通孔120a、120b的第一开口120c附近、或深入连接通孔120a、120b内，使得导电层400a、400b可以与器件引脚210a、210b电连接；电路引脚和连接通孔120a、120b对接，电路引脚至少部分位于连接通孔120a、120b的第一开口120c附近、或第二开口120d附近、或连接通孔120a、120b内壁的附近，使得导电层400a、400b可以与电路引脚电连接；元器件200可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。元器件200可以通过连接通孔120a、120b、导电层400a、400b固定于基板100，也可以是，元器件200通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板100。
其中，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，将导电粘接材料从连接通孔120a、120b的第二开口120d送入连接通孔120a、120b内，使导电粘接材料粘接于连接通孔120a、120b的内壁和器件引脚210a、210b上构成导电层400a、400b。采用从第二开口120d送入导电粘接材料的方式，可以在基板100的背面进行操作，而不会被元器件200干扰，通过粘接的方式将导电粘接材料粘附于连接通孔120a、120b的内壁和与连接通孔对接的器件引脚上，在适当加热或化学处理后，可以同时形成机械和电连接，也确保稳定的导电连接性能。导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆，形成如图9所示的结构，可以根据工艺需要或者基板100材质、连接通孔120a、120b内壁的性质，选择一种或多种的组合。
或者，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，采用丝网印刷在连接通孔120a、120b内设置导电粘接材料。丝网印刷是电路层110a、110b常用制作方法，采用丝网印 刷的方式制作导电层400a、400b，设备通用、可以和电路层110a、110b的制作同步进行，节约工艺流程，进一步降低成本。
或者，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，采用电镀的方式制作导电层400a、400b，形成如图5所示的结构。可以获得很好的导电性能，电镀可以控制导电层400a、400b的厚度，获得理想的导电性能。
进一步的，可以在很大面积的大面板上同时安装多个元器件200，大面板上的批量处理进一步减低成本、节约封装时间。批量生产时，采用大平板的载体，将多组元器件200排列于载体上，将载体覆盖于基板100顶面，使用粘装膜将元器件200粘贴于基板100，将载体与元器件200脱离(可以是采用光敏或热敏材料将元器件200安装于载体，改变温度或光照使载体和元器件200脱离)，然后进行上述步骤2-4，最后根据预设的分组，将基板100裁剪为多个子板，每个子板对应一组元器件200，每个子板都是独立的。如此，可以大批量进行封装作业，大幅提高生产效率。(其中，粘装膜可以同时是绝缘材料)
本实施例中，基板100的顶面和底面分别设有电路层110a、110b，芯片同时与电路层110a、110b电连接；但不限于此，可以是，基板100内嵌设有电路层110a、110b，器件引脚210a、210b与电路层110a、110b电连接；还可以是基板100的顶面设有电路层110a、110b、或/和基板100的底面设有电路层110a、110b、或/和基板100内设有电路层110a、110b，器件引脚210a、210b为至少两个，其中一个器件引脚210a、210b至少与其中一个电路层110a、110b电连接，另有一个器件引脚210a、210b至少与余下另一个电路层110a、110b电连接。基板100设有两层以上的电路层110a、110b，元器件200通过不同的器件引脚210a、210b同时与至少两层不同的电路层110a、110b电连接，扩展电路功能。
本实施例中，可以是，基板100为柔性电路板；或者，基板100包括至少两层层叠设置的柔性电路板。通过本集成电路封装方法将元器件200安装于基板100，并实现元器件200与基板100上电路层110a、110b的电连接，元器件 200、基板100构成的整体厚度小，可以保持整体的柔性，可以用于可穿戴设备等。
其中，元器件200为芯片、或电子元件。本集成电路封装方法适用于芯片或电子元件的封装，电子元件包括但不限于独立的电阻、电容、电感、二极管、或三极管，芯片包括但不限于裸片、晶圆、或者经过封装的集成芯片。可以使用相同的设备和工艺流程对芯片或者电子元件进行封装，降低成本。
其中，图1至6仅示例单个元器件200的结构，但不限于此，还可以是，元器件200为至少两个。本集成电路封装方法适用于两个以上元器件200，进一步的，可以同时对两个以上的元器件200进行操作，将以上的元器件200安装于基板100并实现元器件200与电路层110a、110b的电连接，提高效率、降低成本。当元器件200为至少两个时，可以是，至少两个元器件200当中，包括至少一个芯片和至少一个电子元件。可以同时对芯片和电子元件进行封装，提高效率，降低成本。当在基板100上设置封装层时，可以选择封装单个元器件200或封装两个以上元器件200。封装层的目的主要是保护元器件不受外界环境因素的影响，譬如水汽、电磁辐射对元器件电性能的影响。同时，它也固定了多个元器件在基板上的相对位置，确保电连接的稳定性。在此发明中，在固化后，它更作为支撑板，让我们随后可以方便地在基板上进行连接通孔内壁导电层的制作。此外，还可以在一个基板100上设置两个以上的封装层，封装层相互之间留有间隙，可以提供更大的曲率，使基板100、元器件200、封装层构成的整体更具装柔性，特别是当基板100为柔性电路板或基本为两成以上的柔性电路板构成时，能够使集成封装电路保持这种柔性，使集成封装电路可以应用于例如可穿戴设备这类需要保持柔性的场合。
其中，电路层110a、110b为功能电路，电路层110a、110b具有一定的电子功能；或者电路层110a、110b本身构成电子元件，包括但不限于天线。本集成封装电路结构的电路层110a、110b适用范围广，可以实现集成多种功能。
实施例二
实施例二与实施例一的区别在于：
在连接通孔120a、120b的内壁设有保护层121a、121b，保护层121a、121b用于在制作附加通孔时保护基板100。可以在进行集成电路封装之前，预先在基板100制作好保护层121a、121b；也可以在制作导电层400a、400b之前制作保护层121a、121b。制作附加通孔，可以使用但不限于化学蚀刻、或钻孔的工艺，此时需要穿过连接通孔120a、120b，可能会对连接通孔120a、120b的内壁材料造成损伤，进而对基板100、电路层110a、110b造成损伤，保护层121a、121b可以保护连接通孔120a、120b的内壁在制作连接通孔或者附加通孔的过程中不受损伤。进一步的，保护层121a、121b可以是有助于导电层400a、400b电连接的材料，此时保护层121a、121b可以与电路引脚接触，有助于电路引脚与导电层400a、400b的电连接。
或者，连接通孔120a、120b的内壁设有辅助层，辅助层用于辅助制作导电层400a、400b，使导电层400a、400b更好地与器件引脚210a、210b、电路引脚电连接，或者更好的附着于连接通孔120a、120b的内壁。
如图6至9所示，本实施例中，连接通孔120a、120b的内壁设有保护层121a、121b，保护层121a、121b同时也是辅助层，并且保护层121a、121b(辅助层)采用与电路层110a、110b相同的材料制作，例如电路层110a、110b采用铜，保护层121a、121b(辅助层)也采用铜，进一步提高电连接性能。但不限于本实施例，可以根据需要，可以采用其他材料，可以单独设置提供保护的保护层121a、121b或者辅助电连接的辅助层。如图6所示，本实施例中，保护层121a、121b(辅助层)与电路层110a、110b电连接；如图7所示，将元器件200安放于基板100上，粘装膜(绝缘介质300)将元器件200粘贴于基板100；如图8所示，在粘装膜(绝缘材料)制作辅助通孔；如图9所示，在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b将器件引脚210a、210b和电路引脚电连接。其中，图9所示的导电层400a、400b的形态为采用焊球的方法制作所述导电层400a、400b；但不限于此，也可以采用电镀的方法制作所述导电层400a、400b，最终获得的导电层形态请参考图13。 辅助层(保护层121a、121b)直接与电路引脚电连接，电连接效果好，并且可以延长电路引脚，缩小导电层400a、400b的体积，有利于导电层400a、400b的制作，也利于降低成本。
实施例三
实施例三与实施例一的区别在于：
在封装过程中再制作连接通孔120a、120b，包括步骤：
如图10所示，基板100的顶面、底面分别具有电路层110a、110b，电路层110a、110b具有电路引脚。
如图11所示，元器件200上设有器件引脚210a、210b的一面涂布粘装膜(不限于本实施例，可以在基板100涂布粘装膜)，元器件200具有器件引脚210a、210b的一面朝向基板100，将元器件200安放于基板100，此时，粘装膜将元器件200安装于基板100上。
如图12所示，在所述基板100上制作连接通孔120a、120b，使器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接，连接通孔120a、120b的第二开口120d可供在连接通孔120a、120b内制作导电层400a、400b、在粘装膜制作附加通孔，附加通孔将连接通孔120a、120b与器件引脚210a、210b对接。
如图13所示，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b伸入附加通孔内，导电层400a、400b将器件引脚210a、210b与电路引脚电连接。
本实施例中，预先在基板100制作好电路层110a、110b，但不限于此，也可以根据布线的需要和降低成本的考虑，在集成电路封装时再在基板100上制作电路层110a、110b，例如，采用电镀的方式制作导电层400a、400b。也可以，预先制作其中部分电路层110a、110b，在在集成电路封装时再在基板100上制作另一部分电路层110a、110b。在电镀前，采用溅镀或者蒸镀的工艺制作辅助层。采用电镀的方式制作导电层400a、400b的工艺还包括在电镀前，采用溅镀 或者蒸镀的工艺制作辅助层，然后再电镀。溅镀或者蒸镀的辅助层能够更好地与电路引脚电连接，电镀的导电层400a、400b附着于辅助层。溅镀或者蒸镀辅助层，一方面可以提高电镀的质量，另一方面也能够更好的实现导电层400a、400b与电路引脚的电连接。在基板100的底面设置脱模层，脱模层具有与电路层110a、110b轮廓的模型槽，在制作连接通孔120a、120b后，在制作导电层400a、400b的同时在模型槽内形成电路层110a、110b，例如采用电镀的方式制作导电层400a、400b，电镀的同时中在在模型槽内形成电路层110a、110b。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种集成电路封装方法，其特征在于，包括：
    基板的顶面、或者基板的底面、或者基板内具有电路层，所述电路层具有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接，将元器件安放于所述基板，所述元器件朝向所述基板的一面具有器件引脚，使所述器件引脚与所述连接通孔的第一开口对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，所述导电层将所述器件引脚与所述电路引脚电连接。
  2. 根据权利要求1所述的集成电路封装方法，其特征在于，通过所述连接通孔的第二开口在所述连接通孔内制作导电层的过程中，将导电粘接材料从所述连接通孔的第二开口送入所述连接通孔内，使所述导电粘接材料粘接于所述连接通孔的内壁和所述器件引脚上构成所述导电层。
  3. 根据权利要求2所述的集成电路封装方法，其特征在于，所述导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆。
  4. 根据权利要求2所述的集成电路封装方法，其特征在于，采用丝网印刷在所述连接通孔内设置所述导电粘接材料。
  5. 根据权利要求1所述的集成电路封装方法，其特征在于，采用电镀的方式制作所述导电层。
  6. 根据权利要求1所述的集成电路封装方法，其特征在于，在所述元器件与所述基板之间设置粘装膜，所述粘装膜将所述元器件粘贴于所述基板。
  7. 根据权利要求6所述的集成电路封装方法，其特征在于，通过所述连接通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述连接通孔与所述器件引脚对接，所述导电层伸入所述附加通孔内。
  8. 根据权利要求7所述的集成电路封装方法，其特征在于，在所述连接通孔的内壁设有保护层，所述保护层用于在制作所述附加通孔时保护所述基板。
  9. 根据权利要求1所述的集成电路封装方法，其特征在于，还包括：在制作所述导电层后，在所述基板上设置封装层，两个所述元器件被所述封装层和所述基板包裹封装；
    或者，在将所述元器件安放于所述基板后、制作所述导电层之前，在所述基板上设置封装层，两个所述元器件被所述封装层和所述基板包裹封装。
  10. 根据权利要求1所述的集成电路封装方法，其特征在于，所述元器件为至少两个。
  11. 根据权利要求10所述的集成电路封装方法，其特征在于，还包括：在所述基板上设置封装层，至少两个所述元器件被所述封装层和所述基板包裹封装。
  12. 根据权利要求10所述的集成电路封装方法，其特征在于，所述元器件为芯片或电子元件，至少两个所述元器件当中，包括至少一个芯片和至少一个电子元件。
  13. 根据权利要求1所述的集成电路封装方法，其特征在于，所述元器件为芯片、或电子元件。
  14. 根据权利要求1至13任一项所述的集成电路封装方法，其特征在于，所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的柔性电路板。
  15. 一种集成封装电路，其特征在于，包括：
    元器件，所述元器件设有器件引脚；
    基板，所述基板的顶面、或者所述基板的底面、或者所述基板内设有电路层，所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；
    其中，所述元器件安装于基板，所述器件引脚朝向所述基板，所述连接通孔的第一开口与所述器件引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述器件引脚和所述电路引脚电连接。
  16. 根据权利要求15所述的集成封装电路，其特征在于，所述基板为柔性电路板、或所述基板包括至少两层层叠设置的柔性电路板。
  17. 根据权利要求15所述的集成封装电路，其特征在于，所述电路层为功能电路，或者所述电路层本身构成电子元件。
  18. 根据权利要求15所述的集成封装电路，其特征在于，所述元器件安 装于所述基板的顶面，所述基板的顶面设有所述电路层，所述元器件与所述基板之间设有绝缘介质，所述绝缘介质设有附加通孔，所述附加通孔与所述连接通孔的第一开口相连通，所述导电层伸入所述附加通孔与所述器件引脚电连接。
  19. 根据权利要求15至18任一项所述的集成封装电路，其特征在于，所述基板的顶面设有电路层、或/和所述基板的底面设有电路层、或/和所述基板内设有电路层，所述器件引脚为至少两个，其中一个所述器件引脚至少与其中一个所述电路层电连接，另有一个所述器件引脚至少与余下另一个所述电路层电连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210358883A1 (en) * 2018-10-11 2021-11-18 Shenzhen Xiuyi Investment Development Partnership (Limited Partnership) Fan-out packaging method employing combined process

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113155313B (zh) * 2021-03-16 2023-04-07 中国电子科技集团公司第二十九研究所 一种扇出型封装温度分布原位模拟结构及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407864A (en) * 1992-07-24 1995-04-18 Samsung Electronics Co., Ltd. Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip
US20090135574A1 (en) * 2007-11-22 2009-05-28 Shinko Electric Industries Co., Ltd. Wiring board, semiconductor device having wiring board, and method of manufacturing wiring board
CN102623427A (zh) * 2012-03-31 2012-08-01 苏州晶方半导体科技股份有限公司 半导体封装结构及其封装方法
CN102881799A (zh) * 2011-07-11 2013-01-16 郭文平 一种高压led芯片及制作方法
CN103618041A (zh) * 2013-12-11 2014-03-05 江阴长电先进封装有限公司 一种esd保护的led封装结构及其封装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
JP3176307B2 (ja) * 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
KR101053761B1 (ko) * 2008-11-11 2011-08-02 주식회사 동부하이텍 이미지 센서의 제조 방법
JP5406389B2 (ja) * 2012-03-01 2014-02-05 株式会社フジクラ 部品内蔵基板及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5407864A (en) * 1992-07-24 1995-04-18 Samsung Electronics Co., Ltd. Process for mounting a semiconductor chip and depositing contacts into through holes of a circuit board and of an insulating interposer and onto the chip
US20090135574A1 (en) * 2007-11-22 2009-05-28 Shinko Electric Industries Co., Ltd. Wiring board, semiconductor device having wiring board, and method of manufacturing wiring board
CN102881799A (zh) * 2011-07-11 2013-01-16 郭文平 一种高压led芯片及制作方法
CN102623427A (zh) * 2012-03-31 2012-08-01 苏州晶方半导体科技股份有限公司 半导体封装结构及其封装方法
CN103618041A (zh) * 2013-12-11 2014-03-05 江阴长电先进封装有限公司 一种esd保护的led封装结构及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210358883A1 (en) * 2018-10-11 2021-11-18 Shenzhen Xiuyi Investment Development Partnership (Limited Partnership) Fan-out packaging method employing combined process

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