WO2018098651A1 - 集成电路***及封装方法 - Google Patents

集成电路***及封装方法 Download PDF

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Publication number
WO2018098651A1
WO2018098651A1 PCT/CN2016/107835 CN2016107835W WO2018098651A1 WO 2018098651 A1 WO2018098651 A1 WO 2018098651A1 CN 2016107835 W CN2016107835 W CN 2016107835W WO 2018098651 A1 WO2018098651 A1 WO 2018098651A1
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Prior art keywords
device group
carrier
molding material
layer
circuit layer
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PCT/CN2016/107835
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English (en)
French (fr)
Inventor
胡川
刘俊军
郭跃进
普莱克爱德华⋅鲁道夫
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深圳修远电子科技有限公司
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Application filed by 深圳修远电子科技有限公司 filed Critical 深圳修远电子科技有限公司
Priority to PCT/CN2016/107835 priority Critical patent/WO2018098651A1/zh
Priority to CN201680090825.4A priority patent/CN109997222B/zh
Priority to US16/465,455 priority patent/US10930634B2/en
Publication of WO2018098651A1 publication Critical patent/WO2018098651A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention belongs to the field of electronics, and in particular relates to an integrated circuit system and a packaging method.
  • the present invention overcomes the deficiencies of the prior art, and provides an integrated circuit system and a packaging method, which can integrate more devices on an integrated circuit system, obtain more functions, and have a small overall system size, high production efficiency, and low cost. low.
  • An integrated circuit system packaging method comprising the steps of: curing: a first carrier and a second carrier are oppositely disposed, a first device group on the first carrier and a second device group on the second carrier are located in the Between the first carrier and the second carrier, a molding material is disposed between the first carrier and the second carrier, and the first device group and the second device group are respectively in contact with the molding material Curing the molding material such that the first device group and the second device group are respectively mounted on both sides of the molding material; detaching: the first carrier from the first device group and the Disengaging the molding material to detach the second carrier from the second device group and the molding material; connecting: forming a connection hole in the molding material, and forming a conductive layer to extend the conductive layer The connection hole, the conductive layer will be The first device group is electrically coupled to the second device group.
  • the first device group is mounted to the first carrier by a thermosensitive adhesive material, and in the detaching step, heating or cooling the thermosensitive adhesive material to make the first
  • the carrier is detached from the first device group; or/and the second device group is mounted to the second carrier by a heat-sensitive adhesive material, and in the detaching step, the heat-sensitive adhesive is heated or cooled a material that disengages the second carrier from the second device set.
  • the integrated circuit system packaging method further includes: in the curing step, providing an intermediate layer between the first carrier and the second carrier to distribute the molding material to the first Between a carrier and the intermediate layer, and between the second carrier and the intermediate layer, the molding material is cured such that the intermediate layer is embedded in the molding material.
  • the intermediate layer is a flexible circuit board; or, at least two flexible circuit boards are stacked to form the intermediate layer; or the intermediate layer is a shielding layer; or, the intermediate layer
  • the electronic component itself constitutes an electrical connection between the intermediate layer and the first device group or the second device.
  • the intermediate layer is provided with a base circuit layer electrically connecting the base circuit layer to the first device group or electrically connecting the base circuit layer to the second device group.
  • the molding material is a silicone molded plastic, or a molded resin.
  • the integrated circuit system packaging method further includes: the first device group, the second device group, and the molding material constituting a substrate, after the detaching step, at two of the substrates
  • the first circuit layer and the second circuit layer are respectively fabricated on the side, the first circuit layer is electrically connected to the first device group, and the second circuit layer is electrically connected to the second device group.
  • the pins of the devices of the first device group are oriented toward the first carrier, and the pins of the devices of the second device group are oriented toward the second carrier.
  • the first circuit layer is provided with a first connection port, and a device is mounted on the first circuit layer to electrically connect the device to the first connection port; or
  • the second circuit layer is provided with a second connection port, and the device is mounted on the second circuit layer to electrically connect the device to the second connection port.
  • the integrated circuit system packaging method further includes: before the curing step, fabricating a first circuit layer on the first carrier, and setting a first device group on the first circuit layer, the a circuit layer electrically connected to the first device group; in the detaching step, the first circuit layer and the first device group are both detached from the first carrier, the first circuit layer and The first device group is commonly mounted on the molding material; or/and, before the curing step, forming a second circuit layer on the second carrier and a second device group on the second circuit layer, The second circuit layer is electrically connected to the second device group; in the detaching step, the second circuit layer and the second device group are both separated from the first carrier, and the second circuit A layer and the second device group are mounted together on the molding material.
  • the first device group, the second device group, and the molding material constitute a substrate having an area greater than 10,000 square centimeters.
  • the first device group or/and the second device group includes an invalid device for making the first device group or/and the second device group
  • the density distribution of the device in the distribution of the molding material is balanced to prevent warpage of the molding material.
  • the first device group and the second device group are staggered on both sides of the molding material such that the first device group and the second device group are in the molding material.
  • the density of the side distribution is balanced to avoid warpage of the molding material.
  • At least two of the first device groups are disposed on the first carrier, and at least two of the second device groups are disposed on the second carrier, through the curing step, After the detaching step and the connecting step, the first device group, the second device group, and the molding material constitute a substrate, and the substrate is cut into at least two circuit boards.
  • the first device group includes at least one device
  • the second device group includes at least one device, the device being a chip or a separate electronic component.
  • An integrated circuit system comprising: a first device group detached from a first carrier, a second device group detached from a second carrier, and a cured molding material; wherein a molding material is located in the first device group And the second device group, the first device group and the second device group are in contact with the molding material, and the first device group and the second device group are respectively mounted on the molding material On both sides, the molding material is provided with a connection hole and a conductive layer, and the conductive layer extends into the connection hole, The conductive layer electrically connects the first device group to the second device group.
  • the molding material is a silicone molded plastic, or a molded resin.
  • the first device group, the second device group, and the molding material constitute a substrate, and two sides of the substrate are respectively provided with a first circuit layer and a second circuit layer, A first circuit layer is electrically coupled to the first device group, and the second circuit layer is electrically coupled to the second device group.
  • the first circuit layer is provided with a first connection port, the first circuit layer is provided with a device, and the device is electrically connected to the first connection port; or, the second The circuit layer is provided with a second connection port, the second circuit layer is provided with a device, and the device is electrically connected to the second connection port.
  • the integrated circuit system further includes an intermediate layer disposed between the first device group and the second device group, the intermediate layer being embedded in the molding material.
  • the intermediate layer is a flexible circuit board; or at least two flexible circuit boards are stacked to form the intermediate layer; or the intermediate layer is a shielding layer; or the intermediate layer itself
  • An electronic component is formed that electrically connects the intermediate layer to the first device group or the second device.
  • the intermediate layer is provided with a base circuit layer electrically connecting the base circuit layer to the first device group or electrically connecting the base circuit layer to the second device group.
  • the first device group includes at least one device
  • the second device group includes at least one device, the device being a chip or a separate electronic component.
  • the first device group or/and the second device group includes an invalid device for making the first device group or/and the second device group The device distributes the density on both sides of the molding material to avoid warping of the molding material.
  • An integrated circuit system packaging method comprising the steps of: (1) curing: a first carrier and a second carrier are oppositely disposed, a first device group on the first carrier and a second device group on the second carrier Located between the first carrier and the second carrier, a molding material is disposed between the first carrier and the second carrier, and the first device group and the second device group are respectively Contacting the molding material to cure the molding material, and mounting the first device group and the second device group to the molding material Both sides of the material; (2) detachment: detaching the first carrier from the first device group and the molding material, and the second carrier from the second device group and the molding material Disengagement; (3) wiring: making a connection hole in the molding material, and forming a conductive layer to extend the conductive layer into the connection hole, the conductive layer to the first device group and the second layer The device group is electrically connected. The portion of the conductive layer that protrudes into the connection hole may be attached only to the inner wall of the connection hole, or may completely or partially fill the connection hole.
  • the substrate may be omitted, and the first device group and the second device group are respectively disposed on both sides of the molding material, and the devices accommodated are greatly increased, and the devices on both sides can be electrically connected to each other through the connection holes, and the devices can be on both sides.
  • the number of connection points on the surface is increased, the transmission bandwidth and the operation speed are increased, and high system integration is obtained.
  • the devices on both sides of the molding material are electrically connected by means of connecting holes, and the connecting holes are opened in the molding material without occupying extra space; in particular, for ultra-thin circuit boards, flexible circuit boards, and wearable device boards And the like, the method of the present invention can well maintain the overall ultra-thin, flexible characteristics of the obtained integrated circuit system.
  • the cured molding material plays a role of supporting and fixing.
  • the second device group of the first device group is simultaneously mounted on the molding material, and the device group device is symmetrically placed on the two outer surfaces of the molding material. , can reduce the thermo-mechanical stress, which is of great significance for parallel processing on large-size panels.
  • the traditional system packaging process rearranges the device on a carrier into a large-sized panel or wafer, and then places the molding material to encapsulate. After the molding material is cured, the molding material containing all the devices is completely detached and used as a new substrate. Perform the subsequent process. Because of the large difference in thermo-mechanical properties between the device material silicon and the molding material, after curing from the carrier, the substrate will have a large warpage, which seriously affects the implementation of the subsequent process.
  • the first device group and the second device group are respectively mounted on both sides of the molding material, and the density of the devices on both sides is kept as balanced as possible, so that the warpage of the substrate formed after the molding material is cured can be effectively reduced.
  • first device group and the second device group are disposed on the first carrier and the second carrier, and the flow operation is performed on the large-area panel, and the process involved is simple and the production efficiency is high. Moreover, by using the first carrier and the second carrier, it is ensured that the two outer surfaces of the molding material after detachment are flat, and the subsequent process can be performed without additional surface planarization treatment.
  • the first device group is mounted on the first carrier by a thermosensitive adhesive material, and in the detaching step, heating or cooling the thermosensitive adhesive material to cause the first carrier and the first a device group is detached; or/and the second device group is mounted to the second carrier by a thermosensitive adhesive material, and in the detaching step, the thermosensitive adhesive material is heated or cooled to cause the The second carrier is detached from the second device group.
  • the first device group, or the second device group, or a colleague may be pasted with the heat sensitive material to paste the first device group and the second device group, and when heated or cooled, the first carrier is detached, or the second carrier is detached, Or the first carrier and the second carrier are simultaneously detached to prepare for the wiring step.
  • the use of a heat sensitive material reduces the mechanical stress of the detachment step, without damaging the device set or scratching the surface.
  • an intermediate layer is disposed between the first carrier and the second carrier such that the molding material is distributed between the first carrier and the intermediate layer, and Between the second carrier and the intermediate layer, the molding material is cured such that the intermediate layer is embedded in the molding material without occupying extra space.
  • Adding an intermediate layer before the molding material is uncured can improve the performance of the integrated circuit system, and can impart different characteristics to the intermediate layer as needed, so that the final high integrated circuit system can obtain better characteristics.
  • the intermediate layer can be a circuit layer.
  • the carrier can improve the integration of the integrated circuit system after being electrically connected.
  • the intermediate layer is a flexible circuit board; or, at least two flexible circuit boards are stacked to form the intermediate layer; and a circuit board is disposed between the molding materials as an intermediate layer to expand the function of the entire integrated circuit system.
  • the intermediate layer is a shielding layer; avoiding the first device group and the second device on both sides of the molding material The work of the components does not interfere with each other, ensuring the performance of the entire integrated circuit system.
  • the intermediate layer itself constitutes an electronic component that is electrically connected to the first device group or the second device. Including but not limited to antennas, capacitors, etc., can extend the circuit function, and does not occupy extra space.
  • the intermediate layer is provided with a base circuit layer, and in the step of connecting, the base circuit layer may be electrically connected to the first device group through a connection hole, or/and the base circuit layer and the The second device group is electrically connected.
  • the first device group, the second device group, and the intermediate layer are similar to multilayer circuits, which can increase circuit functions.
  • the base circuit layer may be disposed on one side of the intermediate layer facing the first device group, or facing one side of the second device group, or embedded in the intermediate layer, or both sides of the intermediate layer.
  • the molding material is a moldable molding material such as silicone molded plastic (R 2 SiO x ) or molded resin, including but not limited to polyimide, or polydimethylsiloxane, or poly pair. Xylene. These materials have good fluidity and can be filled with a gap between the first carrier and the second carrier, and the curing operation is simple and facilitates production.
  • the method further includes: forming, by the first device group, the second device group, and the molding material, a substrate after curing, after the detaching step, respectively forming a first circuit on both sides of the substrate And a second circuit layer electrically connecting the first circuit layer and the first device group, and electrically connecting the second circuit layer and the second device group.
  • the first circuit layer, the first device group, the second circuit layer, and the second device group are electrically connected to expand the circuit function. If the first device group is disposed on the first carrier, the pre-existing partial electrical connection between the first device groups may be performed, and the first circuit layer may be extended to extend the original connection; or may be between the first device groups. There is no electrical connection in advance, and electrical connection is made through the first circuit layer.
  • a partial electrical connection may be pre-existing between the second device groups, and the second circuit layer may be extended to extend the original connection; or the second device group may be pre-existed without electricity. Connection, electrical connection through the second circuit layer.
  • the pins of the device of the first device group face the first carrier, the pins of the device of the second device group face the second carrier. After the detachment step, the pins of the device are naturally exposed on both sides of the substrate, so that the first circuit layer and the second circuit layer are separately formed on both sides of the substrate, and the first circuit is formed. a layer electrically connected to the first device group, the second circuit layer and the second device The pieces are electrically connected. In this way, the first circuit layer may be directly formed on the surface of the molding material, or the first circuit layer may be electrically connected to the circuit board through the pins of the device after the first circuit layer is disposed on the other circuit board.
  • the second circuit layer may be directly formed on the surface of the molding material, or the second circuit layer may be disposed on the other circuit board, and the second device group is electrically connected to the device through the pins of the device.
  • the second circuit layer of the board may be directly formed on the surface of the molding material, or the second circuit layer may be disposed on the other circuit board, and the second device group is electrically connected to the device through the pins of the device.
  • the second circuit layer of the board may be directly formed on the surface of the molding material, or the second circuit layer may be disposed on the other circuit board, and the second device group is electrically connected to the device through the pins of the device.
  • the first circuit layer and the first device group are both detached from the first carrier, and the first circuit layer and the first device group are commonly mounted on the molding material.
  • the above “or/and” means that, as needed, the first circuit layer may be separately fabricated, or the second circuit layer may be separately fabricated, or the first circuit layer and the second circuit layer may be simultaneously formed.
  • the method of simultaneously fabricating the first circuit layer and the second circuit layer is: before placing the first device group and the second device group on each of the first carrier and the second carrier, the first carrier and the second carrier.
  • the first circuit layer and the second circuit layer are respectively provided in advance, respectively corresponding to the first device group and the second device group, and the placing process comprises aligning the first device group and the second device group respectively.
  • the circuit layer and the second circuit layer electrically connect the first circuit layer to the first device group, and the second circuit layer is electrically connected to the second device group.
  • the steps of curing, detaching, and wiring are continued, except that it is no longer necessary to make additional circuit layers on the outer surfaces of both sides of the substrate formed after detachment, simply by making A connection hole connecting the first circuit layer and the second circuit layer.
  • the bonding material is disposed between the first carrier, the second carrier, and the first circuit layer and the second circuit layer, so that after the detachment, the first circuit layer and the second circuit layer remain The two outer surfaces of the formed substrate.
  • the circuit layer is formed before the molding material is solidified, and the first circuit layer and the second circuit layer are generally made on the first carrier and the second carrier surface which are more flat and stronger than the molding material, which can be easily fabricated. Thinner line width The distance between the wiring can increase the bandwidth and speed of data communication; because the electrical connection is fixed before the molding material is cured, the relative position of the chip during the curing process can be avoided, which makes the electrical connection of the circuit layer extremely difficult.
  • the first circuit layer is provided with a first connection port, and the device is mounted on the first circuit layer to electrically connect the device with the first connection port; the first circuit layer is reserved for expansion.
  • the first connection port has an expansion function, and after the first circuit layer is fabricated, the device can be repositioned according to different needs, wherein the device can be a chip or an electronic component.
  • the second circuit layer is provided with a second connection port, and the device is mounted on the second circuit layer to electrically connect the device to the second connection port.
  • the second circuit layer is reserved with a second connection port for expansion, and has an expansion function, and after the second circuit layer is fabricated, the device can be re-mounted according to different needs, wherein the device can be a chip or an electronic component.
  • the chip is a die or a chip after the die is packaged.
  • the first device group comprises at least one device
  • the second device group comprises at least one device, the device being a chip or a separate electronic component. After completing a production process, it is possible to complete the installation of chips and electronic components at the same time with high efficiency.
  • the first device group and the second device group comprise more than one device, and the devices of the same group are all disposed on the carrier, and are uniformly installed and processed in parallel through the steps of curing, detaching, and connecting, and the efficiency is high.
  • the first device group, the second device group, and the molding material constitute a substrate, and the substrate is cut into at least two circuit boards.
  • the devices of the first device group and the second device group are mounted with a plurality of sets of the first device group and the second device group are simultaneously fixedly mounted by the molding material, and the connection holes and the conductive layer are simultaneously fabricated, and finally cut into circuits of a desired size. Board, high production efficiency.
  • the first device group is at least two
  • the second device group is at least two
  • each of the circuit boards includes at least one of the first device group or at least one of the second device groups. It is also possible to provide only one of the first device groups or only one second device group, and if necessary, the different boards that are tailored respectively comprise several devices in the first device group, or include the second device group. Several Device.
  • a large-plane circuit board can be fabricated to avoid warpage, ensure the performance of a large-plane circuit board, and at the same time reduce the cost of manufacturing a large-plane circuit board.
  • a large-scale substrate composed of a first device group, a second device group, and a molding material can be fabricated, and at the same time, warpage of a large-sized substrate can be avoided, and the possibility of continuing the subsequent process on the large substrate can be ensured. Quality, reducing production costs.
  • the first device group or/and the second device group includes an inactive device for causing the device of the first device group or/and the second device group to be in the forming
  • the density distribution on both sides of the material is balanced to avoid warpage of the molding material.
  • the device composition of the first device group and the second device group is often determined by the function to be implemented, and the size, size, and number may vary greatly. If only effective devices are used, the substrate may be formed due to uneven material distribution of the device. There are different thermo-mechanical stresses on both sides and there may be warpage during the manufacturing process.
  • the invalid device may be separately set in the first device group, or the invalid device may be separately set in the second device group, or the invalid device may be provided in the first device group and the second device group, as needed.
  • an invalid chip is added, and the invalid chip can offset the difference in volume and occupied area between different devices, so that the entire molding material is made.
  • the surface is balanced by the density occupied by the device, further reducing the warpage, reducing the difficulty of the manufacturing process, and improving the fabrication precision of the wiring circuit layer.
  • the use of ineffective devices can greatly reduce the possible warpage of large-sized substrates during fabrication.
  • the first device group and the second device group are staggered on both sides of the molding material to balance the density distribution of the devices of the first device group and the second device group on both sides of the molding material. Avoid warping of the molding material.
  • the device groups are staggered on the surface of the molding material to avoid possible warpage of the formed large-sized substrate during the manufacturing process.
  • the device components of the first device group and the second device group are often determined by the functions to be implemented, and the size and number may vary greatly. If only valid devices are used, the number of device groups placed increases as the size of the formed substrate increases. Increasing, if only the same device group is placed on the same side of the substrate, because the uneven distribution of the device materials causes different thermo-mechanical stresses on both sides of the formed substrate, the substrate is increased during the manufacturing process.
  • the first device group and the second device group may be alternately discharged on the first carrier and the second carrier, such that The density of the devices on both sides of the substrate formed is more uniform, and the stresses on both sides of the substrate after the first carrier and the second carrier are separated are more symmetrical, and warpage is less likely to occur.
  • the warpage of the formed large-sized substrate during the manufacturing process can be reduced, the difficulty of the manufacturing process can be reduced, and the fabrication precision of the wiring circuit layer can be improved.
  • FIG. 1 is a schematic structural diagram 1 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram 2 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram 3 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram 4 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram 5 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram 6 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram 7 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram 8 of a chip packaging method according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram 9 of a chip packaging method according to an embodiment of the present invention.
  • thermosensitive adhesive material 140
  • first circuit layer 210
  • second device group 220
  • second carrier 240
  • second circuit layer 300
  • molding material 310
  • connection hole 400
  • conductive layer 500, intermediate layer, 510, base circuit layer.
  • the integrated circuit system includes: a first device group 110 detached from the first carrier 120, a second device group 210 detached from the second carrier 220, and a cured molding material 300 as shown in FIGS. 1 to 6;
  • the molding material 300 is located between the first device group 110 and the second device group 210, the first device group 110 and the second device group 210 are in contact with the molding material 300, and the first device group 110 and the second device group 210 are respectively mounted on On both sides of the molding material 300, the molding material 300 is provided with a connection hole 310 and a conductive layer 400.
  • the conductive layer 400 extends into the connection hole 310.
  • the conductive layer 400 connects the first device group 110 and the second device. Group 210 is electrically connected.
  • the conductive layer 400 extending into the connection hole 310 may be attached only to the inner wall of the connection hole 310, or the connection hole 310 may be completely or partially filled.
  • the case where the conductive layer 400 is attached only to the inner wall of the connection hole 310 is as shown in FIG.
  • the first device group 110, the second device group 210, and the molding material 300 constitute a substrate, and the first circuit layer 140 and the second circuit layer 240 are respectively disposed on two sides of the substrate, and the first circuit layer 140 is The first device group 110 is electrically connected, and the second circuit layer 240 is electrically connected to the second device group 210.
  • An intermediate layer 500 is disposed between the first carrier 120 and the second carrier 220, and the intermediate layer 500 is embedded in the molding material 300.
  • the intermediate layer 500 is provided with a base circuit layer 510 electrically connecting the base circuit layer 510 to the first device group 110 or electrically connecting the base circuit layer 510 to the second device group 210.
  • a base circuit layer 510 may be disposed on both sides of the intermediate layer 500, or a base circuit layer 510 may be disposed on one of the sides.
  • the first device group 110, the second device group 210, and the intermediate layer 500 are similar to multilayer circuits, and can increase circuit functions.
  • the base circuit layer 510 may be provided on one side of the intermediate layer 500 facing the first device group 110, or facing one side of the second device group 210, or embedded in the intermediate layer 500, or both sides of the intermediate layer 500.
  • the intermediate layer 500 is a flexible circuit board; or, at least two flexible circuit boards are stacked to form the intermediate layer 500; and the circuit board is disposed between the molding materials 300 as the intermediate layer 500, and the whole is extended.
  • the function of an integrated circuit system The use of a flexible circuit layer and the use of the integrated circuit system packaging method of the present invention can be made very thin, and the resulting system as a whole can still maintain flexible performance.
  • the intermediate layer 500 is a shielding layer; the first device group 110 and the second device group 210 on both sides of the molding material 300 are prevented from interfering with each other to ensure the working performance of the entire integrated circuit system.
  • the intermediate layer 500 itself constitutes an electronic component that electrically connects the intermediate layer 500 with the first device group 110 or the second device. Including but not limited to antennas, capacitors, etc., can extend the circuit function, and does not occupy extra space.
  • the molding material 300 is a moldable molding material such as silicone molded plastic (R 2 SiO x ) or a molded resin including, but not limited to, polyimide, or polydimethylsiloxane, or a pair, as needed. Xylene. These materials have good fluidity, can fill the gap between the first carrier 120 and the second carrier 220, and the curing operation is simple, which is advantageous for production.
  • silicone molded plastic R 2 SiO x
  • a molded resin including, but not limited to, polyimide, or polydimethylsiloxane, or a pair, as needed.
  • Xylene Xylene.
  • the first circuit layer 140 is provided with a first connection port, and the first circuit layer 140 is provided with a device.
  • the device is electrically connected to the first connection port; or the second circuit layer 240 is provided with a second connection port, the second circuit layer 240 is attached with a device, and the device is electrically connected to the second connection port.
  • the first connection port and the second connection port are not shown in the figure.
  • the first device group 110 includes at least one device
  • the second device group 210 includes at least one device, the device being a chip or a separate electronic component.
  • electronic components include, but are not limited to, a store owner, a capacitor, an inductor, a triode, and a diode. After completing a production process, it is possible to complete the installation of chips and electronic components at the same time with high efficiency.
  • the first device group 110 and the second device group 210 comprise more than one device, and the devices of the same group are disposed on the carrier, and are uniformly installed and processed in parallel through the steps of curing, detaching, and connecting, and the efficiency is high.
  • Invalid devices are included in the first device group 110 or/and the second device group 210 for equalizing the density of the devices of the first device group 110 or/and the second device group 210 in the molding material 300, avoiding molding materials 300 warps occur.
  • the area of the substrate is greater than 10,000 square centimeters. According to the integrated circuit system packaging method of the present invention, a large-plane circuit board can be fabricated to avoid warpage, ensure the possibility and quality of the subsequent process on the large substrate, and reduce the manufacturing cost.
  • the main steps of the integrated circuit system packaging method include:
  • the first carrier 120 and the second carrier 220 are oppositely disposed, and the first device group 110 on the first carrier 120 and the second device group 210 on the second carrier 220 are both located first.
  • a molding material 300 is disposed between the first carrier 120 and the second carrier 220; as shown in FIG. 4, the first device group 110 and the second device group 210 Contacting the molding material 300 respectively, curing the molding material 300, and mounting the first device group 110 and the second device group 210 on both sides of the molding material 300;
  • connection hole 310 is formed in the molding material 300; as shown in FIG. 7, a conductive layer 400 is formed, and the conductive layer 400 is extended into the connection hole 310, and the conductive layer 400 is the first device.
  • Group 110 is electrically coupled to the second device group 210.
  • the conductive layer 400 extending into the connection hole 310 may be attached only to the inner wall of the connection hole 310, or the connection hole 310 may be completely or partially filled.
  • the conventional circuit board is provided with a device on only one side.
  • the first device group 110 and the second device group 210 are respectively disposed on both sides of the molding material 300, and the devices accommodated are greatly increased, and the devices on both sides can be electrically connected through the connection holes 310. Connections, connection points increase, transmission bandwidth, and operation speed are improved, and the obtained integrated circuit system has high performance. Moreover, the devices on both sides of the molding material 300 are electrically connected by means of the connection holes 310.
  • connection holes 310 are opened in the molding material 300 without occupying extra space; in particular, for ultra-thin circuit boards, flexible circuit boards, and wearable
  • the circuit board of the device, etc., using the method of the present invention, can well maintain the ultra-thin and flexible characteristics of the integrated circuit system.
  • the first device group 110 is mounted to the first carrier 120 by the heat-sensitive adhesive material 130, 230, and in the detaching step, the heat-sensitive adhesive material 130 is heated or cooled, 230, detaching the first carrier 120 from the first device group 110; or/and, the second device group 210 is mounted to the second carrier 220 by the thermosensitive adhesive material 130, 230, in the detaching step, heating or cooling the thermal The bonding material 130, 230 disengages the second carrier 220 from the second device group 210.
  • the first device group 110 or the second device group 210 may be pasted with a heat sensitive material, or the first device group 110 and the second device group 210 may be pasted together as needed, and when heated or cooled, the first carrier 120 is detached, or The second carrier 220 is detached, or the first carrier 120 and the second carrier 220 are simultaneously detached, in preparation for the wiring step.
  • an intermediate layer 500 is disposed between the first carrier 120 and the second carrier 220 to distribute the molding material 300 on the first carrier 120 and the intermediate layer 500.
  • the molding material 300 is cured so that the intermediate layer 500 is embedded in the molding material 300 without taking up extra space. Adding the intermediate layer 500 before the molding material 300 is uncured can improve the performance of the integrated circuit system, and can impart different characteristics to the intermediate layer 500 as needed, so that the final high integrated circuit system can obtain better characteristics.
  • the first circuit layer 140 and the second circuit layer 240 are formed on both sides of the substrate, as shown in FIG.
  • connection hole 310 and conductive layer 400 directly connect the first circuit layer 140, the second circuit layer 240, and the base circuit layer 510, but are merely simplified descriptions, and in other embodiments, there may be more complicated wiring possibilities.
  • the connection hole 310 and the conductive layer 400 may connect only the first circuit layer 140, the second circuit layer 240, and the base. Any one or two of the circuit layers 510 are then electrically connected by a plurality of connection holes 310 through the conductive layer 400 on the surface of the substrate, thereby electrically connecting several circuit layers.
  • the pins of the devices of the first device group 110 are oriented toward the first carrier 120, and the pins of the devices of the second device group 210 are oriented toward the second carrier 220.
  • the pins of the device of the first device group 110 and the pins of the device of the second device group 210 are exposed on both sides of the substrate, so that the first circuit layer 140 and the first circuit layer are respectively fabricated on both sides of the substrate.
  • the second circuit layer 240 electrically connects the first circuit layer 140 with the first device group 110 and electrically connects the second circuit layer 240 with the second device group 210.
  • the first circuit layer 140 may be directly formed on the surface of the molding material 300, or after the first circuit layer 140 is disposed on another circuit board, the first device group is electrically connected to the circuit board through the pins of the device.
  • a circuit layer 140; the second circuit layer 240 may be directly formed on the surface of the molding material 300, or the second circuit layer 240 may be disposed on another circuit board, and the second device group is electrically connected through the pins of the device.
  • the second circuit layer 240 of the circuit board is inserted.
  • the first device group 110 and the second device group 210 are embedded in the molding material 300. After curing, the two sides of the molding material 300 are flat, which facilitates superimposing other circuit boards on the side or superimposing a plurality of integrated circuit systems.
  • the first circuit layer 140 is provided with a first connection port, and the device is mounted on the first circuit layer 140 to electrically connect the device with the first connection port; the first circuit layer 140 is reserved with the first connection for expansion.
  • the line port has an extended function, and after the first circuit layer 140 is fabricated, the device can be repositioned according to different needs.
  • the second circuit layer 240 is provided with a second connection port, and the device is mounted on the second circuit layer 240 to electrically connect the device to the second connection port.
  • the second circuit layer 240 is reserved with a second connection port for expansion, and has an expansion function. After the second circuit layer 240 is fabricated, the device can be re-mounted according to different needs, wherein the device can be a chip or an electronic component.
  • the device may be a chip or an electronic component, and the chip includes but is not limited to a die or a chip after the die is packaged.
  • the first device group 110 or/and the second device group 210 includes an ineffective device for equalizing the density of the devices of the first device group 110 or/and the second device group 210 in the molding material 300.
  • the molding material 300 is prevented from warping.
  • the traditional circuit board, the device composition of the first device group and the second device group are often determined by the functions to be implemented, and the size and number may vary greatly. If only effective devices are used, the device materials may be unevenly distributed due to uneven distribution of device materials. There are no sides on the formed substrate The same thermomechanical stress may still be warped during the manufacturing process.
  • an invalid chip is added, and the invalid chip can offset the gap between the different devices and the occupied area, so that the whole The surface of the molding material 300 is balanced by the density occupied by the device to avoid warpage.
  • the first device group 110, or the second device group 210, or the first device group 110 and the second device group 210 may be provided with an invalid chip at the same time.
  • the arrangement positions of the devices of the first device group 110 and the second device group 210 may be pre-designed, and then an invalid device is added, and the position of the invalid device is simulated to facilitate balance and avoid warpage. Invalid devices are not shown in the figure.
  • the at least two first device groups 110 are disposed on the first carrier 120, and the at least two second device groups 210 are disposed on the second carrier 220.
  • the first device group 110, The second device group 210 and the molding material 300 constitute a substrate.
  • the substrate is finally cut into at least two circuit boards.
  • the devices of the first device group 110 and the second device group 210 are first mounted with a plurality of sets of the first device group 110 and the second device group 210 are simultaneously fixedly mounted by the molding material 300, and the connection holes 310 and the conductive layer 400 are simultaneously fabricated. Finally, the board is cut to the required size and the production efficiency is high.
  • the first device group 110 is at least two, and the second device group 210 is at least two, and each circuit board includes at least one first device group 110 or at least one second device group 210. It is also possible to provide only one first device group 110 or only one second device group 210, and the different circuit boards after cutting include a plurality of devices in the first device group 110 or include the second device group 210, respectively. Several devices in .
  • the first device group 110, the second device group 210, and the molding material 300 constitute a substrate.
  • the first circuit layer 140 and the second circuit layer 240 are respectively formed on both sides of the substrate, and the first circuit layer 140 is
  • the first device group 110 is electrically connected to electrically connect the second circuit layer 240 with the second device group 210.
  • the first circuit layer 140, the first device group 110, the second circuit layer 240, and the second device group 210 are electrically connected to expand circuit functions.
  • the first device group 110 When the first device group 110 is disposed on the first carrier 120, the first device group 110 may be electrically connected to each other, and the first circuit layer 140 may be extended to extend the original connection; or the first device group may be used.
  • the second device group 210 may be electrically connected to each other, and the second circuit layer 240 may be extended to extend the original connection; or may be between the second device group 210. Electrical connections are made through the second circuit layer 240 without prior electrical connections.

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Abstract

一种集成电路***及封装方法，其中集成电路***封装方法包括步骤，固化：第一载体（120）和第二载体（220）相对设置，第一载体（120）上的第一器件组（110）和第二载体（220）上的第二器件组（210）均位于第一载体（120）和第二载体（220）之间，在第一载体（120）与第二载体（220）之间设置成型材料（300），第一器件组（110）和第二器件组（210）分别与成型材料（300）接触，固化成型材料（300），使第一器件组（110）和第二器件组（210）分别安装于成型材料（300）的两侧；脱离：将第一载体（120）从第一器件组（110）和成型材料（300）上脱离，将第二载体（220）从第二器件组（210）与成型材料（300）上脱离；连线：在成型材料制作连接孔（310），并制作导电层（400），使导电层（400）伸入连接孔（310），导电层（400）将第一器件组（110）与第二器件组（210）电连接。在集成电路***上可以集成更多功能，生产效率高、成本低。

Description

集成电路***及封装方法 技术领域
本发明属于电子领域，具体涉及一种集成电路***及封装方法。
背景技术
传统的多元件、芯片***封装，一般是按***单元封装。将构成一个***的多个电子元件、芯片倒装或线装于一个表面或内含电路的基板的一侧，然后以模压塑料包封。然后再与其它需要的电子元件、芯片一起焊接或插接到电路板上，形成功能完整的集成电路***。经常需要通过以键合或者倒装的方式连接到基板的电路端口上，再接入到电路板上，各种材料使用量大，工艺复杂，生产成本高；而且使用大量特性各异的材料，也容易在各材料界面诱发多种热机械应力的问题。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种集成电路***及封装方法，可以在集成电路***上集成更多器件、获得更强功能，并且***整体体积小、生产效率高、成本低。
其技术方案如下：
一种集成电路***封装方法，包括步骤：固化：第一载体和第二载体相对设置，所述第一载体上的第一器件组和所述第二载体上的第二器件组均位于所述第一载体和所述第二载体之间，在所述第一载体与所述第二载体之间设置成型材料，所述第一器件组和所述第二器件组分别与所述成型材料接触，固化所述成型材料，使所述第一器件组和所述第二器件组分别安装于所述成型材料的两侧；脱离：将所述第一载体从所述第一器件组和所述成型材料上脱离，将所述第二载体从所述第二器件组与所述成型材料上脱离；连线：在所述成型材料制作连接孔，并制作导电层，使所述导电层伸入所述连接孔，所述导电层将所 述第一器件组与所述第二器件组电连接。
在其中一个实施例中，所述第一器件组通过热敏粘合材料安装于所述第一载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第一载体与所述第一器件组脱离；或/和，所述第二器件组通过热敏粘合材料安装于所述第二载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第二载体与所述第二器件组脱离。
在其中一个实施例中，集成电路***封装方法还包括：在所述固化步骤中，在所述第一载体和所述第二载体之间设置中间层，使所述成型材料分布于所述第一载体与所述中间层之间、以及所述第二载体与所述中间层之间，固化所述成型材料，使所述中间层嵌设于所述成型材料内。
在其中一个实施例中，所述中间层为柔性电路板；或者，将至少两层柔性电路板层叠设置构成所述中间层；或者，所述中间层板为屏蔽层；或者，所述中间层本身构成电子元件，将所述中间层与所述第一器件组或所述第二器件电连接。
在其中一个实施例中，所述中间层设有基电路层，将所述基电路层与所述第一器件组电连接、或将所述基电路层与所述第二器件组电连接。
在其中一个实施例中，所述成型材料为有机硅模压塑料、或模压树脂。
在其中一个实施例中，集成电路***封装方法还包括：所述第一器件组、所述第二器件组、以及所述成型材料构成基板，在所述脱离步骤之后，在所述基板的两侧分别制作第一电路层、第二电路层，将所述第一电路层与所述第一器件组电连接，将所述第二电路层与所述第二器件组电连接。
在其中一个实施例中，第一器件组的器件的引脚朝向所述第一载体，所述第二器件组的器件的引脚朝向所述第二载体。
在其中一个实施例中，所述第一电路层设有第一连线端口，在所述第一电路层贴装器件，使器件与所述第一连线端口电连接；或者，所述第二电路层设有第二连线端口，在所述第二电路层贴装器件，使器件与所述第二连线端口电连接。
在其中一个实施例中，集成电路***封装方法还包括：在所述固化步骤前，在所述第一载体上制作第一电路层，在第一电路层上设置第一器件组，所述第一电路层与所述第一器件组电连接；在所述脱离步骤中，所述第一电路层和所述第一器件组均与所述第一载体相脱离，所述第一电路层和所述第一器件组共同安装于所述成型材料上；或/和，在所述固化步骤前，在所述第二载体制作第二电路层，在第二电路层上设置第二器件组，述第二电路层与所述第二器件组电连接；在所述脱离步骤中，所述第二电路层和所述第二器件组均与所述第一载体相脱离，所述第二电路层和所述第二器件组共同安装于所述成型材料上。
在其中一个实施例中，所述第一器件组、所述第二器件组、以及所述成型材料构成基板，所述基板的面积大于10000平方厘米。
在其中一个实施例中，所述第一器件组或/和所述第二器件组中包括无效器件，所述无效器件用于使所述第一器件组或/和所述第二器件组的器件在所述成型材料分布的密度均衡、避免成型材料发生翘曲。
在其中一个实施例中，所述第一器件组和所述第二器件组在成型材料两侧交错排放，使所述第一器件组和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。
在其中一个实施例中，将至少两个所述第一器件组设置于所述第一载体，将至少两个所述第二器件组设置于所述第二载体，经过所述固化步骤、所述脱离步骤、所述连线步骤后，所述第一器件组、所述第二器件组、和所述成型材料构成基板，将所述基板剪裁为至少两个电路板。
在其中一个实施例中，所述第一器件组包括至少一个器件，所述第二器件组包括至少一个器件，器件为芯片或独立的电子元件。
一种集成电路***，包括：从第一载体脱离下的第一器件组、从第二载体脱离下的第二器件组、以及固化后的成型材料；其中，成型材料位于所述第一器件组和所述第二器件组之间，所述第一器件组和所述第二器件组与所述成型材料接触，所述第一器件组和所述第二器件组分别安装于所述成型材料的两侧，所述成型材料上设有连接孔、以及导电层，所述导电层伸入所述所述连接孔， 所述导电层将所述第一器件组与所述第二器件组电连接。
在其中一个实施例中，所述成型材料为有机硅模压塑料、或模压树脂。
在其中一个实施例中，所述第一器件组、所述第二器件组、以及所述成型材料构成基板，所述基板的两侧分别设有第一电路层、第二电路层，所述第一电路层与所述第一器件组电连接，所述第二电路层与所述第二器件组电连接。
在其中一个实施例中，所述第一电路层设有第一连线端口，所述第一电路层贴装有器件，器件与所述第一连线端口电连接；或者，所述第二电路层设有第二连线端口，所述第二电路层贴装有器件，器件与所述第二连线端口电连接。
在其中一个实施例中，集成电路***还包括：所述第一器件组和所述第二器件组之间设有中间层，所述中间层嵌设于所述成型材料内。
在其中一个实施例中，所述中间层为柔性电路板；或者，至少两层柔性电路板层叠设置构成所述中间层；或者，所述中间层板为屏蔽层；或者，所述中间层本身构成电子元件，将所述中间层与所述第一器件组或所述第二器件电连接。
在其中一个实施例中，所述中间层设有基电路层，将所述基电路层与所述第一器件组电连接、或将所述基电路层与所述第二器件组电连接。
在其中一个实施例中，所述第一器件组包括至少一个器件，所述第二器件组包括至少一个器件，器件为芯片或独立的电子元件。
在其中一个实施例中，所述第一器件组或/和所述第二器件组中包括无效器件，所述无效器件用于使所述第一器件组或/和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。
本发明的有益效果在于：
1、集成电路***封装方法，包括步骤：(1)固化：第一载体和第二载体相对设置，所述第一载体上的第一器件组和所述第二载体上的第二器件组均位于所述第一载体和所述第二载体之间，在所述第一载体与所述第二载体之间设置成型材料，所述第一器件组和所述第二器件组分别与所述成型材料接触，固化所述成型材料，使所述第一器件组和所述第二器件组分别安装于所述成型材 料的两侧；(2)脱离：将所述第一载体从所述第一器件组和所述成型材料上脱离，将所述第二载体从所述第二器件组与所述成型材料上脱离；(3)连线：在所述成型材料制作连接孔，并制作导电层，使所述导电层伸入所述连接孔，所述导电层将所述第一器件组与所述第二器件组电连接。所述导电层伸入连接孔的部分，可以只附着于连接孔的内壁，也可以完全或部分填充连接孔。
传统的只能在电路板单面设置器件，在封装层固化的过程中，因为各种材料热膨胀系数的巨大差异，在芯片与基板的连接处产生很大的热应力，影响芯片***的机械可靠性；为了保证***机械性能，又不得不增强基板的机械性能，导致必须使用较厚的基板，整个***的尺寸因而增大。在较新的扇出***封装技术中，因为需要在大尺寸的面板上对多个***的芯片同时进行工艺处理，在封装层固化的过程中，因为封装层材料、芯片和基板材料热膨胀系数的差异又容易造成面板的翘曲，严重影响工艺的良率，限制了可能实现的线宽精度。本发明中可以不使用基板，在成型材料的两面分别设有第一器件组、第二器件组，容纳的器件大幅增加，并且两面的器件通过连接孔可以相互电连接，器件之间可以在两面的表面上通过的连接点增加，传输带宽、运算速度提高，获得很高的***集成度。并且，采用连接孔的方式将成型材料两侧的器件电连接，连接孔开设于成型材料内，不占用额外的空间；特别是，对于超薄电路板、柔性电路板、可穿戴设备的电路板等，采用本发明的方法，能够很好地保持所获得的集成电路***的整体具有超薄、柔性的特性。
固化后的成型材料起到支撑、固定的作用，固化成型材料的过程中就将第一器件组第二器件组同时安装于成型材料上，在成型材料的两个外表面对称地放置器件组器件，可以降低热机械应力，这对在大尺寸面板上进行平行处理的意义重大。
传统***封装工艺会将器件在载体上重排成大尺寸的面板或晶圆，然后放置成型材料包封，待成型材料固化后再将包含所有器件的成型材料整体脱离，并作为新的基片进行后序工艺。因为器件材料硅与成型材料存在很大的热机械性能差异，固化脱离载体后，基片会产生较大翘曲，严重影响后序工艺的实施。 本发明中，将第一器件组与第二器件组分别安装于成型材料的两侧，并尽量保持两侧器件密度均衡对称，这样可以有效减少在成型材料固化之后所形成基片的翘曲。
并且，将第一器件组、第二器件组设于第一载体、第二载体上，在大面积的面板上流水化作业，涉及的工艺简单，生产效率高。而且使用第一载体、第二载体，可以保证脱离后成型材料的两个外表面平整，可以进行后序工艺，而不需要额外的表面平整化处理。
2、所述第一器件组通过热敏粘合材料安装于所述第一载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第一载体与所述第一器件组脱离；或/和，所述第二器件组通过热敏粘合材料安装于所述第二载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第二载体与所述第二器件组脱离。根据需要，可以采用热敏材料粘贴第一器件组、或第二器件组、或同事粘贴第一器件组和第二器件组，当加热或冷却时，第一载体脱离、或第二载体脱离、或第一载体和第二载体同时脱离，为连线步骤做准备。使用热敏材料可降低脱离步骤的机械应力，不至顺坏损坏器件组或划伤脱离表面。
3、在所述固化步骤中，在所述第一载体和所述第二载体之间设置中间层，使所述成型材料分布于所述第一载体与所述中间层之间、以及所述第二载体与所述中间层之间，固化所述成型材料，使所述中间层嵌设于所述成型材料内，不占用额外的空间。在成型材料未固化之前加入中间层，可以提高集成电路***的性能，根据需要，可以赋予中间层不同的特性，使得最终的高集成电路***获得更好的特性，例如，中间层可以是电路层的载体，电连接后可以提高集成电路***的集成度。
4、所述中间层为柔性电路板；或者，将至少两层柔性电路板层叠设置构成所述中间层；在成型材料之间设置电路板为中间层，扩展整个集成电路***的功能。采用柔性电路层、并采用本发明的集成电路***封装方法，可以做的很薄，最终获得的***整体仍然可以保持柔性的性能。
或者，所述中间层板为屏蔽层；避免成型材料两侧的第一器件组、第二器 件组工作不相互干扰，保证整个集成电路***的工作性能。
或者，所述中间层本身构成电子元件，将所述中间层与所述第一器件组或所述第二器件电连接。包括但不限于天线、电容等，可以扩展电路功能，有不占据额外的空间。
5、所述中间层设有基电路层，在连线的步骤，通过连接孔可以将所述基电路层与所述第一器件组电连接、或/和将所述基电路层与所述第二器件组电连接。第一器件组、第二器件组、中间层类似于多层电路，可以增加电路功能。所述基电路层可以设于中间层朝向第一器件组的一面、或者朝向第二器件组的一面、或者嵌设于中间层内、或者中间层的两面均设有电路层。
6、所述成型材料为可模压成型的封装材料，如有机硅模压塑料(R2SiOx)或模压树脂，包括但不限于聚酰亚胺、或聚二甲基硅氧烷、或聚对二甲苯。这些材料具有良好的流动性，可以填充布满第一载体和第二载体之间的间隙，并且固化操作简单，利于生产。
7、还包括：所述第一器件组、所述第二器件组、以及所述成型材料在固化成型后构成基板，在所述脱离步骤之后，在所述基板的两侧分别制作第一电路层、第二电路层，将所述第一电路层与所述第一器件组电连接，将所述第二电路层与所述第二器件组电连接。第一电路层、第一器件组、第二电路层、第二器件组电连接，扩展电路功能。根据需要，将第一器件组设置于第一载体时，可以是第一器件组之间预先存在部分电连接，增加第一电路层可以扩展原有的连接；也可以是第一器件组之间预先没有电连接，通过第一电路层实现电连接。将第二器件组设置于第二载体时，可以是第二器件组之间预先存在部分电连接，增加第二电路层可以扩展原有的连接；也可以是第二器件组之间预先没有电连接，通过第二电路层实现电连接。
8、第一器件组的器件的引脚朝向所述第一载体，所述第二器件组的器件的引脚朝向所述第二载体。这样在脱离步骤后，所述器件的引脚就会自然暴露在所述基板的两侧，便于在所述基板的两侧分别制作第一电路层、第二电路层，将所述第一电路层与所述第一器件组电连接，将所述第二电路层与所述第二器 件组电连接。这样，第一电路层可以是在成型材料表面直接制作，也可以将第一电路层设于另一电路板后，将第一器件组通过所述器件的引脚电连接入所述电路板的第一电路层；第二电路层可以是在成型材料表面直接制作，也可以将第二电路层设于另一电路板后，将第二器件组通过所述器件的引脚电连接入所述电路板的第二电路层。
9、在所述固化步骤前，在所述第一载体上制作第一电路层，在第一电路层上设置第一器件组，所述第一电路层与所述第一器件组电连接；在所述脱离步骤中，所述第一电路层和所述第一器件组均与所述第一载体相脱离，所述第一电路层和所述第一器件组共同安装于所述成型材料上；或/和，在所述固化步骤前，在所述第二载体制作第二电路层，在第二电路层上设置第二器件组，述第二电路层与所述第二器件组电连接；在所述脱离步骤中，所述第二电路层和所述第二器件组均与所述第一载体相脱离，所述第二电路层和所述第二器件组共同安装于所述成型材料上。
上述“或/和”表示，根据需要，可以采用上述方法单独制作第一电路层、或单独制作第二电路层、或同时制作第一电路层和第二电路层。例如，同时制作第一电路层和第二电路层的方法为：在各第一载体、第二载体上放置所述第一器件组、所述第二器件组之前，第一载体、第二载体上已分别预先设有第一电路层、第二电路层，分别对应为第一器件组、第二器件组，放置的过程包括将第一器件组、第二器件组分别对准接入第一电路层、第二电路层，使第一电路层与所述第一器件组电连接，所述第二电路层与所述第二器件组电连接。在通过适当热或化学处理固定电连接之后，继续完成所述固化、脱离和连线的步骤，只是不再必须在脱离后所形成的基板的两侧外表面制作额外的电路层，只需制作连接第一电路层、第二电路层的连接孔。在这种情况下，粘合材料会设在所述第一载体、第二载体和第一电路层、第二电路层之间，这样脱离后，第一电路层、第二电路层会保留在所形成的基板两个外表面。这种制作方法，在成型材料固化前制作电路层，在一般来说比成型材料平整和坚固得多的第一载体、第二载体表面制作第一电路层、第二电路层，可以更容易制作较细线宽线 距的布线，可以提高数据通讯的带宽和速度；因为在成型材料固化前就固定了电连接，就可避免在固化过程中芯片相对位置的漂移，造成电路层电连接的巨大困难。
10、所述第一电路层设有第一连线端口，在所述第一电路层贴装器件，使器件与所述第一连线端口电连接；第一电路层预留有用于扩展的第一连线端口，具备扩展功能，可以在制作第一电路层之后，根据不同的需要再贴装器件，其中器件可以是芯片或者电子元件。
或者，所述第二电路层设有第二连线端口，在所述第二电路层贴装器件，使器件与所述第二连线端口电连接。第二电路层预留有用于扩展的第二连线端口，具备扩展功能，可以在制作第二电路层之后，根据不同的需要再贴装器件，其中器件可以是芯片或者电子元件。所述芯片为裸片、或者将裸片封装后的芯片。
11、所述第一器件组包括至少一个器件，所述第二器件组包括至少一个器件，器件为芯片或独立的电子元件。完成一次制作流程，就可以同时完成芯片、电子元件的安装，效率高。第一器件组、第二器件组包含一个以上的器件，同一组的器件均设置于载体上，经过固化、脱离、连线的步骤统一安装、并行处理，效率高。
12、将至少两个所述第一器件组设置于所述第一载体，将至少两个所述第二器件组设置于所述第二载体，经过所述固化步骤、所述脱离步骤、所述连线步骤后，所述第一器件组、所述第二器件组、和所述成型材料构成基板，将所述基板剪裁为至少两个电路板。先将第一器件组、第二器件组的器件安装好多组第一器件组、第二器件组同时被成型材料固定安装，并且同时制作连接孔和导电层，最后再裁剪为所需大小的电路板，生产效率高。
可以是，所述第一器件组为至少两个，所述第二器件组为至少两个，每个所述电路板包括至少一个所述第一器件组或至少一个所述第二器件组。也可以是，只设置一个所述第一器件组或只设置一个第二器件组，根据需要，裁剪后的不同电路板分别包含第一器件组中的若干器件、或包含第二器件组中的若干 器件。
13、所述基板的面积大于10000平方厘米。按照本发明的集成电路***封装结构和方法，可以制作大平面电路板，避免翘曲，保证大平面电路板的性能，同时可以降低制作大平面的电路板的成本。可以制成大尺寸级别的、由第一器件组、第二器件组和成型材料构成的基板，并且同时避免了大尺寸级别的基板发生翘曲，保证在大基板上继续后序工艺的可能和质量，降低制作成本。
14、所述第一器件组或/和所述第二器件组中包括无效器件，所述无效器件用于使所述第一器件组或/和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。第一器件组和第二器件组的器件构成往往由要实现的功能确定，大小、尺寸和数量可能差异很大，如果只使用有效器件，可能会因为器件材料分布不均导致在所形成的基板两侧有不同的热机械应力，在制作过程中可能还是有翘曲。根据需要，可以单独在第一器件组设置无效器件、或者单独在第二器件组设置无效器件、或者同时在第一器件组和第二器件组设置无效器件。本发明中，除了设置第一器件组、第二器件组实现整个***的电路功能之外，还加入了无效芯片，无效芯片可以抵消不同器件之间的体积、占据面积的差距，使整个成型材料表面被器件占据的密度均衡，进一步减少翘曲，降低制作工艺的难度，提高布线电路层的制作精度。特别是对于大尺寸级别的基板，使用无效器件可以大幅减少大尺寸基板在制作过程中可能的翘曲。
15、所述第一器件组和所述第二器件组在成型材料两侧交错排放，使所述第一器件组和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。在成型材料表面交错排放器件组来避免所形成的大尺寸基板在制作过程中可能的翘曲。第一器件组和第二器件组的器件构成往往由要实现的功能确定，大小尺寸和数量可能差异很大，如果只使用有效器件，随着所形成的基板尺寸增大，放置的器件组数量增大，如果只是在所述基板的同侧放置同一器件组，因为器件材料分布不均导致在所形成的基板两侧有不同的热机械应力也随之增大，在制作过程中所述基板的翘曲度也会增大。在本发明中，可以采用在第一载体、第二载体上交错排放第一器件组和第二器件组，这样在 最终形成的所述基板两侧的器件密度更加均衡，第一载体、第二载体脱离后基板两侧所受应力更加对称，也就更不容易产生翘曲。可以减少所形成的大尺寸基板在制作过程中的翘曲，降低制作工艺的难度，提高布线电路层的制作精度。
附图说明
图1为本发明实施例中芯片封装方法的结构示意图一；
图2为本发明实施例中芯片封装方法的结构示意图二；
图3为本发明实施例中芯片封装方法的结构示意图三；
图4为本发明实施例中芯片封装方法的结构示意图四；
图5为本发明实施例中芯片封装方法的结构示意图五；
图6为本发明实施例中芯片封装方法的结构示意图六；
图7为本发明实施例中芯片封装方法的结构示意图七；
图8为本发明实施例中芯片封装方法的结构示意图八；
图9为本发明实施例中芯片封装方法的结构示意图九。
附图标记说明：
110、第一器件组，120、第一载体，130、230、热敏粘合材料，140、第一电路层，210、第二器件组，220、第二载体，240、第二电路层，300、成型材料，310、连接孔，400、导电层，500、中间层，510、基电路层。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
集成电路***包括：如图1至6所示，从第一载体120脱离下的第一器件组110、从第二载体220脱离下的第二器件组210、以及固化后的成型材料300；其中，成型材料300位于第一器件组110和第二器件组210之间，第一器件组110和第二器件组210与成型材料300接触，第一器件组110和第二器件组210分别安装于成型材料300的两侧，成型材料300上设有连接孔310、以及导电层400，导电层400伸入连接孔310，导电层400将第一器件组110与第二器件 组210电连接。伸入连接孔310的导电层400可以只附着在连接孔310的内壁，也可以将连接孔310完全或部分填充。其中，导电层400只附着在连接孔310的内壁的情况如图7所示。
如6图所示，第一器件组110、第二器件组210、以及成型材料300构成基板，基板的两侧分别设有第一电路层140、第二电路层240，第一电路层140与第一器件组110电连接，第二电路层240与第二器件组210电连接。
第一载体120和第二载体220之间设有中间层500，中间层500嵌设于成型材料300内。中间层500设有基电路层510，将基电路层510与第一器件组110电连接、或将基电路层510与第二器件组210电连接。可以在中间层500的两面均设置基电路层510、或者自在其中一侧面设置基电路层510。第一器件组110、第二器件组210、中间层500类似于多层电路，可以增加电路功能。基电路层510可以设于中间层500朝向第一器件组110的一面、或者朝向第二器件组210的一面、或者嵌设于中间层500内、或者中间层500的两面均设有电路层。不限于本实施例，还可以是，中间层500为柔性电路板；或者，将至少两层柔性电路板层叠设置构成中间层500；在成型材料300之间设置电路板为中间层500，扩展整个集成电路***的功能。采用柔性电路层、并采用本发明的集成电路***封装方法，可以做得很薄，最终获得的***整体仍然可以保持柔性的性能。或者，中间层500板为屏蔽层；避免成型材料300两侧的第一器件组110、第二器件组210相互干扰，保证整个集成电路***的工作性能。或者，中间层500本身构成电子元件，将中间层500与第一器件组110或第二器件电连接。包括但不限于天线、电容等，可以扩展电路功能，有不占据额外的空间。
根据需要，成型材料300为可模压成型的封装材料，如有机硅模压塑料(R2SiOx)或模压树脂，包括但不限于聚酰亚胺、或聚二甲基硅氧烷、或聚对二甲苯。这些材料具有良好的流动性，可以填充布满第一载体120和第二载体220之间的间隙，并且固化操作简单，利于生产。
此外，第一电路层140设有第一连线端口，第一电路层140贴装有器件， 器件与第一连线端口电连接；或者，第二电路层240设有第二连线端口，第二电路层240贴装有器件，器件与第二连线端口电连接。第一连线端口和第二连线端口未在图中示出。
第一器件组110包括至少一个器件，第二器件组210包括至少一个器件，器件为芯片或独立的电子元件。其中，电子元件包括但不限于店主、电容、电感、三极管、二极管。完成一次制作流程，就可以同时完成芯片、电子元件的安装，效率高。第一器件组110、第二器件组210包含一个以上的器件，同一组的器件均设置于载体上，经过固化、脱离、连线的步骤统一安装、并行处理，效率高。
第一器件组110或/和第二器件组210中包括无效器件，无效器件用于使第一器件组110或/和第二器件组210的器件在成型材料300分布的密度均衡、避免成型材料300发生翘曲。
基板的面积大于10000平方厘米。按照本发明的集成电路***封装方法，可以制成大平面电路板，避免翘曲，保证在大基板上继续后序工艺的可能和质量，降低制作成本。
集成电路***封装方法的主要步骤包括：
(1)固化：如图2所示，第一载体120和第二载体220相对设置，第一载体120上的第一器件组110和第二载体220上的第二器件组210均位于第一载体120和第二载体220之间；如图3所示，在第一载体120与第二载体220之间设置成型材料300；如图4所示，第一器件组110和第二器件组210分别与成型材料300接触，固化成型材料300，使第一器件组110和第二器件组210分别安装于成型材料300的两侧；
(2)脱离：如图5所示，将第一载体120从第一器件组110和成型材料300上脱离，将第二载体220从第二器件组210与成型材料300上脱离；
(3)连线：如图6所示，在成型材料300制作连接孔310；如图7所示，并制作导电层400，使导电层400伸入连接孔310，导电层400将第一器件组 110与第二器件组210电连接。伸入连接孔310的导电层400可以只附着在连接孔310的内壁，也可以将连接孔310完全或部分填充。
传统的电路板只在单面设置器件，本发明中成型材料300的两面分别设有第一器件组110、第二器件组210，容纳的器件大幅增加，并且两面的器件通过连接孔310可以电连接，连接点增加，传输带宽、运算速度提高，获得的集成电路***性能高。并且，采用连接孔310的方式将成型材料300两侧的器件电连接，连接孔310开设于成型材料300内，不占用额外的空间；特别是，对于超薄电路板、柔性电路板、可穿戴设备的电路板等，采用本发明的方法，能够很好地保持集成电路***超薄、柔性特性。
根据需要，可以选择，如图1至4所示，第一器件组110通过热敏粘合材料130、230安装于第一载体120，在脱离步骤中，加热或冷却热敏粘合材料130、230，使第一载体120与第一器件组110脱离；或/和，第二器件组210通过热敏粘合材料130、230安装于第二载体220，在脱离步骤中，加热或冷却热敏粘合材料130、230，使第二载体220与第二器件组210脱离。根据需要，可以采用热敏材料粘贴第一器件组110、或第二器件组210、或同时粘贴第一器件组110和第二器件组210，当加热或冷却时，第一载体120脱离、或第二载体220脱离、或第一载体120和第二载体220同时脱离，为连线步骤做准备。
当需要设置中间层500时，在固化步骤中，如8图所示，在第一载体120和第二载体220之间设置中间层500，使成型材料300分布于第一载体120与中间层500之间、以及第二载体220与中间层500之间，固化成型材料300，使中间层500嵌设于成型材料300内，不占用额外的空间。在成型材料300未固化之前加入中间层500，可以提高集成电路***的性能，根据需要，可以赋予中间层500不同的特性，使得最终的高集成电路***获得更好的特性。然后在基板两侧别制作第一电路层140、第二电路层240，如图9所示。图示的连接孔310及导电层400直接连接第一电路层140、第二电路层240，以及基电路层510，只是过于简化的说明，在其他实施例中可以有更多复杂的布线可能。所述连接孔310及导电层400可以只连接第一电路层140、第二电路层240、基 电路层510其中任一或两个电路层，然后再通过在基板表面的导电层400将多个连接孔310电连接，于是将几个电路层电连接。
如图7、9所示，第一器件组110的器件的引脚朝向第一载体120，第二器件组210的器件的引脚朝向第二载体220。这样在脱离步骤后，第一器件组110的器件的引脚和第二器件组210的器件的引脚就会暴露于基板两侧，便于在基板的两侧分别制作第一电路层140、第二电路层240，将第一电路层140与第一器件组110电连接，将第二电路层240与第二器件组210电连接。第一电路层140可以是在成型材料300表面直接制作，也可以将第一电路层140设于另一电路板后，将第一器件组通过所述器件的引脚电连接入电路板的第一电路层140；第二电路层240可以是在成型材料300表面直接制作，也可以将第二电路层240设于另一电路板后，将第二器件组通过所述器件的引脚电连接入所述电路板的第二电路层240。进一步地，第一器件组110、第二器件组210嵌入成型材料300内，固化后成型材料300两个侧面平整，利于在侧面上叠加其他电路板，或者将多个集成电路***叠加。
此外，第一电路层140设有第一连线端口，在第一电路层140贴装器件，使器件与第一连线端口电连接；第一电路层140预留有用于扩展的第一连线端口，具备扩展功能，可以在制作第一电路层140之后，根据不同的需要再贴装器件。或/和，第二电路层240设有第二连线端口，在第二电路层240贴装器件，使器件与第二连线端口电连接。第二电路层240预留有用于扩展的第二连线端口，具备扩展功能，可以在制作第二电路层240之后，根据不同的需要再贴装器件，其中器件可以是芯片或者电子元件。其中，器件可以是芯片或者电子元件，芯片包括但不限于裸片、或者将裸片封装后的芯片。
此外，第一器件组110或/和第二器件组210中包括无效器件，所述无效器件用于使第一器件组110或/和第二器件组210的器件在成型材料300分布的密度均衡、避免成型材料300发生翘曲。传统的电路板，第一器件组和第二器件组的器件构成往往由要实现的功能确定，大小尺寸和数量可能差异很大，如果只使用有效器件，可能会因为器件材料分布不均导致在所形成的基板两侧有不 同的热机械应力，在制作过程中可能还是有翘曲。本发明中，除了设置第一器件组110、第二器件组210实现整个***的电路功能之外，还加入了无效芯片，无效芯片可以抵消不同器件之间的体积、占据面积的差距，使整个成型材料300表面被器件占据的密度均衡，避免发生翘曲。可以是第一器件组110、或第二器件组210、或第一器件组110和第二器件组210同时设有无效芯片。可以预先设计第一器件组110、第二器件组210的器件的排布位置，然后加入无效器件，对无效器件的位置进行模拟设计，以利于获得平衡、避免产生翘曲。无效器件未在图中示出。
将至少两个第一器件组110设置于第一载体120，将至少两个第二器件组210设置于第二载体220，经过固化步骤、脱离步骤、连线步骤后，第一器件组110、第二器件组210、和成型材料300构成基板，在完成固化、脱离、连线、第一和第二电路层240的制作等工序后，最后将基板剪裁为至少两个电路板。如此，先将第一器件组110、第二器件组210的器件安装好多组第一器件组110、第二器件组210同时被成型材料300固定安装，并且同时制作连接孔310和导电层400，最后再裁剪为所需大小的电路板，生产效率高。
第一器件组110为至少两个，第二器件组210为至少两个，每个电路板包括至少一个第一器件组110或至少一个第二器件组210。也可以是，只设置一个第一器件组110或只设置一个第二器件组210，根据需要，裁剪后的不同电路板分别包含第一器件组110中的若干器件、或包含第二器件组210中的若干器件。
第一器件组110、第二器件组210、以及成型材料300构成基板，在脱离步骤之后，在基板的两侧分别制作第一电路层140、第二电路层240，将第一电路层140与第一器件组110电连接，将第二电路层240与第二器件组210电连接。第一电路层140、第一器件组110、第二电路层240、第二器件组210电连接，扩展电路功能。根据需要，将第一器件组110设置于第一载体120时，可以是第一器件组110之间相互电连接，增加第一电路层140可以扩展原有的连接；也可以是第一器件组110之间预先没有电连接，通过第一电路层140实 现电连接。将第二器件组210设置于第二载体220时，可以是第二器件组210之间相互电连接，增加第二电路层240可以扩展原有的连接；也可以是第二器件组210之间预先没有电连接，通过第二电路层240实现电连接。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (24)

  1. 一种集成电路***封装方法，其特征在于，包括步骤：
    固化：第一载体和第二载体相对设置，所述第一载体上的第一器件组和所述第二载体上的第二器件组均位于所述第一载体和所述第二载体之间，在所述第一载体与所述第二载体之间设置成型材料，所述第一器件组和所述第二器件组分别与所述成型材料接触，固化所述成型材料，使所述第一器件组和所述第二器件组分别安装于所述成型材料的两侧；
    脱离：将所述第一载体从所述第一器件组和所述成型材料上脱离，将所述第二载体从所述第二器件组与所述成型材料上脱离；
    连线：在所述成型材料制作连接孔，并制作导电层，使所述导电层伸入所述连接孔，所述导电层将所述第一器件组与所述第二器件组电连接。
  2. 根据权利要求1所述的集成电路***封装方法，其特征在于，所述第一器件组通过热敏粘合材料安装于所述第一载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第一载体与所述第一器件组脱离；
    或/和，所述第二器件组通过热敏粘合材料安装于所述第二载体，在所述脱离步骤中，加热或冷却所述热敏粘合材料，使所述第二载体与所述第二器件组脱离。
  3. 根据权利要求1所述的集成电路***封装方法，其特征在于，还包括：在所述固化步骤中，在所述第一载体和所述第二载体之间设置中间层，使所述成型材料分布于所述第一载体与所述中间层之间、以及所述第二载体与所述中间层之间，固化所述成型材料，使所述中间层嵌设于所述成型材料内。
  4. 根据权利要求3所述的集成电路***封装方法，其特征在于，所述中间层为柔性电路板；或者，将至少两层柔性电路板层叠设置构成所述中间层；
    或者，所述中间层板为屏蔽层；
    或者，所述中间层本身构成电子元件，将所述中间层与所述第一器件组或所述第二器件电连接。
  5. 根据权利要求3所述的集成电路***封装方法，其特征在于，所述中间层设有基电路层，将所述基电路层与所述第一器件组电连接、或将所述基电 路层与所述第二器件组电连接。
  6. 根据权利要求1所述的集成电路***封装方法，其特征在于，所述成型材料为有机硅模压塑料、或模压树脂。
  7. 根据权利要求1所述的集成电路***封装方法，其特征在于，还包括：所述第一器件组、所述第二器件组、以及所述成型材料构成基板，在所述脱离步骤之后，在所述基板的两侧分别制作第一电路层、第二电路层，将所述第一电路层与所述第一器件组电连接，将所述第二电路层与所述第二器件组电连接。
  8. 根据权利要求7所述的集成电路***封装方法，其特征在于，第一器件组的器件的引脚朝向所述第一载体，所述第二器件组的器件的引脚朝向所述第二载体。
  9. 根据权利要求7所述的集成电路***封装方法，其特征在于，所述第一电路层设有第一连线端口，在所述第一电路层贴装器件，使器件与所述第一连线端口电连接；
    或者，所述第二电路层设有第二连线端口，在所述第二电路层贴装器件，使器件与所述第二连线端口电连接。
  10. 根据权利要求1所述的集成电路***封装方法，其特征在于，还包括：
    在所述固化步骤前，在所述第一载体上制作第一电路层，在第一电路层上设置第一器件组，所述第一电路层与所述第一器件组电连接；在所述脱离步骤中，所述第一电路层和所述第一器件组均与所述第一载体相脱离，所述第一电路层和所述第一器件组共同安装于所述成型材料上；
    或/和，在所述固化步骤前，在所述第二载体制作第二电路层，在第二电路层上设置第二器件组，述第二电路层与所述第二器件组电连接；在所述脱离步骤中，所述第二电路层和所述第二器件组均与所述第一载体相脱离，所述第二电路层和所述第二器件组共同安装于所述成型材料上。
  11. 根据权利要求1至10任一项所述的集成电路***封装方法，其特征在于，所述第一器件组、所述第二器件组、以及所述成型材料构成基板，所述基板的面积大于10000平方厘米。
  12. 根据权利要求11所述的集成电路***封装方法，其特征在于，所述第一器件组或/和所述第二器件组中包括无效器件，所述无效器件用于使所述第一器件组或/和所述第二器件组的器件在所述成型材料分布的密度均衡、避免成型材料发生翘曲。
  13. 根据权利要求11所述的集成电路***封装方法，其特征在于，所述第一器件组和所述第二器件组在成型材料两侧交错排放，使所述第一器件组和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。
  14. 根据权利要求1至10任一项所述的集成电路***封装方法，其特征在于，将至少两个所述第一器件组设置于所述第一载体，将至少两个所述第二器件组设置于所述第二载体，经过所述固化步骤、所述脱离步骤、所述连线步骤后，所述第一器件组、所述第二器件组、和所述成型材料构成基板，将所述基板剪裁为至少两个电路板。
  15. 根据权利要求1至10任一项所述的集成电路***封装方法，其特征在于，所述第一器件组包括至少一个器件，所述第二器件组包括至少一个器件，器件为芯片或独立的电子元件。
  16. 一种集成电路***，其特征在于，包括：从第一载体脱离下的第一器件组、从第二载体脱离下的第二器件组、以及固化后的成型材料；
    其中，成型材料位于所述第一器件组和所述第二器件组之间，所述第一器件组和所述第二器件组与所述成型材料接触，所述第一器件组和所述第二器件组分别安装于所述成型材料的两侧，所述成型材料上设有连接孔、以及导电层，所述导电层伸入所述所述连接孔，所述导电层将所述第一器件组与所述第二器件组电连接。
  17. 根据权利要求16所述的集成电路***，其特征在于，所述成型材料为有机硅模压塑料、或模压树脂。
  18. 根据权利要求16所述的集成电路***，其特征在于，所述第一器件组、所述第二器件组、以及所述成型材料构成基板，所述基板的两侧分别设有 第一电路层、第二电路层，所述第一电路层与所述第一器件组电连接，所述第二电路层与所述第二器件组电连接。
  19. 根据权利要求16所述的集成电路***，其特征在于，所述第一电路层设有第一连线端口，所述第一电路层贴装有器件，器件与所述第一连线端口电连接；
    或者，所述第二电路层设有第二连线端口，所述第二电路层贴装有器件，器件与所述第二连线端口电连接。
  20. 根据权利要求16所述的集成电路***，其特征在于，还包括：所述第一器件组和所述第二器件组之间设有中间层，所述中间层嵌设于所述成型材料内。
  21. 根据权利要求20所述的集成电路***，其特征在于，所述中间层为柔性电路板；
    或者，至少两层柔性电路板层叠设置构成所述中间层；
    或者，所述中间层板为屏蔽层；
    或者，所述中间层本身构成电子元件，将所述中间层与所述第一器件组或所述第二器件电连接。
  22. 根据权利要求20所述的集成电路***，其特征在于，所述中间层设有基电路层，将所述基电路层与所述第一器件组电连接、或将所述基电路层与所述第二器件组电连接。
  23. 根据权利要求16至22任一项所述的集成电路***，其特征在于，所述第一器件组包括至少一个器件，所述第二器件组包括至少一个器件，器件为芯片或独立的电子元件。
  24. 根据权利要求16至22任一项所述的集成电路***，其特征在于，所述第一器件组或/和所述第二器件组中包括无效器件，所述无效器件用于使所述第一器件组或/和所述第二器件组的器件在所述成型材料两侧分布的密度均衡、避免成型材料发生翘曲。
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